WO2003003473A1

WO2003003473A1 - Nonvolatile semiconductor memory cell and semiconductor memory and method for fabricating nonvolatile semiconductor memory

Info

Publication number: WO2003003473A1
Application number: PCT/JP2001/005544
Authority: WO
Inventors: Renichi Yamada; Tomoko Sekiguchi; Yuki Mori
Original assignee: Hitachi, Ltd.
Priority date: 2001-06-28
Filing date: 2001-06-28
Publication date: 2003-01-09
Also published as: JPWO2003003473A1

Abstract

A nonvolatile semiconductor memory cell comprising a substrate, a source region and a drain region formed in the surface of the substrate, a channel region formed in the surface of the substrate between the source region and the drain region, an insulating film so formed as to cover the channel region, and a gate electrode formed above the insulating film, wherein the insulating film constitutes a charge storage section and the trap level thereof is set up using a trap level set-up means in addition to an insulating film forming means. Furthermore, variation in the memory characteristics of a nonvolatile memory which retains memory by trapping charge in a gate insulation insulator can be suppressed using an enhancement transistor. A nonvolatile memory can thereby be produced inexpensively with high yield.

Description

Description Non-volatile semiconductor storage element and semiconductor storage device

The present invention relates to a nonvolatile semiconductor memory device and a semiconductor memory device. Background art

Currently, mass-produced nonvolatile semiconductor memory devices are mainly flash memories having a floating gate between a substrate and a control gate. Flash memory requires a floating gate, which complicates the structure and makes it difficult to reduce production costs. The complexity of this structure is also disadvantageous in terms of obtaining high production yields. In addition, low power consumption and low drive voltage are required for the application of nonvolatile semiconductor memory devices to portable equipment in recent years. However, from this point of view, the flash memory has a disadvantage that a high voltage of about 2 OV is required for rewriting since the flash memory has a structure in which two layers of gate insulating films are stacked above and below the floating gate.

In contrast to the flash memory, there is a nonvolatile semiconductor memory device having a transistor having a metal-oxide-nitride-oxide-semiconductor (hereinafter, referred to as “MONOS”) structure that does not require a floating gate as a storage portion. Such a MONOS semiconductor memory device has a simple structure because it has no floating gate.

On the other hand, a nonvolatile semiconductor memory device having a metal-oxide-semiconductor (hereinafter, referred to as “MOS”) structure has been proposed in contrast to the above-mentioned two nonvolatile semiconductor memory devices. Such examples can be found in, for example, Japan, Patent Publication, Japanese Patent Application Laid-Open Nos. H11-134870 and H5-112765. In the nonvolatile semiconductor memory device, nonvolatile storage is realized by capturing charges in an oxide. In such a nonvolatile semiconductor memory device, the storage element can be manufactured in the same process as the peripheral circuit. Therefore, it can be manufactured at a lower cost as compared with the above-mentioned 2 nonvolatile semiconductor memory device.

However, in a non-volatile semiconductor memory device having a MOS structure, since the trap in the oxide film is a charge holding site, it is difficult to control the amount of held charge. For example, when a semiconductor memory device is used in a binary system, in the storage state, the threshold voltage becomes lower than necessary in a state where the absolute value of the threshold voltage is lower (hereinafter referred to as “low V th state”). And read failure.

On the other hand, in a MONOS-type nonvolatile semiconductor memory device in which a similar problem is considered to occur, a technology has been invented in which an enhancement transistor is formed for each memory transistor to prevent a reading failure. And Japanese Patent Application Laid-Open Publication No. Hei 6-232314. Disclosure of the invention

The present invention provides a MOS type nonvolatile semiconductor memory element in which the influence of threshold voltage variation is reduced, and a nonvolatile semiconductor memory device using the same. In particular, the present invention provides a method for controlling traps (t ra p) in an oxide film, which is a cause of threshold voltage variation in the first place. Further, the present invention provides a method for easily manufacturing an enhancement transistor as a technique for eliminating the influence of threshold voltage variation of a nonvolatile semiconductor memory device.

First, a MOS type non-volatile semiconductor storage element capable of performing a stable storage operation will be described.

According to a first aspect of the present invention, there is provided a substrate, a source region and a drain region provided on a surface portion of the substrate, a channel region provided on a surface portion of the substrate between the source region and the drain region, and the channel region. And at least a gate electrode formed on the insulating film, wherein the insulating film constitutes a charge storage portion, and a trap level of the insulating film is: This is a nonvolatile semiconductor memory element formed by requiring trap level forming means in addition to the forming means. Further, if the invention of the present application is referred from another viewpoint, the following can be said. That is, a second aspect of the present invention provides a semiconductor device comprising: a substrate; a source region and a drain region provided on a surface portion of the substrate; a channel region provided on a surface portion of the substrate between the source region and the drain region; At least a gate electrode formed above the insulating film, the insulating film forming a charge storage portion, and a trap level of the insulating film. Is a nonvolatile semiconductor memory element that is larger than at least the number of trap levels formed in a thermal oxide film as a usual insulating film. In other words, the trap level of the insulating film formed over the channel region of the transistor in the memory portion is changed by the insulating film formed over the channel region of the transistor in the peripheral circuit portion of the semiconductor memory device. It is larger than the number of trap levels.

FIG. 15 shows the basic configuration of the semiconductor memory device of the present invention. Reference numeral 50 is a substrate, 51 and 52 are a source and a drain, 53 is an insulating film, 54 is a trap, 55 is a gate electrode, and 56 is a carrier captured at a trap level. Is shown. The basic operation of the above-described nonvolatile semiconductor memory device is as follows. That is, by trapping carriers of the same conductivity type as the substrate of the field-effect transistor at the trap (capture) level of carriers formed in the gate insulating film of the MOS field-effect transistor, At the interface between the substrate of the field effect transistor and the gate insulating film, a carrier of a conductivity type opposite to that of the trapped carrier is induced. Therefore, the threshold voltage of the field-effect transistor decreases. Conversely, by trapping the carrier of the opposite conductivity type with the substrate of the field-effect transistor, the carrier trapped on the interface between the substrate of the field-effect transistor and the gate insulating film. A carrier of the same conductivity type is induced. Therefore, the threshold voltage of the field-effect transistor increases. In this way, multiple threshold voltages can be achieved depending on the presence or absence of carriers to be captured. Therefore, by utilizing the difference in current driving force at a desired gate voltage, Information can be stored. Further, by applying a bias to the gate electrode of the field-effect transistor, carriers trapped in the gate insulating film can be released from the trap level and erased. Thus, it is possible to realize a semiconductor memory element capable of electrically writing and erasing information.

In many cases, the insulating film is a silicon oxide film, a silicon nitride film, or a composite film thereof. In the present invention, it is important that these films have more trap levels than the state of the insulating film usually formed. Thus, desired carriers can be captured in a so-called gate insulating film, and a so-called nonvolatile memory element can be operated sufficiently stably. That is, a desired carrier is captured by the trap level, and desired information is stored. Although the present invention is a nonvolatile memory element, it does not require a so-called floating gate. Note that the basic operation such as reading of information is the same as that of the conventional nonvolatile semiconductor memory element, and therefore detailed description is omitted.

As the trap level forming means added to the insulating film forming means, the following method can be used.

(1) After a nonvolatile semiconductor memory device is manufactured by a usual method, a voltage at which a tunnel current is generated, that is, an electrical stress is applied to a gate electrode of the memory device, and a trap level is actively formed. I do. In this case, it is convenient to form what is called electrical stress, which corresponds to the amount of injected charges at which the trap density generated in the insulating film is saturated. This voltage application is preferably performed when the gate electrode has a negative potential. By applying such a high bias stress, it is possible to create traps required for the MOS type nonvolatile memory, but various types of insulating films can be used as the base insulating film. A typical example is shown in (2).

(2) When forming a gate insulating film, the insulating film is formed in a plurality of times. By using a plurality of insulating film forming steps, in particular, trap levels are introduced between these layers. Is entered. As a result, more trap levels can be introduced into the gate insulating film than in a single step of forming the insulating film.

Further, a plurality of different manufacturing methods can be used for forming the insulating film in the plurality of steps. For example, by forming a thermal oxide film and forming an oxide film thereon by the CVD method, more trap levels can be introduced than in forming an insulating film in one step.

(3) The methods (1) and (2) are used in combination. This method can more effectively introduce a trap level at a desired position. Further, according to the embodiment of the present invention, it is possible to control the position of the trap level to be formed, that is, the distance from the substrate interface. Even for the same amount of charge, the amount of change in the threshold voltage varies depending on the trapped position. Therefore, it is preferable to control the position of the trap level to be formed according to the required characteristics.

Next, various embodiments of the nonvolatile semiconductor memory device aiming at higher performance will be described. A typical example of the nonvolatile semiconductor memory device of the present invention is an example in which the nonvolatile semiconductor memory device includes at least a memory transistor section and an enhancement transistor section.

The first feature of the nonvolatile semiconductor memory device according to the present invention is the two-level gate oxide film. That is, the thickness of the gate oxide film is changed from the position corresponding to the source region to the position corresponding to the drain region.

A second typical example of the nonvolatile semiconductor memory device of the present invention is a form in which at least each source and drain of the memory transistor portion and the enhancement transistor portion are commonly configured.

That is, the enhancement transistor is a transistor having a threshold voltage between the low V th and the high V th state of the memory transistor in the memory cell, and the threshold voltage is stable against rewriting of the memory cell. . Then, the enhancement transistor is connected to the source (or drain) of the memory transistor. By connecting the drain (or source) of the transistor, it plays a role in preventing read failure due to Vth variation in the low Vth state of the memory transistor. In order to realize such a state in the MOS nonvolatile memory, it is necessary to realize two kinds of film thicknesses in which the gate oxide film thickness changes from the source to the drain as shown in FIG. In FIG. 1, 1 is a gate electrode, 2 is a semiconductor substrate, 3 is a source, 4 is a drain, 5 and 6 are two types of gate oxide films, 5 is a thin film portion, 6 is a thick film portion, 7 Is an interlayer insulator. In the case of the structure of FIG. 1, the source and the drain may be exchanged. The structure in FIG. 1 has two types of gate oxide films, and as shown in the equivalent circuit in FIG. 2, a structure in which two types of transistors having different threshold voltages are joined by a source and a drain is realized. When a bias is applied to the gate of the transistor such that a tunnel current flows between the gate electrode of the thin film portion 5 of the gate oxide film and the substrate and no tunnel current flows between the gate electrode of the thick film portion 6 and the substrate. However, charge trapping occurs only in the thin film part 5, and charge trapping does not occur in the thick film part 6. That is, only the thin film portion 5 becomes a memory holding region, and the thick film portion 6 becomes an enhancement transistor having a stable threshold voltage.

Further, even if the gate oxide film does not have two thicknesses, the enhancement transistor can be realized by separating the gate electrode into two as shown in FIG. In FIG. 3, 2 is a semiconductor substrate, 3 and 4 are a source and a drain, 5 is a gate oxide film, 8 is a gate electrode of a memory transistor, 9 is a gate electrode of an enhancement transistor, and 7 is an interlayer. It is an insulating film. Fig. 4 shows an equivalent circuit of the structure in Fig. 3. A bias necessary for rewriting operation is applied to the gate electrode 8 of the memory transistor to the MOS nonvolatile memory, and only a bias that does not cause a rewriting operation is applied to the gate electrode 9 of the enhancement transistor. By applying the voltage, a desired operation can be realized.

In the memory cell structure shown in Figs. 1 and 3, the process can be simplified by forming the gate of the peripheral circuit at the same time as forming the gate oxide film. You.

In general, the charge trap density in the oxide film immediately after formation is often insufficient for realizing a MOS nonvolatile memory, and even if the density is sufficient, the trap density between memory cells varies. And it is difficult to control the threshold voltage. As a method for solving this, it is effective to apply an electric stress to the gate oxide film of the memory transistor in advance to make the trap density constant. As shown in Fig. 14, when a bias is applied to the gate of a MOS capacitor and a tunnel current flows, the charge trap density in the oxide film is saturated at a certain value (Q crit). The value does not depend on the initial charge trap density. In other words, a uniform and stable charge trap can be realized by applying an electrical stress corresponding to the amount of injected charge Qcrit to the gate oxide film of the memory cell transistor in advance.

Generally, traps are often generated at the oxide film interface, and the trap is likely to be generated. Therefore, if an oxide film is formed in plural times to form an interface in the film, the trap generation position can be controlled.

Various forms of the nonvolatile semiconductor memory device described above are arranged and listed below. In a first embodiment of the nonvolatile semiconductor memory device, a second conductive type drain region selectively formed on a semiconductor substrate surface on a first conductive type semiconductor substrate, and a predetermined distance from the drain region A source region of the second conductivity type selectively formed on the surface of the semiconductor substrate across the semiconductor substrate, the semiconductor region at least partially overlapping an end of the drain region, and the end of the source region. A storage element including an insulating film having two different thicknesses formed over a substrate and a gate electrode formed over the insulating film is provided. This is a semiconductor memory device that stores information in a state.

In this case, it is useful to apply the above-mentioned method of performing thermal oxidation after forming an oxide film by depositing a thin film portion of the insulating film by CVD (deposition). Further, it is also useful to form the thin film portion of the insulating film by performing thermal oxidation a plurality of times. Further, in such a semiconductor memory device, it is particularly useful to apply an electric stress to the gate electrode to form a trap in the thin film portion of the insulating film. A typical example of a memory array to which the nonvolatile semiconductor memory device described so far is applied is an AND type and a NOR type.

The nonvolatile semiconductor memory device of the first embodiment described above is arranged in n pieces. In the semiconductor memory device, m pieces of semiconductor memory rows in which a source is connected to a source line and a drain is connected to a bit line are arranged, and n pieces are arranged. The gates of the m semiconductor devices are connected to the lead lines of the semiconductor device, and at this time, only one semiconductor storage device belonging to a different row of the semiconductor storage devices is connected to one word line. Semiconductor storage device. Furthermore, the nonvolatile semiconductor memory device is composed of two cells of the first embodiment of the above-mentioned nonvolatile semiconductor memory device, and is composed of n semiconductor memory cells having a structure in which the sources are connected to each other. The source and gate of the m semiconductor memory cells are connected to the source line and the word line, respectively, by connecting m source lines and 2 × n read lines connected to the m rows of the semiconductor memory devices connected to the lines. At this time, this is a NOR type semiconductor memory device in which only one semiconductor memory device belonging to a different semiconductor memory device column is connected to one source line and one gate line.

In a second embodiment of the nonvolatile semiconductor memory device, a second conductive type drain region selectively formed on a surface of the semiconductor substrate on a first conductive type semiconductive substrate; A source region of the second conductivity type selectively formed on the surface of the semiconductor substrate at a distance of at least a distance from the end of the source region; A memory transistor portion and an enhancement transistor portion each including an insulating film having two different thicknesses formed on the semiconductor substrate and a gate electrode formed on the insulating film are provided. The semiconductor memory device has a common source and drain.

The insulating film of this type of memory transistor is deposited by CVD. It is useful to apply the above-described method of performing thermal oxidation after forming an oxide film. Further, it is also useful to form the insulating film of the memory transistor by performing thermal oxidation a plurality of times. Further, in such a semiconductor memory device, it is particularly useful to form a trap in the insulating film of the memory transistor by applying an electric stress to the gate electrode.

A typical NOR type memory array to which the nonvolatile semiconductor memory device shown so far is applied will be exemplified.

That is, the nonvolatile semiconductor memory device is composed of two nonvolatile semiconductor memory devices according to the second embodiment, and has a structure in which n sources of the semiconductor memory device are connected to each other, and 2 × n drains are all connected to the bit lines. An array of m semiconductor memory devices is arranged, and n source lines, 2 × n lead lines, and 2 n memory lines are connected to the m sources of the semiconductor memory device cells and the enhancement transistor transistors. The gate of the transistor and the gate of the transistor are connected to a source line, a word line, and a memory line, respectively, and one source line, a lead line, and a memory line belong to different semiconductor storage device columns. Only a NOR type semiconductor memory device to which only one is connected. As described above, the gate insulating film of the MOS transistor used in the nonvolatile semiconductor element application circuit or the peripheral circuit of the nonvolatile semiconductor device is formed by the same process as the formation of the thin film portion of the memory cell insulating film. It can be manufactured. And this measure is extremely useful in practice. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a schematic sectional view of a cell of a MOS type nonvolatile memory having two types of gate oxide films.

FIG. 2 is a cell equivalent circuit diagram of the MOS nonvolatile memory shown in FIG. FIG. 3 is a schematic cross-sectional view of a cell of a MOS nonvolatile memory having a memory transistor and an enhancement transistor. FIG. 4 is a cell equivalent circuit of the MOS nonvolatile memory shown in FIG. FIG. 5 is an AND type memory array circuit diagram using the MOS type nonvolatile memory cells shown in FIGS. 1 and 2.

FIG. 6 is a schematic cross-sectional view of the element shown in the order of steps for manufacturing the memory array shown in FIG.

FIG. 7 is a schematic plan view of an element shown in the order of steps for manufacturing the memory array shown in FIG.

FIG. 8 is a circuit diagram of a NOR memory array using the MOS nonvolatile memory cells shown in FIGS. 1 and 2.

FIG. 9 is a schematic cross-sectional view of an element shown in the order of steps for manufacturing the memory array shown in FIG.

FIG. 10 is a schematic plan view of an element shown in the order of steps for manufacturing the memory array shown in FIG.

FIG. 11 is a circuit diagram of a NOR type memory array using the MOS type nonvolatile memory cells shown in FIGS. 3 and 4.

FIG. 12 is a schematic cross-sectional view of an element shown in the order of steps for manufacturing the memory array shown in FIG.

FIG. 13 is a schematic plan view of an element shown in the order of steps for manufacturing the memory array shown in FIG.

FIG. 14 is a diagram showing the dependence of the trap density generated in the oxide film on the amount of injected charge when a high bias stress is applied to the MOS capacitor.

FIG. 15 is a sectional view of a main part of the nonvolatile semiconductor memory element of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION

The embodiments of the present invention are various depending on the type of the memory array. Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings by way of specific examples. I do.

Embodiment 1>

FIG. 5 shows a circuit diagram when the memory cells shown in FIGS. 1 and 2 are arranged in an AND memory array. In order to realize the memory array shown in FIG. 5, for example, a process as shown in FIGS. 6 and 7 can be considered. FIG. 6 is a schematic sectional view showing the progress of the process in the order of a to i. FIG. 7 shows a schematic plan view of a part of the process shown in FIG.

First, after forming a gate oxide thin film portion 5 on a semiconductor substrate (FIG. 6A), a part 10 of a gate electrode is formed (FIG. 6B). Again, an oxide film is grown on the substrate to form a gate oxide film portion 6 (FIG. 6, c). After forming the remaining portion 11 of the gate electrode (FIG. 6D), the source and drain 12 are formed using the gate electrode as a mask region (FIG. 6E). Thereafter, a sidewall 13 is formed beside the gate electrode (f in FIG. 6), and a trench 14 for element isolation is formed using this as a mask (g in FIG. 6). An insulator 15 serving as both an element isolation and an interlayer insulator is buried in the groove 14 (h in FIG. 6).

The shapes of the gates 10 and 11 and the sidewalls 13 formed in the steps up to this point are striped. This state is shown as a plan view in FIG. 7a and FIG. 7 when viewed from above in steps g and h in FIG. 6, respectively. Thereafter, a lead line 16 which is in electrical contact with the gate electrode is formed (i in FIG. 6), and is processed into a stripe shape in a direction perpendicular to the element isolation groove (c in FIG. 7). If the processing depth is set within the gate oxide film 5 formed first, the AND type memory array shown in FIG. 5 can be realized.

By applying a high bias stress to the gate oxide film 5 in advance, a trap having a density required for a MOS nonvolatile memory can be formed. Also, when forming the gate oxide film 5, by forming the oxide film a plurality of times and forming an interface in the oxide film, a trap-rich portion can be formed in the oxide film. Further Needless to say, as described above, a plurality of different insulating film manufacturing methods may be combined. That is, a silicon oxide film is manufactured using a CVD method and a thermal oxidation method.

The above-described high bias stress generally uses the following method. As described with reference to FIG. 14, charge injection corresponding to the injected charge amount at which the trap density is saturated in the film is performed. The optimum value differs depending on the type and quality of the insulating film, but generally, the current silicon oxide film is injected with a charge of 1 C, cm ² from 10 OmCZcm ² . Therefore, 1 mAZcm ² than 1 0 OmA / cm ² of current density, and the current injection, it is preferable to apply a stress. Although charge injection is possible at 1 mA / cm ² or less, it takes too much time to obtain the desired value, which is not practical. Also, at a current density exceeding 1 O OmAZcm ² , the film is more likely to cause dielectric breakdown, which is not practical. On the other hand, when stress is applied by an electric field, the range of 51 \ 1001 \ 201 \ 10 is preferable. Although charge injection is possible at 5 MV cm or less, it takes too much time to obtain a desired value, which is not practical. At current densities greater than 2 OMVZcm, the film is more likely to cause dielectric breakdown, which is also impractical.

These general conditions are not limited to the example of the present embodiment, but are considered in various embodiments of the present invention.

When the memory array shown in the present embodiment is formed in a device, a force for making the thickness of the gate oxide film of the MOS FET in the circuit on the same device other than the memory cell equal to that of the oxide film of 5 or 6, Alternatively, the oxidation process can be reduced by removing the oxide after performing the oxidation of step 5 and removing the oxide film to have the same thickness as the oxide film formed by the second oxidation.

FIG. 8 shows a circuit diagram when the memory cells shown in FIGS. 1 and 2 are arranged in a NOR type memory array. In order to realize the memory array shown in FIG. 8, for example, a process as shown in FIGS. 9 and 10 can be considered. Fig. 9 In the schematic plan view, the progress of the process is shown in the order of a to g. FIG. 10 shows a schematic plan view of a part of the steps shown in FIG.

First, a stripe-shaped element isolation groove is formed in a semiconductor substrate, and an insulator 15 is buried in the groove. Then, a gate oxide thin film portion 5 is formed on the surface of the semiconductor substrate (a in FIG. 9). The plan view at this time is shown in FIG. Thereafter, a portion 10 of the gate electrode is formed (FIG. 9b), and an oxide film is formed again on the semiconductor substrate to form a gate oxide thick film portion 6 (FIG. 9c). The remaining 11 is formed (d in FIG. 9). Using the gate electrode as a mask region, the source and drain 12 are formed by ion implantation (FIG. 9, e). Thereafter, the gate electrode is covered with silicon nitride 17 (f in FIG. 9). The plan view at this time is shown in FIG. The source of the memory cell is short-circuited at the source line 18, the plug 19 is set up at the drain (c in FIG. 10), and this plug 19 is short-circuited at the bit line 20 (g in FIG. 9). ). The plan view at this time is shown in FIG. 10d.

By applying a high bias stress to the gate oxide film 5 in advance, a trap having a density required for the MOS type nonvolatile memory can be formed. In addition, when the gate oxide film 5 is formed, by forming the oxide film a plurality of times and forming an interface in the oxide film, a portion with many traps can be formed in the oxide film. Further, it goes without saying that a plurality of different methods of manufacturing the insulating film may be combined as described above. That is, a silicon oxide film is manufactured using the CVD method and the thermal oxidation method.

When fabricating the memory array shown in this embodiment in a device, the thickness of the gate oxide film of the MOS FET in the circuit on the same device other than the memory cell is the same as the oxide film of layer 5 or layer 6. Alternatively, the oxidation step can be reduced by oxidizing the layer 5 and then removing it to make it the same as the oxide film thickness formed by the second oxidation. <Embodiment 3>

In FIG. 11, the memory cells shown in FIG. 3 and FIG. FIG. 2 shows a circuit diagram in the case of arrangement in an array. In order to realize the memory array shown in FIG. 11, for example, the processes shown in FIGS. 12 and 13 can be considered. FIG. 12 is a schematic sectional view showing the progress of the process in the order of a to f. FIG. 13 shows a schematic plan view of a part of the steps shown in FIG.

First, a stripe-shaped element isolation groove is formed in a semiconductor substrate, an insulator 15 is buried in the groove, and then a gate oxide film 5 is formed on the surface of the semiconductor substrate (a in FIG. 12). The plan view at this time is shown in Fig. 13a. Thereafter, the gate 8 of the memory transistor and the gate 9 of the enhancement transistor are formed (FIG. 12b), and the source and drain 12 are formed by ion implantation using this gate electrode as a mask region (first step). 2 Figure 1 c). Thereafter, the gate electrode 9 of the enhancement transistor and the gate electrode 8 of the memory transistor are covered with silicon nitride 17 (d in FIG. 12 and b in FIG. 13), and the source of the memory cell is connected to the source line 1. Short-circuit at 8 and set up a plug 19 at the drain (c in FIG. 13), and short-circuit this plug 19 with a bit line 20 (e in FIG. 12). The plan view at this time is shown in Fig. 13d.

By applying a high bias stress to the gate oxide film 5 in advance, a trap having a density required for the MOS type volatile memory can be formed. Also, by forming the oxide film a plurality of times when forming the gate oxide film 5 and forming an interface in the oxide film, a portion with many traps can be formed in the oxide film. Further, it goes without saying that a plurality of different methods of manufacturing the insulating film may be combined as described above. That is, a silicon oxide film is manufactured using the CVD method and the thermal oxidation method.

When making the memory array shown in this embodiment in a device, the oxidation process is performed by making the thickness of the gate oxide film of the MOS FET in the circuit on the same device other than the memory cell the same as that of the oxide film 5. Can be reduced.

Simpler than conventional non-volatile memory by MOS non-volatile memory of the present invention A non-volatile memory having a simple structure can be realized with a smaller number of masks. With a small number of masks, memories can be manufactured at low cost. In addition, because of its simple structure, the cause of failures is smaller than that of conventional non-volatile memory, and development time can be shortened and high yield can be achieved.

The main symbols are listed below to help understand the drawings.

1 ... gate electrode, 2 ... semiconductor substrate, 3 ... source, 4 ... drain, 5 ... gate oxide film, 6 ... thick gate oxide film, 7 ... interlayer insulating film, 8 ... memory transistor gate electrode, 9 ... enhancement Transistor gate electrode, 10… part of gate electrode, 11… part of gate electrode, 12… source ■ drain, 13… silicon nitride sidewall, 14… element isolation groove, 15… element isolation And interlayer insulating films, 16 ... word lines, 17 ... silicon nitride, 18 ... source lines, 19 ... plugs, 20 ... bit lines, 21 ... memory lines. Industrial applicability

The present invention can provide a nonvolatile semiconductor memory element and a semiconductor device with stable operation.

Claims

The scope of the claims

1. a substrate, a source region and a drain region on a surface of the substrate, a channel region on a surface of the substrate between the source and drain regions, and an insulating film formed to cover the channel region And a gate electrode formed on the insulating film, wherein the insulating film constitutes a charge storage section, and the trap level of the insulating film is a trap level in addition to the insulating film forming means. A nonvolatile semiconductor memory element formed by using a position forming means.

2. a substrate; a source region and a drain region on the surface of the substrate; a channel region on the surface of the substrate between the source and drain regions; and an insulating film formed to cover the channel region. And at least a gate electrode formed on the insulating film. The insulating film constitutes a charge storage portion, and the insulating film is formed on the insulating film formed by the insulating film forming means. A nonvolatile semiconductor memory element to which electric stress has been applied.

3. The non-volatile semiconductor memory device according to claim 1, wherein the insulating film is an insulating film formed by performing thermal oxidation a plurality of times.

4. The non-volatile semiconductor device according to claim 1, wherein the insulating film is constituted by a plurality of insulating films formed by different manufacturing methods of the insulating film. Storage element.

5.The insulating film has an insulating film formed by a CVD (Chemical Vapor Deposit On) method and an insulating film formed by a thermal oxidation method. 3. The nonvolatile semiconductor memory device according to any one of items 1 to 2 above.

6. The insulating film according to claim 1, wherein the insulating film is an insulating film formed by applying an electric stress to the insulating film after forming the insulating film. 3. The nonvolatile semiconductor memory device according to claim 1.

7. The nonvolatile semiconductor memory device according to claim 3, wherein the insulating film is an insulating film formed by applying an electric stress to the insulating film after the formation of the insulating film. .

8. The nonvolatile semiconductor memory device according to claim 4, wherein the insulating film is an insulating film formed by applying an electric stress to the insulating film after the formation of the insulating film. .

9. The nonvolatile semiconductor memory element according to claim 5, wherein the insulating film is an insulating film formed by applying an electric stress to the insulating film after the formation of the insulating film. .

10. On the semiconductor substrate of the first conductivity type, the drain region of the second conductivity type selectively formed on the surface of the semiconductor substrate, and the drain region is selected on the surface of the semiconductor substrate at a predetermined distance. A source region of the second conductivity type formed in an integrated manner, an insulating film formed so as to at least partially overlap an end of the drain region and extending over an end of the source region, and a gate insulating film. Wherein the insulating film is disposed between the semiconductor substrate of the first conductivity type and the gate insulating film, and the insulating film has regions of two different thicknesses; and A non-volatile semiconductor memory device that stores information by holding electric charge in a thin portion of an insulating film.

11. The nonvolatile semiconductor memory device according to claim 10, wherein at least a thin film portion of said insulating film is an insulating film formed by performing thermal oxidation a plurality of times.

12. The method according to claim 10, wherein at least a thin film portion of the insulating film is constituted by a plurality of insulating films formed by different manufacturing methods of the insulating film. Non-volatile semiconductor storage device.

1 3. At least a thin film portion of the insulating film has an insulating film formed by a chemical vapor deposition (CVD) method and an insulating film formed by a thermal oxidation method. Claim 10 Non-volatile semiconductor storage device.

14. The at least thin film portion of the insulating film is an insulating film formed by applying an electrical stress to the insulating film after the formation of the insulating film. 14. The nonvolatile semiconductor memory device according to any one of items 13 to 13.

15. The semiconductor memory device according to any one of claims 10 to 14, wherein n semiconductor memory devices are arranged, and the source of the nonvolatile semiconductor memory device is a source line and the drain is a bit line. M rows of non-volatile semiconductor memory devices connected to the memory cell array are connected, and m gate electrodes of the non-volatile semiconductor memory devices are connected to n read lines, and a different word line is connected to one word line. An AND-type semiconductor memory device, wherein only the semiconductor memory devices belonging to the non-volatile semiconductor memory device column are connected.

16. The semiconductor memory device according to any one of claims 10 to 14, comprising two semiconductor memory devices having a structure in which the sources are connected to each other. , 2 x n drains connected to bit lines, m rows of semiconductor storage devices are arranged, and n source lines and 2 x n read lines are connected to m sources of the semiconductor storage cells. The gate is connected to a source line and a line, respectively. At this time, only one semiconductor memory device belonging to a different semiconductor memory device column is connected to one source line and the line. NOR type semiconductor

17. A drain region of the second conductivity type selectively formed on the surface of the semiconductor substrate on the semiconductor substrate of the first conductivity type, and the drain region is selected on the surface of the semiconductor substrate at a predetermined distance. A source region of the second conductivity type, which is formed on the semiconductor substrate, and an insulation formed on the semiconductor substrate so as to at least partially overlap an end of the drain region, and to extend over an end of the source region. A semiconductor memory device provided with a memory transistor and an enhancement transistor formed of a film and a gate electrode formed on the insulating film, and having a common source and drain.

18. The memory transistor insulating film is formed by multiple thermal oxidations. 18. The semiconductor memory device according to claim 17, wherein said semiconductor memory device is an edge film.

19. The semiconductor memory device according to claim 17, wherein said memory transistor insulating film is constituted by a plurality of insulating films formed by different insulating film manufacturing methods.

20. The memory transistor insulating film has an insulating film formed by a CVD (Chemica IV apour Deposition) method and an insulating film formed by a thermal oxidation method. The semiconductor storage device according to claim 17.

21. The memory transistor insulating film according to claim 18, wherein the memory transistor insulating film is an insulating film formed by applying an electric stress to the insulating film after the formation of the insulating film. The semiconductor memory device according to any one of the above.

22. A semiconductor memory device comprising n two semiconductor memory devices according to any one of claims 17 to 21 and having a structure in which sources are connected to each other, comprising 2 x n cells Of the semiconductor memory cells in which m drains are connected to bit lines, and n source lines, 2 × n word lines and 2 × n memory lines have m The gate of the enhancement transistor and the gate of the memory transistor are connected to the source line, the lead line, and the memory line, respectively. A NOR type semiconductor memory device in which only semiconductor memory devices belonging to a semiconductor memory device row are connected.

23. Manufacturing for manufacturing a semiconductor memory device having at least a storage unit and an electronic circuit unit other than the storage unit, and a field-effect transistor constituting the storage unit having a gate insulating film having a different thickness region A method of forming a gate insulating film of a field-effect transistor constituting the storage unit and at least a gate insulating film of a field-effect transistor included in an electronic circuit unit other than the storage unit. A semiconductor memory device having at least a step formed by Production method.

24. A step of forming a gate insulating film of a field-effect transistor constituting a storage unit, and applying an electric stress to the gate insulating film to form a trap level in the gate insulating film. A method for manufacturing a nonvolatile semiconductor memory device, comprising at least the following steps:

25. The method according to claim 24, wherein the step of forming the gate insulating film includes a plurality of thermal oxidation steps.

26. The method for manufacturing a nonvolatile semiconductor memory device according to claim 24, wherein the step of forming the gate insulating film includes a step of forming the gate insulating film by a different insulating film manufacturing method.

27. The step of forming the gate insulating film includes a step of forming an insulating film by a chemical vapor deposition (CVD) method and a step of forming the insulating film by a thermal oxidation method. 25. The method for manufacturing a nonvolatile semiconductor memory device according to claim 24, wherein: