WO2003005050B1 - Method and apparatus for optimized parallel testing and access of electronic circuits - Google Patents

Method and apparatus for optimized parallel testing and access of electronic circuits

Info

Publication number
WO2003005050B1
WO2003005050B1 PCT/US2002/020505 US0220505W WO03005050B1 WO 2003005050 B1 WO2003005050 B1 WO 2003005050B1 US 0220505 W US0220505 W US 0220505W WO 03005050 B1 WO03005050 B1 WO 03005050B1
Authority
WO
WIPO (PCT)
Prior art keywords
test
bus
controllers
data signal
cancelled
Prior art date
Application number
PCT/US2002/020505
Other languages
French (fr)
Other versions
WO2003005050A1 (en
Inventor
Michael Ricchetti
Christopher J Clark
Original Assignee
Intellitech Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intellitech Corp filed Critical Intellitech Corp
Priority to CA002421047A priority Critical patent/CA2421047C/en
Priority to JP2003510974A priority patent/JP4083117B2/en
Priority to KR1020037003224A priority patent/KR100623310B1/en
Priority to EP02742331A priority patent/EP1402278B1/en
Priority to DE60221836T priority patent/DE60221836T2/en
Publication of WO2003005050A1 publication Critical patent/WO2003005050A1/en
Publication of WO2003005050B1 publication Critical patent/WO2003005050B1/en
Priority to HK04106974A priority patent/HK1064444A1/en

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test
    • G01R31/318563—Multiple simultaneous testing of subparts
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318516—Test of programmable logic devices [PLDs]
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318555—Control logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/26—Accessing multiple arrays
    • G11C2029/2602—Concurrent test

Abstract

A Parallel Test Architecture (PTA) is provided that facilitates simultaneous access to multiple electronic circuits (i.e.), in parallel) for optimized testing, debugging, or programmable configuration of the circuits. The PTA includes a Parallel Test Bus (PTB), a test controller connected to the PTB, and a plurality of addressable PTB controllers connected to the PTB, in which each addressable PTB controller is coupleable to a respective electronic circuit to be accessed. The test controller is configured to send at least one control signal over the PTB to respective addressable PTB controllers to initiate parallel scan access of the electronic circuits coupleable thereto by the respective addressable PTB controllers. Further, each addressable PTB controller is configured to employ a scan protocol to access the respective electronic circuit coupleable thereto based on the control signal sent over the PTB by the test controller, and send resultant scan data over the PTB to the first controller in response to accessing the respective electronic circuit.

Claims

AMENDED CLAIMS[received by the International Bureau on 7 January 2003 (07.01.2003); orginal claims 1-51 cancelled; new claims 52-116 added (18 pages)]
1. (Cancelled)
2. (Cancelled)
3. (Cancelled)
4. (Cancelled)
5. (Cancelled)
6. (Cancelled)
(Cancelled)
8. (Cancelled)
9. (Cancelled)
10. (Cancelled)
11 (Cancelled)
12. (Cancelled)
13. (Cancelled)
14. (Cancelled)
15. (Cancelled)
70
16. (Cancelled)
17. (Cancelled)
18. (Cancelled)
19. (Cancelled)
20. (Cancelled)
21. (Cancelled)
22. (Cancelled)
23. (Cancelled)
24. (Cancelled)
25. (Cancelled)
26. (Cancelled)
27. (Cancelled)
28. (Cancelled)
29. (Cancelled)
30. (Cancelled)
31. (Cancelled)
32 (Cancelled)
71
33. (Cancelled)
34. (Cancelled)
35. (Cancelled)
36. (Cancelled)
37. (Cancelled)
38. (Cancelled)
39. (Cancelled)
40. (Cancelled)
41. (Cancelled)
42. (Cancelled)
43. (Cancelled)
44. (Cancelled)
45. (Cancelled)
46. (Cancelled)
47. (Cancelled)
48. (Cancelled)
72
49. (Cancelled)
50. (Cancelled)
51. (Cancelled)
52. A system for accessing one or more electronic circuits for testing, debugging, or programmably configuring the electronic circuits, comprising: a test bus; a first test resource connected to the test bus; and a plurality of controllers connected to the test bus, each controller being coupleable to a respective electronic circuit to be accessed, wherein the first test resource is configured to send at least one first signal over the test bus to respective controllers to access, in parallel, the electronic circuits via the respective controllers, and wherein each controller is configured to employ a first protocol to access the respective electronic circuit coupleable thereto based on the at least one first signal sent over the test bus by the first test resource, and to provide at least one first resultant signal over the test bus to the first test resource as a result of accessing the respective electronic circuit.
53. The system of claim 52 wherein each controller includes an interface compatible with the IEEE 1149.1 test standard, each controller being further configured to employ the protocol given in the IEEE 1149.1 test standard to access the respective electronic circuit coupleable thereto.
73
54. The system of claim 52 wherein each controller includes an interface compatible with the IEEE 1149.4 test standard, each controller being further configured to employ the protocol given in the IEEE 1149.4 test standard to access the respective electronic circuit coupleable thereto.
55. The system of claim 52 wherein the first test resource includes an interface compatible with the IEEE 1149.1 test standard.
56. The system of claim 52 wherein the test bus comprises a multi-drop test access bus, and each electronic circuit to be accessed includes a respective test access bus.
57. The system of claim 56 wherein each controller is further configured to link the multi-drop test access bus to the respective test access bus included in the electronic circuit coupleable thereto.
58. The system of claim 52 wherein the test bus is compatible with the IEEE 1149.1 test standard.
59. The system of claim 52 wherein the test bus comprises a digital test bus, and the system further includes an analog test bus, a second test resource, and a communication link configured to couple the second test resource to the first test resource, the analog test bus being coupled to the second test resource and coupleable to the respective electronic circuits to be accessed.
60. The system of claim 59 wherein the second test resource is configured to employ a second protocol to access the respective electronic circuits based on at least one second
74 signal sent over the digital test bus by the first test resource, and to provide at least one second resultant signal over the communication link to the first test resource as a result of accessing the respective electronic circuits.
61. The system of claim 59 wherein the second test resource includes an interface compatible with the IEEE 1149.4 test standard, the second test resource being further configured to employ the protocol given in the IEEE 1149.4 test standard to access the respective electronic circuits.
62. The system of claim 52 wherein the first test resource is further configured to send at least one expected-data signal to the respective controllers, the expected-data signal being indicative of data expected to be received from the electronic circuits as a result of being accessed by the respective controllers .
63. The system of claim 62 wherein each controller is further configured to receive at least one actual-data signal from the respective electronic circuit as a result of being accessed, to compare the actual-data signal to the expected-data signal, and to provide at least one resultant-data signal over the test bus to the first test resource as a result of the comparison.
64. The system of claim 52 wherein each controller is further configured to receive at least one actual-data signal from the respective electronic circuit as a result of being accessed, and the first test resource is further configured to send at least one mask-data signal to the respective controllers, the mask-data signal being operative to mask at least a portion of the actual-data signal.
75
65. The system of claim 52 wherein each controller is further configured to provide at least one input-data signal to the respective electronic circuit coupleable thereto, and the first test resource is further configured to send at least one mask-data signal to the controller, the mask-data signal being operative to mask at least a portion of the input-data signal.
66. The system of claim 63 wherein the respective controllers are further configured to store the resultant-data signal.
67. The system of claim 66 wherein the first test resource is further configured to retrieve the stored resultant-data signal .
68. The system of claim 63 wherein the respective controllers are further configured to compact the actual-data signal.
69. The system of claim 65 wherein the respective controllers are further configured to generate at least a portion of the input-data signal.
70. The system of claim 52 wherein each controller includes a digital input/output circuit configured to convey one or more digital signals between the controller and the respective electronic circuit based on at least one second signal sent over the test bus by the first test resource.
71. The system of claim 70 wherein the first test resource is configured to send at least one expected-data signal to the respective controllers, the at least one expected-data signal being indicative of data expected to be sent to the respective digital input/output circuits by the electronic circuits as a result of being accessed by the respective controllers.
72. The system of claim 71 wherein the respective controllers are further configured to receive at least one actual-data signal from the electronic circuit coupleable thereto, to compare the actual-data signal to the expected-data signal, and to provide at least one resultant-data signal over the test bus to the first test resource as a result of the comparison.
73. The system of claim 70 wherein the respective controllers are further configured to receive at least one actual-data signal from the electronic circuit coupleable thereto, the first test resource being further configured to send at least one mask-data signal to the respective controllers, the mask- data signal being operative to mask at least a portion of the actual-data signal.
74. The system of claim 70 wherein each controller is configured to provide at least one input-data signal to the respective electronic circuit coupleable thereto, and the first test resource is further configured to send at least one mask-data signal to the controller, the mask-data signal being operative to mask at least a portion of the input-data signal provided to the respective electronic circuit by the controller.
75. The system of claim 72 wherein the respective controllers are further configured to store the resultant-data signal.
77
76. The system of claim 75 wherein the first test resource is further configured to retrieve the stored resultant-data signal .
77. The system of claim 72 wherein the respective controllers are further configured to compact the actual-data signal.
78. The system of claim 74 wherein the respective controllers are further configured to generate at least a portion of the input-data signal.
79. The system of claim 52 wherein each controller includes an auto start circuit configured to send a start signal over the test bus from the controller to the first test resource, the start signal being operative to indicate to the first test resource that the respective electronic circuits to be accessed are coupled to the controllers, thereby enabling the first test resource to provide the at least one first signal to access, in parallel, the electronic circuits via the respective controllers.
80. The system of claim 52 wherein each controller includes a communication interface having an associated voltage level coupleable to the respective electronic circuit to be accessed, and a programmable input/output voltage circuit configured to set the voltage level of the communication interface to assure electrical compatibility with the respective electronic circuit.
81. The system of claim 80 wherein the programmable input/output voltage circuit sets the voltage level of the communication interface based on at least one second signal sent over the test bus by the first test resource.
78
82. The system of claim 52 wherein the test bus comprises a plurality of test buses, and respective pluralities of controllers are connected to the test buses, and further including at least one bus bridge configured for successively interconnecting the test buses.
83. The system of claim 82 wherein the bus bridge interconnects a first test bus and a second test bus, the first test bus being configured as a source bus.
84. The system of claim 82 wherein the bus bridge interconnects a first test bus and a second test bus, each of the first and second test buses including a respective test- data input line and a respective test-data output line, the bus bridge being configured to link the test-data output line of the first test bus to the test-data input line of the second test bus, and to link the test-data output line of the second test bus to the test-data input line of the first test bus.
85. The system of claim 52 wherein the first test resource is configured to store data denoting a plurality of modes for addressing the plurality of controllers, and to execute at least one application to address at least one of the plurality of controllers according to one of the addressing modes.
86. The system of claim 85 wherein each controller has an associated address value, and in one of the addressing modes the test resource addresses a single controller based on its associated address value.
79
87. The system of claim 85 wherein each controller has an associated identification value, and in one of the addressing modes the test resource addresses one or more of the plurality of controllers based on their associated identification values.
88. The system of claim 85 wherein each controller has an associated group address value, and in one of the addressing modes the test resource addresses respective controllers having the same group address value.
89. The system of claim 85 wherein at least one of the plurality of controllers has an associated alias address value, and in one of the addressing modes the test resource addresses at least one controller based on its associated alias address value.
90. A test bus architecture for accessing one or more electronic circuits for testing, debugging, or programmably configuring the electronic circuits, comprising: a test bus; a first test resource connected to the test bus; and a plurality of controllers connected to the test bus, each controller being coupleable to a respective electronic circuit to be accessed, wherein the test bus is configured to convey at least one first signal from the first test resource to respective controllers to access, in parallel, the electronic circuits via the respective controllers, and to convey at least one first resultant signal from the respective controllers to the first test resource as a result of accessing the respective ports of the electronic circuits coupleable thereto.
80
91. The test bus architecture of claim 90 wherein the respective ports of the electronic circuits to be accessed are compatible with IEEE 1149.1 test standard.
92. The test bus architecture of claim 90 wherein the test bus comprises a multi-drop test access bus.
93. The test bus architecture of claim 90 wherein the test bus is compatible with the IEEE 1149.1 test standard.
94. The test bus architecture of claim 90 wherein the test bus is further configured to convey at least one test access signal between the first test resource and the plurality of controllers, the at least one test access signal being selected from a signal group including a test clock signal, a test mode select signal, a test data input signal, a test data output signal, and a test reset signal.
95. The test bus architecture of claim 90 wherein the test bus is further configured to convey at least one expected-data signal from the first test resource to the respective controllers, the expected-data signal being indicative of data expected to be received from the electronic circuits as a result of being accessed by the respective controllers.
96. The test bus architecture of claim 95 wherein the respective controllers are further configured to receive at least one actual-data signal from the respective electronic circuits, and to compare the actual-data signal to the expected-data signal, and the test bus is further configured to convey at least one resultant-data signal from the respective controllers to the first test resource as a result of the comparison.
81
97. The test bus architecture of claim 90 wherein the respective controllers are further configured to receive at least one actual-data signal from the respective electronic circuits, and the test bus is further configured to convey at least one mask-data signal from the first test resource to the respective controllers, the mask-data signal being operative to mask at least a portion of the actual-data signal.
98. The test bus architecture of claim 90 wherein each controller is configured to provide at least one input-data signal to the respective electronic circuit coupleable thereto, and the test bus is further configured to convey at least one mask-data signal from the first test resource to the controller, the mask-data signal being operative to mask at least a portion of the input-data signal.
99. The test bus architecture of claim 90 wherein the test bus is further configured to convey a start signal from the respective controllers to the first test resource, the start signal being operative to indicate to the first test resource that the respective electronic circuits to be accessed are coupled to the controllers, thereby enabling the first test resource to provide the at least one first signal to access, in parallel, the respective ports of the electronic circuits via the respective controllers.
100. A test resource for controlling access to one or more electronic circuits for testing, debugging, or programmably configuring the circuits, comprising: a communication interface connectable to a test bus, the test bus being connected to a plurality of controllers, each
82 controller being coupleable to a respective electronic circuit to be accessed; and at least one storage device configured to store at least one application for accessing, in parallel, the respective electronic circuits via the plurality of controllers, wherein the test resource is configured to execute the at least one application to control the transmission of at least one first signal over the test bus via the communication interface to respective controllers, the respective controllers employing a first protocol to access the electronic circuits coupleable thereto based on the at least one first signal sent over the test bus by the test resource.
101. The test resource of claim 100 wherein the communication interface is compatible with the IEEE 1149.1 test standard.
102. The test resource of claim 100 wherein the at least one storage device is configured to store at least one application for accessing a single electronic circuit by a selected controller, the test resource being configured to execute the at least one application to control the transmission of at least one first signal over the test bus via the communication interface to the selected controller.
103. The test resource of claim 100 wherein the at least one storage device is configured to store data denoting a plurality of modes for addressing the plurality of controllers, the test resource being configured to execute the at least one application to address at least one of the plurality of controllers according to one of the addressing modes .
83
104. The test resource of claim 103 wherein each controller has an associated address value, and in one of the addressing modes the test resource addresses a single controller based on its associated address value.
105. The test resource of claim 103 wherein each controller has an associated identification value, and in one of the addressing modes the test resource addresses one or more of the plurality of controllers based on their associated identification values.
106. The test resource of claim 103 wherein each controller has an associated group address value, and in one of the addressing modes the test resource addresses respective controllers having the same group address value.
107. The test resource of claim 103 wherein at least one of the plurality of controllers has an associated alias address value, and in one of the addressing modes the test resource addresses at least one controller based on its associated alias address value.
108. A method of accessing one or more electronic circuits for testing, debugging, or programmably configuring the electronic circuits, comprising the steps of: providing a first test bus; providing a first test resource and a plurality of first controllers connected to the first test bus, each first controller being coupleable to a respective electronic circuit to be accessed; sending at least one first signal over the first test bus to respective first controllers by the first test resource to
84 access, in parallel, the electronic circuits via the respective first controllers; employing a first protocol to access the electronic circuits by the respective first controllers based on the at least one first signal sent over the first test bus by the first test resource; and providing at least one first resultant signal over the first test bus to the first test resource as a result of accessing the respective electronic circuits by the respective first controllers.
109. The method of claim 108 further including the steps of providing a second test bus coupleable to the respective electronic circuits to be accessed and respective second controllers connected to the second test bus and the first controllers, and employing a second protocol to access the respective electronic circuits via the respective second controllers by the first controllers based on at least one second signal sent over the first test bus by the first test resource.
110. The method of claim 108 further including the step of sending at least one expected-data signal to the respective first controllers by the first test resource, the expected- data signal being indicative of data expected to be received from the electronic circuits as a result of being accessed by the respective first controllers.
111. The method of claim 110 further including the steps of receiving at least one actual-data signal from the respective electronic circuit as a result of being accessed by the first controller, comparing the actual-data signal to the expected- data signal by the first controller, and providing at least
85 one resultant-data signal over the test bus to the first test resource as a result of the comparison by the first controller.
112. The method of claim 108 further including the steps of receiving at least one actual-data signal from the respective electronic circuit as a result of being accessed by the first controller, sending at least one mask-data signal to the respective first controllers by the first test resource, the mask-data signal being operative to mask at least a portion of the actual-data signal.
113. The method of claim 108 further including the steps of providing at least one input-data signal to the respective electronic circuit by the first controller, and sending at least one mask-data signal to the first controller by the first test resource, the mask-data signal being operative to mask at least a portion of the input-data signal.
114. The method of claim 108 wherein the first providing step includes providing a plurality of test buses, and the second providing step includes providing respective pluralities of first controllers connected to the test buses, and further including the step of successively interconnecting the test buses by at least one bus bridge.
115. The method of claim 114 wherein the step of successively interconnecting the test buses includes interconnecting a first test bus and a second test bus by the bus bridge, the first test bus being a source bus.
116. The method of claim 114 wherein the step of successively interconnecting the test buses includes interconnecting a
86 first test bus and a second test bus by the bus bridge, each of the first and second test buses including a respective test-data input line and a respective test-data output line, and further including the steps of linking the test-data output line of the first test bus to the test-data input line of the second test bus, and linking the test-data output line of the second test bus to the test-data input line of the first test bus.
87
PCT/US2002/020505 2001-07-05 2002-06-27 Method and apparatus for optimized parallel testing and access of electronic circuits WO2003005050A1 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
CA002421047A CA2421047C (en) 2001-07-05 2002-06-27 Method and apparatus for optimized parallel testing and access of electronic circuits
JP2003510974A JP4083117B2 (en) 2001-07-05 2002-06-27 Electronic circuit optimum parallel inspection access method and apparatus
KR1020037003224A KR100623310B1 (en) 2001-07-05 2002-06-27 Method and apparatus for optimized parallel testing and access of electronic circuits
EP02742331A EP1402278B1 (en) 2001-07-05 2002-06-27 Method and apparatus for optimized parallel testing and access of electronic circuits
DE60221836T DE60221836T2 (en) 2001-07-05 2002-06-27 METHOD AND DEVICE FOR OPTIMIZED PARALLEL TESTING AND ACCESS TO ELECTRONIC CIRCUIT
HK04106974A HK1064444A1 (en) 2001-07-05 2004-09-14 Method and apparatus for optimized parallel testing and access of electronic circuits

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US30305201P 2001-07-05 2001-07-05
US60/303,052 2001-07-05
US10/119,060 US6988232B2 (en) 2001-07-05 2002-04-09 Method and apparatus for optimized parallel testing and access of electronic circuits
US10/119,060 2002-04-09

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Publication Number Publication Date
WO2003005050A1 WO2003005050A1 (en) 2003-01-16
WO2003005050B1 true WO2003005050B1 (en) 2003-03-06

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EP (1) EP1402278B1 (en)
JP (1) JP4083117B2 (en)
KR (1) KR100623310B1 (en)
CN (1) CN100416288C (en)
AT (1) ATE370423T1 (en)
CA (1) CA2421047C (en)
DE (1) DE60221836T2 (en)
HK (1) HK1064444A1 (en)
TW (1) TWI250293B (en)
WO (1) WO2003005050A1 (en)

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