WO2003017342A3 - Verfahren zum herstellen einer selbstjustierten struktur auf einem halbleiter-wafer - Google Patents

Verfahren zum herstellen einer selbstjustierten struktur auf einem halbleiter-wafer Download PDF

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Publication number
WO2003017342A3
WO2003017342A3 PCT/DE2002/002651 DE0202651W WO03017342A3 WO 2003017342 A3 WO2003017342 A3 WO 2003017342A3 DE 0202651 W DE0202651 W DE 0202651W WO 03017342 A3 WO03017342 A3 WO 03017342A3
Authority
WO
WIPO (PCT)
Prior art keywords
layer
semiconductor wafer
self
production
light
Prior art date
Application number
PCT/DE2002/002651
Other languages
English (en)
French (fr)
Other versions
WO2003017342A2 (de
Inventor
Matthias Goldbach
Thomas Hecht
Joern Luetzen
Bernhard Sell
Original Assignee
Infineon Technologies Ag
Matthias Goldbach
Thomas Hecht
Joern Luetzen
Bernhard Sell
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Matthias Goldbach, Thomas Hecht, Joern Luetzen, Bernhard Sell filed Critical Infineon Technologies Ag
Priority to DE50209782T priority Critical patent/DE50209782D1/de
Priority to JP2003522152A priority patent/JP3989898B2/ja
Priority to US10/485,307 priority patent/US7041568B2/en
Priority to KR1020047001186A priority patent/KR100602918B1/ko
Priority to EP02753028A priority patent/EP1412969B1/de
Publication of WO2003017342A2 publication Critical patent/WO2003017342A2/de
Publication of WO2003017342A3 publication Critical patent/WO2003017342A3/de

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Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G03F7/2022—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure
    • G03F7/203—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure comprising an imagewise exposure to electromagnetic radiation or corpuscular radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0385—Making a connection between the transistor and the capacitor, e.g. buried strap

Abstract

Eine Struktur auf einer Schichtenoberfläche des Halbleiter-Wafers weist zumindest einen für elektromagnetische Strahlung reflektierenden ersten Flächenbereich (8,9) und zumindest einen zweiten, im Wesentlichen nicht reflektierenden Flächenbereich (10,11,12) auf. Auf diese Schichtenoberfläche wird eine lichtdurchläßige Isolationsschicht (13) und eine lichtempfindliche Schicht erzeugt. Die elektromagnetische Strahlung wird mit einem Einfallswinkel θ auf die lichtempfindliche Schicht gerichtet und die Struktur der Schichtenoberfläche mit einem lateralen Ersatz in die lichtempfindliche Schicht abgebildet.
PCT/DE2002/002651 2001-08-02 2002-07-18 Verfahren zum herstellen einer selbstjustierten struktur auf einem halbleiter-wafer WO2003017342A2 (de)

Priority Applications (5)

Application Number Priority Date Filing Date Title
DE50209782T DE50209782D1 (de) 2001-08-02 2002-07-18 Verfahren zum herstellen einer selbstjustierten struktur auf einem halbleiter-wafer
JP2003522152A JP3989898B2 (ja) 2001-08-02 2002-07-18 半導体ウエハーにおける自動位置合わせ構造の製造方法
US10/485,307 US7041568B2 (en) 2001-08-02 2002-07-18 Method for the production of a self-adjusted structure on a semiconductor wafer
KR1020047001186A KR100602918B1 (ko) 2001-08-02 2002-07-18 반도체 웨이퍼 상에 셀프-얼라인 구조물을 제조하는 방법
EP02753028A EP1412969B1 (de) 2001-08-02 2002-07-18 Verfahren zum herstellen einer selbstjustierten struktur auf einem halbleiter-wafer

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10137830.0 2001-08-02
DE10137830A DE10137830A1 (de) 2001-08-02 2001-08-02 Verfahren zum Herstellen einer selbstjustierten Struktur auf einem Halbleiter-Wafer

Publications (2)

Publication Number Publication Date
WO2003017342A2 WO2003017342A2 (de) 2003-02-27
WO2003017342A3 true WO2003017342A3 (de) 2003-06-26

Family

ID=7694088

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2002/002651 WO2003017342A2 (de) 2001-08-02 2002-07-18 Verfahren zum herstellen einer selbstjustierten struktur auf einem halbleiter-wafer

Country Status (7)

Country Link
US (1) US7041568B2 (de)
EP (1) EP1412969B1 (de)
JP (1) JP3989898B2 (de)
KR (1) KR100602918B1 (de)
DE (2) DE10137830A1 (de)
TW (1) TW567391B (de)
WO (1) WO2003017342A2 (de)

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US7343581B2 (en) * 2005-06-27 2008-03-11 Tela Innovations, Inc. Methods for creating primitive constructed standard cells
US7590968B1 (en) 2006-03-01 2009-09-15 Tela Innovations, Inc. Methods for risk-informed chip layout generation
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US8247846B2 (en) 2006-03-09 2012-08-21 Tela Innovations, Inc. Oversized contacts and vias in semiconductor chip defined by linearly constrained topology
US8214778B2 (en) 2007-08-02 2012-07-03 Tela Innovations, Inc. Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US8541879B2 (en) 2007-12-13 2013-09-24 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US7943967B2 (en) 2006-03-09 2011-05-17 Tela Innovations, Inc. Semiconductor device and associated layouts including diffusion contact placement restriction based on relation to linear conductive segments
US8653857B2 (en) 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US7932545B2 (en) 2006-03-09 2011-04-26 Tela Innovations, Inc. Semiconductor device and associated layouts including gate electrode level region having arrangement of six linear conductive segments with side-to-side spacing less than 360 nanometers
US8225239B2 (en) 2006-03-09 2012-07-17 Tela Innovations, Inc. Methods for defining and utilizing sub-resolution features in linear topology
US9035359B2 (en) 2006-03-09 2015-05-19 Tela Innovations, Inc. Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US7763534B2 (en) * 2007-10-26 2010-07-27 Tela Innovations, Inc. Methods, structures and designs for self-aligning local interconnects used in integrated circuits
US7446352B2 (en) 2006-03-09 2008-11-04 Tela Innovations, Inc. Dynamic array architecture
US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US9009641B2 (en) 2006-03-09 2015-04-14 Tela Innovations, Inc. Circuits with linear finfet structures
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US8448102B2 (en) 2006-03-09 2013-05-21 Tela Innovations, Inc. Optimizing layout of irregular structures in regular layout context
US7956421B2 (en) 2008-03-13 2011-06-07 Tela Innovations, Inc. Cross-coupled transistor layouts in restricted gate level layout architecture
US7908578B2 (en) 2007-08-02 2011-03-15 Tela Innovations, Inc. Methods for designing semiconductor device with dynamic array section
US8225261B2 (en) 2006-03-09 2012-07-17 Tela Innovations, Inc. Methods for defining contact grid in dynamic array architecture
US8245180B2 (en) 2006-03-09 2012-08-14 Tela Innovations, Inc. Methods for defining and using co-optimized nanopatterns for integrated circuit design and apparatus implementing same
US7577049B1 (en) 2006-08-08 2009-08-18 Tela Innovations, Inc. Speculative sense enable tuning apparatus and associated methods
US7979829B2 (en) * 2007-02-20 2011-07-12 Tela Innovations, Inc. Integrated circuit cell library with cell-level process compensation technique (PCT) application and associated methods
US8286107B2 (en) 2007-02-20 2012-10-09 Tela Innovations, Inc. Methods and systems for process compensation technique acceleration
US8667443B2 (en) 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US8453094B2 (en) 2008-01-31 2013-05-28 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US7939443B2 (en) 2008-03-27 2011-05-10 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
US9122832B2 (en) 2008-08-01 2015-09-01 Tela Innovations, Inc. Methods for controlling microloading variation in semiconductor wafer layout and fabrication
US8661392B2 (en) 2009-10-13 2014-02-25 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the Same
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same

Citations (6)

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EP0083397A2 (de) * 1981-12-31 1983-07-13 International Business Machines Corporation Verfahren zur Herstellung von elektronischen Mikroschaltkreisstruckturen
EP0523768A2 (de) * 1991-06-28 1993-01-20 Philips Electronics Uk Limited Herstellung von einem Dünnschicht-Transistor
US5879866A (en) * 1994-12-19 1999-03-09 International Business Machines Corporation Image recording process with improved image tolerances using embedded AR coatings
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US6022764A (en) * 1995-12-11 2000-02-08 Hyundai Electronics Industries Co., Ltd. Exposure apparatus and method for forming thin film transistor
US6080654A (en) * 1999-08-20 2000-06-27 Advanced Micro Devices, Inc. Simplified method of forming self-aligned vias in a semiconductor device

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Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0083397A2 (de) * 1981-12-31 1983-07-13 International Business Machines Corporation Verfahren zur Herstellung von elektronischen Mikroschaltkreisstruckturen
EP0523768A2 (de) * 1991-06-28 1993-01-20 Philips Electronics Uk Limited Herstellung von einem Dünnschicht-Transistor
US5879866A (en) * 1994-12-19 1999-03-09 International Business Machines Corporation Image recording process with improved image tolerances using embedded AR coatings
US6022764A (en) * 1995-12-11 2000-02-08 Hyundai Electronics Industries Co., Ltd. Exposure apparatus and method for forming thin film transistor
US5981150A (en) * 1996-07-05 1999-11-09 Kabushiki Kaisha Toshiba Method for forming a resist pattern
US6080654A (en) * 1999-08-20 2000-06-27 Advanced Micro Devices, Inc. Simplified method of forming self-aligned vias in a semiconductor device

Also Published As

Publication number Publication date
EP1412969A2 (de) 2004-04-28
TW567391B (en) 2003-12-21
DE50209782D1 (de) 2007-05-03
EP1412969B1 (de) 2007-03-21
JP2004538661A (ja) 2004-12-24
JP3989898B2 (ja) 2007-10-10
US7041568B2 (en) 2006-05-09
WO2003017342A2 (de) 2003-02-27
US20040259032A1 (en) 2004-12-23
DE10137830A1 (de) 2003-02-27
KR100602918B1 (ko) 2006-07-19
KR20040030865A (ko) 2004-04-09

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