WO2003023626A1 - High speed serial data transport between communications hardware modules - Google Patents
High speed serial data transport between communications hardware modules Download PDFInfo
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- WO2003023626A1 WO2003023626A1 PCT/US2002/028941 US0228941W WO03023626A1 WO 2003023626 A1 WO2003023626 A1 WO 2003023626A1 US 0228941 W US0228941 W US 0228941W WO 03023626 A1 WO03023626 A1 WO 03023626A1
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- serial data
- data stream
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/409—Mechanical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
- H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
- H04N21/236—Assembling of a multiplex stream, e.g. transport stream, by combining a video stream with other content or additional data, e.g. inserting a URL [Uniform Resource Locator] into a video stream, multiplexing software data into a video stream; Remultiplexing of multiplex streams; Insertion of stuffing bits into the multiplex stream, e.g. to obtain a constant bit-rate; Assembling of a packetised elementary stream
- H04N21/23608—Remultiplexing multiplex streams, e.g. involving modifying time stamps or remapping the packet identifiers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
- H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
- H04N21/236—Assembling of a multiplex stream, e.g. transport stream, by combining a video stream with other content or additional data, e.g. inserting a URL [Uniform Resource Locator] into a video stream, multiplexing software data into a video stream; Remultiplexing of multiplex streams; Insertion of stuffing bits into the multiplex stream, e.g. to obtain a constant bit-rate; Assembling of a packetised elementary stream
- H04N21/2365—Multiplexing of several video streams
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/60—Network structure or processes for video distribution between server and client or between remote clients; Control signalling between clients, server and network components; Transmission of management data between server and client, e.g. sending from server to client commands for recording incoming content stream; Communication details between server and client
- H04N21/63—Control signaling related to video distribution between client, server and network components; Network processes for video distribution between server and clients or between remote clients, e.g. transmitting basic layer and enhancement layers over different transmission paths, setting up a peer-to-peer communication via Internet between remote STB's; Communication protocols; Addressing
- H04N21/643—Communication protocols
- H04N21/64322—IP
Definitions
- the present invention is directed to systems, methods, protocols, apparatus and related software for high-speed data communications. More particularly, the invention relates to the transport of digital data between communications hardware in accordance with a differential serial Internet Protocol (IP). Accordingly, the general objects of the invention are to provide novel systems, methods, apparatus and software of such character.
- IP differential serial Internet Protocol
- the typical modern communications system may include one or more signal receivers, decoders, modulators, data servers, streaming video servers, transaction, billing and conditional access processors, communication controllers and/or broadband media routers.
- Broadband media routers and/or Transport Multiplexers (TMXs) are particularly important and are generally used to multiplex data streams or to re-multiplex data streams that have previously been multiplexed.
- broadband media routers are used to groom multiple transport streams, such as MPEG2 (Moving Picture Experts Group) encoded video streams, and to thereby produce output streams for video appliances such as digital televisions, personal versatile recorders (PNR), and the like.
- the grooming provided by a broadband media router can include, for example, transcoding, advertisement insertion, adding IP opportunistic data, re-multiplexing incoming services to provide a new channel line-up, etc. While these features make such routers important devices in modern digital communications systems, conventional routers impose serious limitations on the rate of information transfer through these communications systems.
- Broadband media routers typically comprise various hardware components and, since it is necessary to communicate signals between these various components, this hardware must be communicatively linked together. These components are typically linked with the use of a backplane which is a circuit board that serves to interconnect such components situated on shelves within a rack or chassis.
- backplane which is a circuit board that serves to interconnect such components situated on shelves within a rack or chassis.
- Custom backplane designs have been the typical solution for interconnecting components in a particular way in order to achieve the desired functionality.
- Such custom designs incorporate discrete hardware to send data in parallel form between the different components (e.g., circuit boards) connected by the backplane. While effective to a degree, these custom designs are expensive, single use solutions and are, therefore, neither efficient nor cost-effective. They, additionally, are bandwidth limited, which poses limitations on the systems with which they are used.
- One form of the present invention satisfies the above-stated needs and overcomes the above-stated and other deficiencies of the related art by providing a high speed Internet Protocol communications system, such as a transport multiplexer, for serially transporting digital data between communications hardware.
- the system includes a chassis and a plurality of boards communicatively linked together via the chassis.
- the chassis receives the plural boards and has a backplane (or, alternatively, a mid-plane) with a control data bus and a serial content data bus for communicatively linking the plural boards together.
- the plural boards can comprise an input board for receiving a parallel data stream and for transmitting a differential serial data stream to the serial data bus.
- the input board has a serializer for converting the processed parallel data stream into the serial data stream and a transmitter for transmitting the serial data stream to the serial data bus of the chassis.
- the system also has at least one other board with a serial data receiver and a deserializer.
- the receiver preferably receives the serial data stream from the serial data bus and a deserializer with clock recovery.
- the received serial data stream is then converted into an output data stream in accordance with control signals received via the control data bus.
- the communications system can be a transport multiplexer wherein the serial data transported between the communications hardware via the serial data bus comprises MPEG2 encoded data packets.
- each of the data packets preferably comprises a header having target media accelerator processor data, an MPEG2 data packet and a footer having a time stamp.
- the transmitter can be a low voltage differential signal transmitter
- the receiver can be a low voltage differential signal receiver and data can be transported unidirectionally from the transmitter to the receiver.
- the input board can have, e.g., eleven low voltage differential signal transmitters, and the other boards can have, e.g., four low voltage signal receivers.
- This particular configuration of the inventive system enables the rate of the serial data transport from the input board to the other boards to reach at least about 324 Mbps.
- Alternative embodiments can use up to twelve transmitters and twelve receivers per board.
- some of the communicatively linked boards may be transcoder boards with a low voltage differential signal receiver for receiving the serial data stream via the serial data bus and a media accelerator processor for generating the output data stream.
- Other boards may be time division multiplexer boards with at least one media accelerated processor and at least one low voltage signal receiver for receiving the serial data stream via the serial data bus.
- Some embodiments of the invention can also include a CPU board that is communicatively linked to the input board via the control data bus.
- the input board of the invention can be implemented as a field programmable gate array that performs packet identifier filtering, performs packet identifier aliasing and determines where to send, or transmit, the serial data.
- a serial differential protocol can be used for packet communication. This provides for the transport of the packets at a higher rate than was possible with the related art.
- Other apparatus embodiments of the invention can include a high speed Internet Protocol backplane (or a mid-plane) for communicatively linking an input board with at least one other board.
- the backplane preferably includes a cPCI control data bus for delivering control data to the other board and a serial data bus for serially delivering content data from the input board to the other board, wherein the control data bus and the serial data bus comprise independent communications pathways linking the input board and the other board together.
- the invention also encompasses methods for serially transporting digital data between communications hardware. Some of these method embodiments of the invention include communicatively linking the communications hardware via a control data bus and a serial content data bus, receiving a parallel data stream, serializing the parallel data stream, transmitting the serialized data stream to the serial data bus, receiving the serialized data stream via the serial data bus, and converting the received serial data stream into an output data stream in accordance with control signals received via the control data bus.
- Figure 1 is a diagram illustrating use of a transport multiplexer in accordance with the present invention, the TMX being shown in combination with various other equipment;
- Figure 2 is a diagram showing a representative data transport scheme for a TMX backplane in accordance with one embodiment of the invention
- FIG. 3 is a block diagram showing the use of an Internet Protocol
- IP IP bus in a representative TMX in accordance with a preferred embodiment of the invention
- Figure 4 is a diagram showing the IP routing on the connectors of the backplane used in the TMX of Figure 2;
- Figure 5 illustrates the IP bus for the TMX of Figure 3, and in particular the input (INP), transcoder (TRC) and/or multiplexer (MUX), central processing unit (CPU) and hot swap controller (HSC) boards in a larger chassis;
- IPP input
- TRC transcoder
- MUX multiplexer
- CPU central processing unit
- HSC hot swap controller
- Figure 6 summarizes the IP bus of Figure 5 for a smaller chassis in accordance with an alternative embodiment of the present invention
- FIG. 7 is a high-level block diagram of a TMX in accordance with a preferred embodiment of the present invention.
- Figure 8 is a block diagram of a representative input processor board that can be used in the TMX of Figure 7;
- Figure 9 illustrates a data packet configuration for use with a preferred embodiment of the invention, the packet having a routing header (1 byte), an MPEG2 packet (188 bytes) and a trailing time stamp (4 bytes);
- Figure 10 is a functional block diagram of a field programmable gate array (FGPA) implementation of an input processor;
- FGPA field programmable gate array
- Figure 11 illustrates a representative PID table for use with the input processor of the invention
- Figure 12 shows an exemplary memory access scheme, along with memory partition, for the input processor of the invention.
- Figure 13 is a block diagram of a transcoder board with Low
- LNDS Noltage Differential Signal
- FIG. 1 is a high-level system diagram showing a representative application for an inventive TMX 20, TMX 20 being shown in combination with a control system and various other equipment.
- the TMX system can utilize, for example, Motorola Computer Group's (MCG) chassis, the CPX8216IP, or the customized CPX1205IP chassis for low end needs.
- MCG Motorola Computer Group's
- the CPX8216IP is a 16 slot 12RU chassis while the CPX1205IP is a five slot 3RU chassis.
- One desirable feature of the CPX8216IP backplane is that it has two domains and, therefore, can be made to be completely 1 : 1 redundant.
- the CPX8216IP and CPX1205IP are compact PCI chassis. Both fit into an 18" deep rack, accept cards from the front and rear, and can be equipped with either AC or DC power supply modules.
- each of these chassis has a backplane 30 (or, more particularly, a special type of backplane known as a mid-plane) with two independent communication buses.
- a backplane 30 or, more particularly, a special type of backplane known as a mid-plane
- the IP bus 34 can be either a uni-directional or a bi-directional IP bus over which data can be sent to or received from any board up to a rate of 1 GHz.
- One preferred configuration for the 8216IP chassis is shown in Figure 5.
- the four center slots of the 8216IP chassis preferably receive two host CPUs and two Hot Swap Controller (HSC) cards 46.
- HSC Hot Swap Controller
- the HSC card 46 serves two primary purposes: (i) to bridge the two PCI domains so as to appear as one twelve slot PCI bus (instead of two six slot PCI buses as is the case for redundancy); and (ii) to provide hot swap functionality.
- Other configurations within the scope of the invention are possible.
- the 8216IP chassis could be equipped with a single CPU board.
- each of the CPX8216IP and the CPX1205IP chassis has two independent communication pathways; namely, the cPCI bus 32 allowing for configuration and control, and the passage of compressed bitstreams to MUX 60; and the IP interconnect bus 34 over which incoming data can be distributed to any card such as representative Transcoder card (TRC) 70' or the MUX card 60'.
- TRC Transcoder card
- the IP interconnect bus 34 is preferably used to route MPEG2 packets. This is preferably accomplished by utilizing a family of devices called SerDes, which serialize and de-serialize data.
- Serializers and de-serializers which incorporate clock recovery on the deserializer end, allow for a serial link across backplane 30 to pass data from board to board.
- a particularly preferred embodiment uses a serializer/deserializer pair whose serial link is a low voltage differential signal (LNDS).
- LNDS low voltage differential signal
- the system will define fixed locations across backplane 30 which are capable of receiving input cards such as input card 50'. The remainder of the available slots or locations are preferably reserved for the TRC or MUX card (70' and 60', respectively).
- Input board 50' will have serializers 54 installed, while the TRC and MUX cards (70' and 60') will have the de-serializers (74 and 64, respectively) and plural media accelerated processors installed. Any incoming packet can be routed to any target Media Accelerated Processor (MAP) (e.g., 66 or 76) on any target card.
- MAP Media Accelerated Processor
- both aforementioned preferred chassis are capable of receiving a CPU card 40, e.g., a Motorola 750 PowerPC based CPU card (see especially, Figures 4 and 7).
- a CPU card 40 e.g., a Motorola 750 PowerPC based CPU card (see especially, Figures 4 and 7).
- Figure 4 is a diagram showing IP routing on the connectors of the
- each connection comprises two differential pairs; Receive (Rx) and Transmit (Tx) and there is a point-to-point connection between every slot, including itself. Additionally, there are two differential pairs across backplane 30 for distributing a common clock reference 47 and a sync signal 48 to every board to maintain system synchronization.
- serial LNDS transmitters 54 and receivers 64 and 74 may be used instead of an Ethernet link. This also allows a higher payload data rate link between boards.
- slots SI through S4 may be dedicated for the input processor (INP) boards 50' as shown in Figure 5, and the remaining slots S5-S6 and S11-S16 can receive TRC or MUX boards 70' and 60' in the 8216IP chassis.
- the backplane of the 1205IP chassis provides many of the features of the 8216 IP chassis discussed immediately above.
- the 1205IP backplane 30' of Figure 6 was designed for Ethernet connectivity, only some of the available interconnects need to be utilized (namely the transmit lines) in the preferred embodiment. This is also due to the fact that the preferred architecture passes data unidirectionally.
- Serial LNDS transmitters 54 and receivers 74 or 64 may be used instead of an Ethernet link in order to allow a higher payload data rate link of, e.g., 216 Mbps between two boards.
- slot SI' is preferably dedicated to receive the T ⁇ P board 50'
- slot S2' or slot S3' can each receive one of an I ⁇ P, TRC or MUX board (50' 5 70" or 60').
- slot S4' receives either a TRC or MUX board 70' or 60'.
- a high-level block diagram of a preferred TMX is provided in
- the TMX can serve multiple applications, such as High Definition (HD) television and Standard Definition (SD) television Add/Drop multiplexing, advertisement splicing, IP data processing and scrambling.
- the input signals 22 received by TMX 20 can be in a number of widely known and used formats. These input signal formats include, for example, ASI, DHEI and DS3. While the number and type of signal inputs and outputs that can be accommodated by the system are merely a matter of design choice, up to forty ASI inputs can be supported in the system when the aforementioned preferred chassis are utilized.
- the output data stream formats can be any combination of ASI, DS3, SMPTE-310M or DHEI. [0037] A representative implementation of the input processor INP 50' is illustrated in Figure 8.
- the input processor's ( NP) 50 primary functions are to accept a plurality of data streams (e.g., up to ten MPEG2 data streams), to perform packet identifier (PID) filtering and aliasing, and to determine where to route the data streams for processing based on configuration data provided by the host CPU board via the control bus.
- the INP card 50' targets TRC's or MUX's via LVDS drivers and serial bus 34, and targets the CPU via the PCI bus. While typical incoming data packet lengths are 188 bytes. Out-going packets preferably have a length of 193 bytes and three components: 1 target MAP processor byte + a 188 byte packet of content data + a 4 byte time stamp.
- the maximum supported data rates are 324 Mbps to each target MAP and/or MUX.
- FIG. 9 illustrates the configuration of a preferred data transfer packet 80.
- incoming data is filtered for null packets, and fed into a first-in-first-out (FIFO) for rate conversion before being written to the SRAM.
- FIFO first-in-first-out
- a header 82 and a footer 86 are built on top of each content data packet 80 for (in the case of Figure 9, an MPEG2 data packet) for routing and time stamping purposes.
- a header 82 can, for example, be provided as the first byte of the 193 byte packet (Target Map byte) and is used to target a particular processor on a transcoder or multiplexer board receiving the data packets.
- the footer 86 can, for example, comprise a four byte object which follows the content data packet and is used as a time stamp. This time stamp is processed at the receiving board to correct the program clock reference (PCR). Those skilled in the art will appreciate that other implementations are also possible.
- PCR program clock reference
- FIG. 10 is a structural block diagram of a preferred input processor 50. While those skilled in the art will appreciate that other implementations are also possible, processor 50 is implemented as a field programmable gate array (FPGA) with an SRAM memory in this representative implementation. As shown in the embodiment of Figure 10, an SRAM wagon wheel 90 memory access scheme with ten spokes preferably runs at a preferred clock speed of 54 MHz. Table 1 shown immediately below lists a number of input data rates that are supported:
- the buffer size for each port can comprise, for example, 512 packets. Since each memory access is preferably 32 bits wide, and the SRAM preferably operates at packet boundaries, 196 bytes can be transferred during each read or write operation. Taking the case in which all ten inputs are active, it takes forty- nine 54MHz cycles for a write operation, and fifty-four 54 MHz cycles for a read operation, times ten (1,030 cycles) to complete the wagon wheel, and to thereby write or read 196 bytes to/from the SRAM for each port.
- Table SRAM is accessed to determine the PID alias, target board, and target MAP for the packet to be processed.
- the SRAM is configured by the CPU via the PCI bus. The definition of each address location is shown in Figure 11 and discussed immediately below.
- the actual packet memory can be divided as shown in Figure 12.
- each entry in PID table 110 consists of high and low priority queues for the CPU, a MAP target, a slot target and the 13-bit MPEG2 packet PID alias.
- INP 50 uses this data to route packets through the transport multiplexer in any one of a number of ways. For example, data could be routed to a single slot, or a number of slots, and a single MAP or a number of MAPs, and/or the CPU. Those skilled in the art will appreciate that other implementations are also possible.
- a representative method 120 for accessing the memory device is illustrated, along with memory partition, in Figure 12.
- Data is stored and retrieved in accordance with the invention using the concatenation of the port number and PID number to access memory locations.
- the upper four bits of the address refer to the port and the lower 13 bits refer to the PID.
- the address field is a 17-bit address field.
- a transcoder (TRC) 70 in accordance with one embodiment of the invention is illustrated in Figure 13.
- TRC 70 a basic function of TRC 70 is to accept four LNDS data streams, and to send these streams to one of five MAP processors 76.
- data packets received by TRC 70 are preferably 193 bytes long; a one byte target MAP identifier, a 188 byte MPEG2 packet of content, and a four byte time stamp.
- the TRC can be configured as a modified MUX card, based on special code written for such functionality being resident on one of the MAP processors of TRC 70, with the remaining four MAPs serving as transcoders.
- TRC 70 can have a ROM connected to it. This enables the TRC to serve as the master clock to the entire system (thus driving the reference clock (27/4 MHz) to the backplane) and also the time stamp sync signal to synchronize all boards upon its terminal count.
- the DHEI frequencies and the 27 MHz are derived from the 44.736 MHz clock via a numerically controlled oscillator ( ⁇ CO).
- ⁇ CO numerically controlled oscillator
- the TRC is not configured to be the master clock generator. In this alternative embodiment, the system would accept the 27/4 MHz clock from the backplane, along with the time stamp sync signal, and synchronize its time stamp counter to it.
- the MAP processors 76 shown therein will accept code download, configuration, and quantization and provide status and buffer characteristics via the PCI Bus.
- Each of the MAP processors is capable of transcoding video packets in accordance with a conventional transcoding algorithm to thereby compress the outgoing data stream.
- the MAP buffer delays any associated audio or data elementary streams so they can be put together with the transcoded video data.
- the recombined bit stream is sent to the MUX MAP via the PCI.
- the present invention provides apparatus and methods for using an Internet Protocol backplane to transport digital packets (such as MPEG2 packets) between boards in a chassis using a serial differential protocol capable of achieving a high data transfer rate.
- the invention therefore, provides a solution to the problem of routing digital packets (e.g., MPEG2 packets) to target processing engines across a backplane.
- the inventive solution obviates the related art requirements for custom backplane designs, together with discrete hardware, for sending data in parallel form between boards.
- the invention uses a backplane architecture designed specifically for IP data traffic from any slot to any slot of a chassis.
- a Motorola MCG 8216TP sixteen slot chassis is used to provide board-to-board data pathways.
- This preferred hardware solution allows packets to be sent from any one of plural input ports of an input board to any MPEG2 processing engine on any other board in the system.
- Low Noltage Differential Signal (LNDS) transmitters are provided on input boards, and LNDS receivers are provided on other boards.
- a header and a footer are preferably built on top of each data packet for routing and time stamping purposes. In the transcoder embodiment illustrated in Figure 13, this header is provided in the first byte of a 193 byte packet and is used to target a particular one of the five processors on each transcoder board.
- the customized footer which preferably comprises four bytes at the end of the entire 193 byte packet, provides a time stamp.
- This time stamp can be taken from a free running counter that is synchronized between the two cards (e.g., an input processor card and a transcoder card).
- the first byte is used to route content to one of five processors on the transcoder board and is then dropped.
- the processor on the receiving board uses the time stamp in the last four bytes to correct the program clock reference.
- This hardware solution minimizes costs for the system as well as optimizes data transfer speeds.
- the chassis is preferably a modified compact PCI chassis, which can accommodate the IP interconnections and which uses the dedicated slot for serial inter-connections to thereby free up the PCI bandwidth for other important tasks.
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Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
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KR10-2004-7003807A KR20040063118A (en) | 2001-09-13 | 2002-09-11 | High speed serial data transport between communications hardware modules |
CA002460421A CA2460421C (en) | 2001-09-13 | 2002-09-11 | High speed serial data transport between communications hardware modules |
MXPA04002432A MXPA04002432A (en) | 2001-09-13 | 2002-09-11 | High speed serial data transport between communications hardware modules. |
EP02759644A EP1428132A1 (en) | 2001-09-13 | 2002-09-11 | High speed serial data transport between communications hardware modules |
Applications Claiming Priority (4)
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US32206301P | 2001-09-13 | 2001-09-13 | |
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US10/124,610 US7408961B2 (en) | 2001-09-13 | 2002-04-16 | High speed serial data transport between communications hardware modules |
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WO2003023626A1 true WO2003023626A1 (en) | 2003-03-20 |
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PCT/US2002/028941 WO2003023626A1 (en) | 2001-09-13 | 2002-09-11 | High speed serial data transport between communications hardware modules |
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WO (1) | WO2003023626A1 (en) |
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- 2002-09-11 WO PCT/US2002/028941 patent/WO2003023626A1/en not_active Application Discontinuation
- 2002-09-11 EP EP02759644A patent/EP1428132A1/en not_active Withdrawn
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CA2460421A1 (en) | 2003-03-20 |
US7408961B2 (en) | 2008-08-05 |
CA2460421C (en) | 2009-09-08 |
CN1555529A (en) | 2004-12-15 |
MXPA04002432A (en) | 2004-07-23 |
EP1428132A1 (en) | 2004-06-16 |
US20030056049A1 (en) | 2003-03-20 |
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