WO2003025770A2

WO2003025770A2 - Reconfigurable system

Info

Publication number: WO2003025770A2
Application number: PCT/EP2002/010084
Authority: WO
Inventors: Martin Vorbach
Original assignee: Pact Xpp Technologies Ag
Priority date: 2001-09-07
Filing date: 2002-09-09
Publication date: 2003-03-27
Also published as: WO2003025770A3; EP1449109A2; AU2002342668A1

Abstract

The invention relates to a reconfigurable processor (VPU) which is designed to be integrated into a technical environment comprising a standard processor (CPU), such as a DSP, RISC, or CISC processor or a (micro)controller. Said processor must be designed in such a way that a connection is created which is as simple and as efficient as possible. According to another aspect of the invention, the system created is easy to programme. The invention takes into account the continued use of existing programmes of the CPU, the code compatibility and the simple integration of the VPU into the existing programmes.

Description

Title: Reconfigurable system

description

The present invention relates to what is claimed in the preamble. The present invention thus addresses the question of how a reconfigurable processor can be connected to a standard processor in a particularly favorable manner.

In the present case, a reconfigurable architecture is understood to mean modules (VPU) with configurable function and / or networking, in particular integrated modules with a plurality of arithmetic and / or logical and / or logical and / or analog and / or storing and / or internal / external arranged in one or more dimensions networking modules that are connected to each other directly or through a bus system.

The category of these modules includes, in particular, systolic arrays, neural networks, multiprocessor systems, processors with a plurality of arithmetic units and / or logical cells and / or communicative / peripheral cells (10), networking and network components such as crossbar switches, as well as known ones Modules of the genus FPGA, DPGA, Chameleon, XPUTER, etc. Reference is made in this connection in particular to the following property rights and applications by the same applicant: P 44 16 881.0-53, DE 197 81 412.3, DE 197 81 483.2, DE 196 54 846.2- 53, DE 196 54 593.5-53, DE 197 04 044.6-53, DE 198 80 129.7, DE 198 61 088.2-53, DE 199 80 312.9, PCT / DE 00/01869, DE 100 36 627.9-33, DE 100 28 397.7, DE 101 10 530.4, DE 101 11 014.6, PCT / EP 00/10516, EP 01 102 674.7, DE 196 51 075.9-53, DE 196 54 846.2-53, DE 196 54 593.5-53, DE 197 04 728.9, DE 198 07 872.2, DE 101 39 170.6, DE 199 26 538.0, DE 101 42 904.5, DE 101 10 530.4, DE 102 02 044.2, DE 102 06 857.7,

DE 101 35 210.7-53, EP 02 001 331.4, 60 / 317,876. These are hereby fully incorporated for disclosure purposes.

The above Architecture is used as an example for clarification and is referred to below as the VPU. The architecture consists of any arithmetic, logical (also memory) and / or memory cells and / or network cells and / or communicative / peripheral (IO) cells (PAEs), which can be arranged in a one- or multi-dimensional matrix (PAC), whereby the matrix can have different, arbitrarily designed cells; the bus systems are also understood as cells. A configuration unit (CT) is assigned to the matrix as a whole or parts thereof, which influences the networking and function of the PA.

The object of the invention is to provide something new for commercial use.

The solution to the problem is claimed independently. Preferred embodiments can be found in the subclaims.

A reconfigurable processor (VPU) is therefore designed into a technical environment that has a standard processor (CPU), such as a DSP, RISC, CISC processor or (micro) controller. The design is such that there is a connection that is as simple as possible and yet very powerful. Another

Aspect that results is the simple programming of the emerging system. The use of existing programs of the CPU as well as the code compatibility and the simple integration of the VPU into existing programs are easily taken into account by the described method.

State of the art

Reconfigurable modules (VPUs) of different types (such as PACT XPP technology, Morphics, Morphosys, Chameleon) are largely incompatible with existing technical environments and programming methods.

The programs of the blocks are further incompatible with existing programs from CPUs. As a result, a considerable development effort for programming is required, eg. B. especially for building blocks of the genera Morphics, Morphosys. Chameleon already integrates a standard processor (ARC) on the reconfigurable modules. This means that programming tools are available. However, not every technical environment is suitable for the use of ARC

Processors suitable, in particular existing programs, code libraries etc. are often available for any indefinite other CPUs.

Description of the invention

A VPU (or, without being specifically mentioned, several VPUs) is coupled to a preferred CPU in such a way that it takes the place and function of a coprocessor there. The function as a coprocessor enables simple integration into existing program codes in accordance with the already existing methods for handling coprocessors according to the prior art. The system can in particular be designed as a (standard) processor or assembly and / or be integrated in a semiconductor (system on chip SoC).

In order to provide the coprocessor connection between CPU and VPU, data or information exchange between CPU and VPU is necessary. In particular, the processor must typically convey data and instructions to the coprocessor unit as to what must be done with them. The data exchange between CPU and VPU can now take place by means of memory coupling and / or IO coupling. In principle, the CPU and VPU can share all resources; in special configurations, on the other hand, it is also possible for the CPU and VPU to use only a part of the resources together, while other resources are explicitly and exclusively available for the CPU or VPU. The question of which variant is preferred will typically depend, among other things, on the overall design of the system, the possible costs, available resources, the expected data load, etc. It should be noted that, where reference has been made to a single CPU, several CPUs can also be addressed together.

In order to carry out a data exchange, data records and / or configurations can be copied or written / read into memory areas specially provided for this purpose and / or corresponding base addresses can be set so that they point to the respective data areas.

To control the coprocessor is now preferred

Variant provided a record that, for example, the

Basic settings of a VPU includes, such as certain base addresses. Furthermore, status variables to control and function control of a VPU by a CPU in the data record or for separate transmission and be exchanged with or separately from data. In a particularly preferred variant, the addresses can be flexibly distributed and assigned. Preferably, therefore, only a basic address in the I / O or memory address space needs to be firmly agreed in order to serve with its data record as a pointer to the flexibly defined addresses.

The data record can be exchanged via a common memory (RAM) and / or via a common peripheral address space (10). The addresses can be flexibly distributed and assigned.

To synchronize the CPU and VPU, one-sided or mutual interrupt procedures (e.g. interrupt lines) can be provided and / or the synchronization is carried out using a polling procedure. Interrupts can also be used to synchronize data and / or DMA transfers. In a particularly preferred embodiment, a VPU is started by a CPU and then independently processes the started or instructed application.

A preferred structure is particularly powerful, in which the VPU used provides its own mechanisms for loading and checking configurations. The genus of these VPUs include, for example, PACT XPP and Chameleon. The circuits according to the invention enable a method of operation in such a way that all configurations of the VPU or part of the VPU configurations are loaded into a memory together with the program to be executed by the CPU. The CPU can refer the VPU to the memory locations during the execution of the program (e.g. by specifying the addresses or Pointer) that contain the configurations to be executed. The VPU can then load the configurations independently and without further influence from the CPU. If and to the extent that the VPU, ie the reconfigurable field with, in particular, coarse-grained runtime configurable elements, has loading logic for loading configurations, it may be sufficient if the processor issues the instruction to the CPU to load a specific configuration. The reconfigurable processor, which then serves as a coprocessor, can therefore preferably be called up via a single command to the loading logic. It should be noted that prior agreement between the VPU and CPU, that is, the calling host processor, can be used to determine exactly which configuration is to be carried out by which call. It should be mentioned that corresponding control means can be provided in the charging logic unit, be it dedicated, implemented or formed by one or more reconfigurable cells of the reconfigurable processor. Execution starts immediately or if necessary with additional information (eg interrupt and / or start command) from the CPU.

In a particularly preferred extension, the VPU can read and write data independently within one or more memories, some of which can be together with or independent of the CPU.

In a particularly preferred extension, the VPU can also independently load new configurations from the memory and, if necessary, reconfigure itself without the need for further influence by the CPU.

These configurations allow a largely from

CPU-independent operation of VPUs. Just a synchronization Exchange of information between the CPU and the VPU, which can preferably take place bidirectionally, should also be provided in order to coordinate the data processing and / or configuration executions.

In principle, the sequence control of a VPU can be carried out directly by a program running on the CPU, which is basically the main program that outsources certain subroutines to the VPU. This is a particularly easy to implement variant.

Mechanisms controlled by the operating system (in particular the scheduler) are preferably used for synchronization and sequence control. A simple scheduler can, after transfer of the function to the VPU, especially where possible,

1. Allow the current main program to continue to run on the CPU, provided that this can run independently and in parallel to data processing on a VPU, with and / or alternatively,

2. if or as soon as the main program has to wait for the data processing on the VPU to end, the task scheduler switches over to another task (for example another main program). The VPU can continue to work in the background regardless of the current CPU task.

Each newly activated task, if it uses the VPU, is typically checked before use to determine whether it is available for data processing or is currently still processing data in a way that blocks the required VPU resources; then either the termination of the data transfer work or, if preferred, the task can be changed.

A simple, yet powerful process can be set up or implemented in particular by so-called descriptor tables, which can be implemented as follows, for example:

To call up the VPU, each task generates one or more tables (VPUPROC) with a suitable defined data format in the memory area assigned to it. This table contains all tax information for a VPU, e.g. the program / configuration to be executed (or pointer to the corresponding memory locations) and / or memory location (s) (or pointer to it) and / or data sources (or pointer to it) of the input data and / or the memory location (s) (or pointers to them) of the operands or the result data.

A table or linked list (LINKLIST), which points to all VPUPROC tables in the order in which they were created and / or called, can be located in the memory area of the operating system, for example.

The data processing on the VPU is now preferably carried out in such a way that a main program creates a VPUPROC and calls the VPU via the operating system. The operating system creates an entry in the LINKLIST. The VPU processes the LINKLIST and executes the referenced VPUPROC. The termination of a respective data processing is then preferably indicated in each case by a corresponding entry in the LINKLIST and / or VPUCALL table, which the CPU z. B. can poll by regular pollen. Alternatively, you can Interrupts from the VPU to the CPU are used as a display and, if necessary, also for exchanging the VPU status; it is not only possible to indicate that the program has ended; Rather, it can also be displayed that and, if appropriate, which point in the subroutine has already been reached.

In this preferred method according to the invention, the VPU works largely independently of the CPU. In particular, the CPU and the VPU can perform independent and different tasks per time unit. The operating system and / or the respective tasks only have to monitor the tables (LINKLIST or VPUPROC).

Alternatively, the LINKLIST can also be dispensed with by linking the VPUPROCs to one another using pointers, as is the case, for example, with B. is known from lists. Processed VPUPROCs are removed from the list, new ones are added to the list. The method is known to programmers and therefore does not have to be carried out further.

The structure of a particularly preferred VPU is shown in Figure 1. Preferably hierarchical configuration managers (CT's) (0101) control and manage an arrangement of reconfigurable elements (PACs) (0102). A local memory for the configurations is assigned to the CT's (0103). The memory also has an interface (0104) to a global memory that provides the configuration data. The configuration processes can be controlled via an interface (0105). An interface of the reconfigurable element (0102) for sequence control and event management (0106) is available, as is an interface for data exchange (0107). FIG. 2 shows a section from an exemplary CPU system, for example a DSP of the type C6000 from Texas Instruments or a microcontroller from ARM (0201). Program memory (0202), data memory (0203), any peripherals (0204) and EMIF (0205) are shown. A VPU is integrated as a coprocessor (0208) via a memory bus (0206) and a peripheral bus (0207). A DMA controller (EDMA) (0209) can perform any DMA transfers, for example between memory (0203) and VPU (0208) or memory (0203) and peripherals (0204). In principle, the VPU and / or CPU can also access the memory independently without the aid of a DMA. The shared memory can in particular also be designed as a dual-port or multi-port memory. Additional modules can be assigned to the system, in particular reconfigurable FPGAs can be used to enable fine-grained processing of individual signals or data bits and / or flexible adaptable interfaces (eg various serial interfaces (V24, USB, etc.), various parallel interfaces , Hard disk interfaces, Ethernet, telecommunications interfaces (a / b, T0, ISDN, DSL, etc)).

Figure 3 shows a more abstract system definition. A CPU (0301) is assigned memory (0302), to which it has write and / or read access. A VPU (0303) is coupled to the memory. The VPU is divided into a CT part (0309) and the reconfigurable elements for data processing (0310).

In order to increase the memory accesses, the memory can have several independent access busses that can possibly be used simultaneously (multiport). In a particularly In a preferred embodiment, the memory is segmented into a number of independent segments (memory banks), with each bank being able to be accessed independently. All segments are preferably within a uniform address space.

Preferably, one segment is mainly available for the CPU (0304), another segment is mainly available for data processing of the VPU (0305), another segment is mainly available for configuration data of the VPU (0306).

A fully configured VPU typically and preferably has its own address generators and / or DMAs in order to carry out data transfers. Alternatively and / or additionally, it is possible that a DMA (0307) is provided within the system (FIG. 3) for data transfers with the VPU.

The system contains IO means (0308) to which the CPU and VPU can have access. Both the CPU and the VPU can each have dedicated memory areas and IO areas to which the other has no access.

A data record (0311) which, as shown graphically, can be in the memory area and / or in the IO area and / or partially in one of the two is used for communication between CPU and VPU, e.g. B. for the exchange of basic parameters and control information. The data record can contain the following information, for example, and thus represents a basic setting data record:

1. Base address (es) of the CT memory area in 0306 for localizing the configurations,

2. Base address (es) of data transfers with 0305,

3. I / O addresses for data transfers with 0308, 4. synchronization information, e.g. B. resetting, stopping, starting the VPU,

5. Status information of the VPU, e.g. B. Error or state of data processing. 6th

The CPU and VPU are synchronized by polling status data and / or information and / or preferably by interrupt control (0312).

The basic setting data record can be a LINKLIST and / or

Contain VPUCALLs, or alternatively point to the LINKLIST and / or VPUCALLs or the first entry of each by pointer.

FIG. 4 shows a possible configuration of the interface structure of a VPU for integration into a system similar to FIG. 3. For this purpose, the VPU is assigned a memory / DMA and / or IO interface for data transfer (0401); another system interface (0402) takes over the sequential control such as B. managing interrupts, starting / stopping processing, exchanging error states, etc.

The memory / DMA and / or IO interface is connected to a memory bus and / or IO bus. The system interface is preferably connected to an IO bus, but can alternatively or additionally be connected to a memory in accordance with 0311. The interfaces (0401, 0402) can be designed to adapt different operating frequencies of the CPU and / or VPU and / or system and can have a clock adaptation circuit, for example the system or the CPU can

400MHz and the VPU work at 200MHz.

The interfaces can carry out a translation of the bus protocols with a protocol adaptation circuit, for example The VPU internal protocol can be converted to an external AMBA bus protocol and vice versa.

The memory / DMA and / or IO interface supports the memory access of the CT to an external memory, which is preferably done directly (memory mapped). The data transfer of the CT (s) and / or PAC (s) can be buffered e.g. B. via FIFO stages. External memory (e.g. 0308, 0203) can be addressed and addressed directly, and DMA internal and / or external DMA transfers can also be carried out. The data processing is controlled via the system interface, such as the initialization and / or the start of configurations. Status and / or error states are also exchanged. Interrupts for the control and synchronization between the CT's and a CPU can be supported.

The system interface can convert internal VPU protocols in such a way that they are converted to external (standard) protocols (e.g. AMBA).

It is pointed out that it is also possible to provide bus interfaces, RAM cells, I / O cells and the like as parts (PAEs) of a VPU. This also applies if these units are to be used for the processor-coprocessor coupling.

A preferred method for code generation for the system described is described in the patent application PACT20, which is fully incorporated for the purposes of disclosure. The method describes a compiler that divides program code into code for a CPU and code for a VPU. Disassembly is carried out on the different processors using different methods. In a particularly preferred embodiment, the respective disassembled The interface codes for communication between the CPU and the VPU have been added to the codes. The expansion can be done automatically by the compiler.

An advantage according to the invention is that administration and / or interface expenditure and programming of the system according to the invention are inexpensive and simple.

The following tables show exemplary communications between a CPU and a VPU. The respective active units are assigned to the columns: CPU, system DMA and DMA interface (EDMA) or memory interface (memory I / F), system interface (system I / F, 0402), CT's , as well as the PAC. The execution cycles of the individual cycles are entered in the lines. Kl references a configuration to be executed 1.

The first table shows, for example, a sequence when using the system DMA (EDMA) for data transfer. Each line shows a sequential control process; the columns show the respective activity in the corresponding assembly:

It should be mentioned that the synchronization between the EDMA and the VPU takes place automatically via the interface 0401, i.e. DMA transfers only take place if the VPU is ready for it.

A second table shows, for example, a preferred, optimized process. The VPU itself has direct access to the configuration memory (0306). Furthermore, the data transfers are carried out by DMA circuitry within the VPU, which can, for example, be permanently implemented (PACT03) and / or arise from the configuration of configurable parts of the PAC.

The work and synchronization effort for the CPU is minimal, which means maximum performance.

Furthermore, the method can provide for several configurations to be carried out on different areas of the VPU, that is to say on different PAEs at the same time, or to be time-multiplexed on the same resources.

In particular, a type of "double buffering" can be used for particularly simple and at the same time fast reconfiguration, in which a plurality of VPUs are provided, one part being able to be reconfigured at a time of the VPUs, while another part is computing and possibly another is inactive can be. The data, trigger, status connections etc. are suitably exchanged between the plurality of VPUs and, if necessary, interconnected by addressed buses and / or multiplexers / demultiplexers in accordance with the currently active and / or reconfigurable VPUs.

All mentioned PACT patent applications and their family members are fully incorporated for disclosure purposes.

Any other configurations and combinations of the described inventions are possible and obvious to a person skilled in the art. In this context, it should be mentioned in particular that instead of coupling a VPU to a CPU using the VPU as a coprocessor, such a coupling is also possible using the CPU as a coprocessor is. Such a case is particularly preferred in order to have command structures identified as program parts with only low parallelism and / or small vector parts processed sequentially during compilation. It is then possible, in particular, for the VPU to call up the CPU via link lists or tables. The link lists or tables can contain information indicating where data can be obtained, the address at which the CPU can access the program information to be processed, etc. The query as to whether the CPU can then process the program parts to be executed by it finished, can in turn via polling or the like. happen. Here, too, it is possible to use the operating system to assign tasks to the CPU and / or to monitor the tasks to be performed by it. In principle, all of the methods described can be used both for coupling a CPU to a VPU as a coprocessor and vice versa. What is important here is the type of coupling for which the operating system is designed. It should be pointed out that it is in particular possible to provide an operating system which enables mutual coupling, that is to say in particular optionally couples the CPU to the VPU or parts thereof and vice versa. The latter is particularly advantageous, for example, if entire program blocks with predominantly sequential parts are to be delivered by the VPU as the host to the CPU as coprocessor and these program blocks still have partially strong vectorial or parallel code that can be quasi retransmitted by the CPU, in particular in response to a determined current or forecasted VPU load.

Claims

Title: Reconfigurable system

claims

1. Data processing system, characterized in that at least one reconfigurable processor is coupled to a standard processor (CPU).

2. Data processing system according to claim 1, characterized in that the reconfigurable processor is arranged as a coprocessor.

3. Data processing system according to one of the preceding claims, characterized in that a memory and / or I / O coupling means for coupling the standard processor and the reconfigurable processor to one another is provided.

4. Data processing system according to one of the preceding

Claims, characterized in that the coupling means are designed for coupling by transmission of data and / or status information and / or configurations.

Data processing system according to one of the preceding claims, characterized in that the CPU and the reconfigurable processor and / or their peripherals are designed in such a way that they can jointly access at least part of the resources available to them and in particular part of the memory area.

6. Data processing system according to one of the preceding claims, characterized in that at least one and / or multi-sided interrupt line is provided for synchronization between the CPU and the reconfigurable processor.

7. Data processing system according to one of the preceding claims, characterized in that the reconfigurable processor has its own configuration loading and / or control means, in particular for at least partial reconfiguration and / or reconfiguration without CPU input during the runtime.

8. A data processing system integrated on a chip according to one of the preceding claims.

9. A method for data processing with a reconfigurable and a standard processor, wherein the standard processor calls subroutines or subroutine parts to be executed on the reconfigurable processor and these are executed on the reconfigurable processor or vice versa.

10. Data processing method according to the preceding claim, characterized in that control information is generated when the reconfigurable processor is called.

11. Data processing method according to the preceding claim, characterized in that the control information is generated as a table, in particular the configuration to be carried out and / or pointer to corresponding

Storage locations and / or data sources and / or operands Storage locations and / or result data storage locations or pointers to them.

12. A method for operating a data processing system according to one of the preceding method claims, wherein a link list is created when the coprocessor is called and is processed by the reconfigurable processor.

13. The method according to any one of the preceding claims, characterized in that the information exchanged between the reconfigurable and standard processor includes a base address of a loading logic memory area for localizing configurations, a base address for data transfers, I / O addresses for data transfers, synchronization information , in particular with regard to resetting, stopping or starting the VPU, and / or status information of the VPU, in particular relating to errors and / or states of the data processing.

14. Method for data processing according to one of the preceding method claims, characterized in that the CPU and VPU are synchronized by polling status data and / or information and / or by interrupt control.