WO2003026212A1

WO2003026212A1 - A switch fabric apparatus and method

Info

Publication number: WO2003026212A1
Application number: PCT/IL2002/000769
Authority: WO
Inventors: Mordechai Kintzlinger; Ayelet Shemesh
Original assignee: Cinata Inc.
Priority date: 2001-09-17
Filing date: 2002-09-17
Publication date: 2003-03-27

Abstract

A switch fabric apparatus (10) for establishing communication between switch endpoints of a medium. The endpoints (70, 40) constituting m input lines over n output lines such that a communication link is selectively established between pairs of input and output lines. The switch fabric apparatus (10) comprises a scheduler (20) that includes m over n computing units (202) operating in parallel. Each computing unit (202) is associated to an input line from among the n input lines and to an outline from among thed m output lines and capable of determining in an autonomous and digital manner whether or not to establish a communication link in the medium between its respective pair of input and output lines.

Description

A Switch Fabric Apparatus and Method

FIELD OF THE INVENTION

This invention relates to switching and routing in digital communication systems, and particularly to a switch fabric apparatus and method.

BACKGROUND OF THE INVENTION In digital communication systems such as data communication or telecommunication systems, a device called 'switch' or 'router' performs a switching function among many communication links. Generally, the switching function inside a router is sometimes referred to as the 'switch fabric' and is usually located in a centralized location of the system, facilitating thus to create link connections between the switch end-points. A switch fabric is usually based on two major components: scheduler and medium. The medium provides the physical connections between the end-point links and is controlled by the medium control, which, in turn, is controlled by the scheduler. The medium can be implemented in various ways, such as a crossbar implementation. The second component of a switch fabric is the scheduler that decides on the appropriate switching configuration and controls the medium by executing a scheduling algorithm.

Generally, the act of decision-making is needed, since each of the end-points operates independently, and there might be conflicts between the needs of the end- points. For example, two or more end-points "want" to connect to the same other end-point. The role of the scheduler in a switching function is, inter alia, to decide which end-point will be connected and which will wait for the next round of requests.

US Patent no. 5,923,656 discloses an asynchronous mode transfer (ATM) switch that comprises input ports and output ports, and a matrix cell scheduler having rows and columns corresponding to the input and output ports, respectively. The matrix is an array of autonomous processing units. The matrix cell scheduler receives entries corresponding to input cells, which are queued to be routed to their designated output ports. The cell scheduler conducts an iterative selection process to choose an optimal set of cells to be transmitted during a subsequent transmission cycle, to achieve maximal throughput. Each step in the iterative selection process includes choosing an entry having the highest calculated weight. The weight of any particular entry is calculated autonomously by the respective processing unit, and is a function of its priority level and all other priority levels for entries in the cell scheduler which corresponds to a common row or column of the traffic matrix. The autonomous processing operation of each processing unit is achieved in an analogous manner, as follows. Each of the processing units draws a current from a row and column current sources in proportion to its weight. A responsive voltage charger develops a charge based upon the amount of current drawn until one or more processing unit reaches a predetermined charge indicating that entries in the units have the highest weight. The process terminates after a maximum of N iterations, where N represents the smaller number of the input ports or output ports. A separate tie-break process, and shifting steps having a maximum of 2N iterations, are executed by separate tie-break circuitry, if any step resulted in the conflicting entries. The disclosed switch can be implemented to provide a throughput of approximately 128 Gbps for a 32X32 ATM switch.

SUMMARY OF THE INVENTION

The present invention provides a switch fabric apparatus for establishing communication between switch endpoints of a medium. The endpoints constituting m input lines over n output lines such that a communication link is selectively established between pairs of input and output lines. The switch fabric apparatus comprises a scheduler that includes m over n computing units operating in parallel. Each computing unit is associated to an input line from among said m input lines and to an outline from among said n output lines and capable of determining in an autonomous and digital manner whether or not to establish a communication link in said medium between its respective pair of input and output lines. According to one embodiment, the invention provides a switch fabric apparatus for establishing communication between endpoints of a medium. The endpoints constituting m input lines over n output lines such that a communication link is selectively established for transmission of data units between pairs of input and output lines during each one of a succession of computational cycles. The switch fabric apparatus comprises a scheduler that includes m over n computing units operating in parallel and arranged in a matrix of m rows over n columns that correspond to said n input lines and m output lines, constituting m row channels and n column channels; each computing unit is associated to an input line from among said n input lines and to an output line from among said m output lines; each computing unit is selectively associated with a preference vector; each computing unit includes a row module and a column module which are cross-coupled; said row module and column module are capable of determining for each computational cycle whether the associated preference vector value is extreme as compared to the preference vector values of other computing units along the row channel and the column channel, and, if in the affirmative, to facilitate a communication link between the associated input and output lines; said computational cycle is divided to a succession of computational iterations during each of which, in parallel and in a digital manner: i) the row module is capable of determining whether its preference vector value is inclusive extreme as compared to the preference vector values of other computing units along a common row channel; in the case of

"inclusive extreme" result write its preference vector value on the row channel and in the case of "no inclusive extreme" result disable the corresponding column module; ii) the column module is capable of determining whether its preference vector value is inclusive extreme as compared to the preference vector values of other computing units along a common column channel; in the case of "inclusive extreme" result write its preference vector value on the column channel and in the case of "no inclusive extreme" result disable the corresponding row module; iii) the row module is capable of enabling a disabled corresponding column module in the case that its preference vector value is exclusive extreme as compared to the preference vector values of other computing units along a common row channel; and iv) the column module is capable of enabling a disabled corresponding row module in the case that its preference vector value is exclusive extreme as compared to the preference vector values of other computing units along a common column channel.

Note that the term "data unit" used herein signifies any digital unit format suitable to be used in digital communication networks, such as data packets and sub-packets cells, for example, asynchronous mode transmission (ATM) cells.

Note also that for each input-output pair of lines for which data transmission is required (and, consequently, a communication link between said may be established) during a specific operational cycle of the switch, the corresponding computing unit is associated with a preference vector, representing a value of an extreme function. In order to determine the optimal transmission configuration, the scheduler finds per row and column at least one computing unit that holds an extreme value of the preference vectors along the corresponding row and column. The term "extreme value" is used herein to denote either maximum value or minimum value. Thus, according to one embodiment of the invention, the scheduler finds per row and column, per computational cycle, at least one computing unit that holds the maximum value of the preference vectors along the corresponding row and column (hereinafter denoted as the "maximum embodiment"). According to another embodiment (hereinafter denoted as the "minimum embodiment"), the scheduler finds per row and column, per computational cycle, at least one computing unit that holds the minimum value of the preference vectors along the corresponding row and column. As mentioned above, the computing units operate in an autonomous and digital manner, i.e., each of the computing units is capable of determining whether it holds the extreme value (either maximum or minimum) among the values of the preference vectors along the corresponding row and column. The term "computational cycle" is used herein to denote the operational step of the computing unit, during which it determines as either holding the extreme value of the corresponding row and column, or not. For those computing units that hold the extreme value by the end of the computing cycle, data transmission is established between the corresponding input-output pair. During each computational cycle, a computing unit performs a succession of and computational iterations. During each iteration, the computing unit determines whether it holds the extreme value along the corresponding row and column, or not. Note that during the same computational cycle, the computing unit may determine in one iteration that it holds the extreme value whilst in another (not necessarily consecutive) iteration, it may determine that it does not hold the extreme value, or vice versa. This extreme/no extreme changes may be repeated more than once during the same computational cycle (hereinafter the flickering effect) until eventually a given state (i.e. extreme or not extreme) is determined for this particular computational cycle, when a predefined condition is met. Each of the computing units includes a row module and a column module, which are cross-coupled. The row module is connected to the row channel, and the column module is connected to the column channel. Per computational iteration, each of the unit's modules is capable of determining whether its preference vector value is inclusive extreme as compared to the preference vector values of other computing units along the corresponding channel.

The term "inclusive extreme" value denotes, for the maximum embodiment, a preference vector value which is greater than or equal to the other preference vector values. For the minimum embodiment, the term "inclusive extreme" value denotes a preference vector value which is lower than or equal to the other preference vector values. The term "no inclusive extreme result" denotes a preference vector value, which is lower than the other preference vector values (for the maximum embodiment), and a preference vector value, which is greater than the other preference vector values (for the minimum embodiment). In the same manner, the term "exclusive extreme" denotes a preference vector value, which is greater than the other preference vector values (for the maximum embodiment), and lower than the other preference vector values (for the minimum embodiment).

As mentioned above, each of the computing unit modules is capable of determining, per computing iteration, if it holds the inclusive extreme value and the exclusive extreme value of the corresponding channel, and accordingly, to disable or enable the cross-coupled module. Thus, per iteration, each module is either in enabled status or in disabled status. The term "disabled" denotes a module status in which the module will determine, during the next iteration, if it holds the exclusive extreme value of the corresponding channel. The term "enabled" denotes a module status in which the module will determine, during the next iteration, if it holds the inclusive extreme value as well as the exclusive extreme value of the corresponding channel, and is able, under appropriate conditions, to write its value onto the corresponding channel. Thus, while in operation, the module continuously determines its value to the other values along the row and column channels to check if it holds the "exclusive extreme" value. Only in the "enabled" status, the module is able to check if it holds the "inclusive extreme" value, and to act accordingly.

Thus, according to one embodiment, the invention provides a switch fabric apparatus for establishing communication between endpoints of a medium; the endpoints constituting m input lines over n output lines such that a communication link is selectively established for transmission of a data unit between pairs of input and output lines during each one of a succession of computational cycles; the switch fabric apparatus comprises a scheduler that includes m over n computing units operating in parallel and arranged in a matrix of m rows over n columns that correspond to said n input lines and m output lines, constituting m row channels and n column channels; each computing unit is associated to an input line from among said n input lines and to an output line from among said m output lines; each computing unit is selectively associated with a preference vector; each computing unit includes a row module and a column module which are cross-coupled; said row module and column module are capable of determining for each computational cycle whether the associated preference vector value is extreme and unique as compared to the preference vector values of other computing units along the row channel and the column channel, and if in the affirmative to facilitate a communication link between the associated input line and output line.

According to another embodiment the invention provides a switch fabric apparatus for establishing communication between endpoints of a medium. The endpoints constituting m input lines over n output lines such that a communication link is selectively established for transmission of data units between pairs of input and output lines during each one of a succession of computational cycles. The switch fabric apparatus comprises a scheduler that includes m over n computing units operating in parallel and arranged in a matrix of m rows over n columns that correspond to said m input lines and n output lines, constituting m row channels and n column channels. Each computing unit is associated to an input line from among said m input lines and to an output line from among said n output lines. Each computing unit is selectively associated with a preference vector. Each computing unit includes a row module and a column module, which are cross- coupled. Said row module and column module are capable of determining for each computational cycle whether the associated preference vector value is extreme as compared to the preference vector values of other computing units along the row channel and the column channel, and if in the affirmative to facilitate a communication link between the associated input and output lines. The computational cycle is divided to a succession of computational iterations during each of which, in parallel and in a digital manner: 1) disabling an enabled row module of the computing unit if disable conditions are met or enabling a disabled row arithmetic function module of the computing unit if enable conditions are met; and 2) disabling an enabled column module of the computing unit if disable conditions are met or enabling a disabled column arithmetic function module of the computing unit if enable conditions are met.

According to yet another embodiment, the invention provides a scheduling module comprising N logic cells that are connected in a chain; an input signal of a first cell among said N logic cells is the input signal of said module and an output signal of a last cell among said N logic cells is the output signal of said module; said module is further associated with an N-bit long vector, for determining in an autonomous and digital manner if said vector holds an extremity value as compared to the values of M-1 vectors, associated with M-1 scheduling modules respectively; said module and M-1 modules constitute together M scheduling modules that share a communication channel having N lines; said module is capable of determining if its associated vector holds said extremity value, substantially simultaneous to the operation of said M-1 scheduling modules, including: - each of said N logic cell corresponds to one bit of said associated N-bit vector and is capable of determining the ratio between said bit value and the communication channel bit value as being one of a group consisting of: (i) either greater than or equal to, (ii) either lower than or equal to.

According to yet another embodiment, the invention provides a scheduling module comprising N logic cells that are connected in a chain; an input signal of a first cell among said N logic cells is the input signal of said module and an output signal of a last cell among said N logic cells is the output signal of said module; said module is further associated with an N-bit long vector, for determining in an autonomous and digital manner if said vector holds an extremity value as compare to the values of M-1 vectors, associated with M-1 scheduling module respectively; said module and M-1 module constituting together M scheduling modules that share a communication channel having N lines; said module is capable of determining if said vector holds said extremity value including:

- each logic cell corresponds to one bit of said associated vector and is capable of determining the ratio between said bit value and the communication channel bit value as being one of a group consisting of: equal to, higher than, lower than; and - logic cell number I is capable of writing its corresponding bit value to the I line of said shared communication channel if the value of a sub-vector comprising the vector bits N-l to 1+1 is one of a group consisting of (i) either greater than or equal to the communication channel value composed of lines N-l to 1+1, or (ii) either lower than or equal to the communication channel value composed of lines N-l to 1+1, I being an integer number between 0 to N-l.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to understand the invention and to see how it may be carried out in practice, one embodiment of the invention will now be described, by way of non- limiting example only, with reference to the accompanying drawings, in which:

Fig. 1 is a schematic illustration of a switch fabric apparatus according to the one embodiment of the invention;

Fig. 2 is a schematic illustration of a scheduler of a switch fabric apparatus according to one embodiment of the invention; Fig. 3 illustrates a simplified implementation of an apparatus according to one embodiment of the invention;

Fig. 4 is schematic illustration of a computing unit of a switch fabric apparatus according to one embodiment of the invention;

Fig. 5A is a flow chart showing the principal operating steps carried out by the switch fabric apparatus according to one embodiment of the invention;

Fig. 5B illustrates schematically a sequence of operations performed in a specific implementation of the embodiment of Fig. 5 A;

Fig. 6 is a more detailed schematic illustration of a single computing unit (CU) according to one embodiment of the invention; Fig. 7 is an ever more detailed schematic illustration of the computing module of Fig. 6.

DETAILED DESCRIPTION OF THE INVENTION Fig. 1 is a schematic illustration of a switch fabric apparatus 10 according to an embodiment of the invention. The switch fabric 10 connects between the endpoints 70, designated as input lines 30 and the output lines 40. The switch fabric 10 includes a scheduler 20 and a medium 60, which are connected by medium control 50. By one embodiment, the switch fabric 10 is design to (i) support a large number of end-points (e.g. up to thousands), (ii) provide high bandwidth (e.g. up to lOOGbps), (iii) low switching times (e.g. less than 1 microsecond), and (iv) one or more decision criterion. Note that the specified (i) to (iv) limitations are by no means binding and accordingly by other embodiments one or more of the specified limitations may be modified or avoided, and/or others may be added, all as required, depending upon the particular application. Note that apparatus 10 can be used with a variety of network technologies (such as ATM, TCP/IP, etc.).

Fig. 2 is a schematic illustration of a scheduler 20 according to a one embodiment of the invention. The scheduler 20 is an m over n array of computing units (CU) 202, where m signifies the number of input lines 30 and n the total number of output lines 40. Note that by one embodiment, dual input/output is used, where each port serves both for input and output.

The CU 202 are identical computing elements, each of which being responsible for connecting between a specific input-output pair. For example, CU [1,1] is responsible for connecting input line 1 and output line 1, while CU [m,n] is responsible for connecting input line m and output line n. As shown in Fig. 2, CU's 202 are connected by means of row and column communication channels 204, 206. All CU's 202 with the same input line number are connected to the same row communication channel 204. For example, CU's [1,1], [1,2] to [l,n] are connected to row communication channel number 1. CU's 202 with the same output line number are connected to the same column communication channel 206. For example, CU's [1,1], [2,1] to [m,l] are connected to column communication channel number 1. In other words, row communication channel 206, number 1 connects all

CU's that selectively establish communication between input line number 1 with any one of the n output lines 40. In the same manner, column communication channel 204 number 1 connects all CU's that selectively establish communication between any one of the m input lines 30 with output line number 1. Fig. 3 illustrates a switch fabric apparatus 11 according to the one embodiment of invention, in which the medium 60 of Fig. 1 is a crossbar medium (designated 80). For simplicity, a 4X4 crossbar is shown. Thus, the crossbar medium 80 includes a matrix of lines where the input lines 30 are in one dimension and the output lines 40 are at the other dimension. At each cross point of input line and output line resides a switch 216 that is able to actually link between the two lines. Thus, the switch fabric 11 is constructed such that the scheduler 20, the medium control 50 and medium 60 (as noted in Fig. 1) are physically attached, and for any CU 202, the on/off switch control 502 is directly connected to control switch 216 at the cross point. It should be noted that the invention is not limited to a direct control configuration. The CU's principal function is to decide whether or not a specific link will be made. The actual linking between the endpoints can be made non- directly, for example by utilizing a re-arrangeable non-blocking network.

Fig. 4 is a schematic illustration of a single computing unit (CU) 202 according to one embodiment of the invention. As described above, the CU is connected to a single row and a single column communication channels (channels 206, 204, respectively). The CU 202 is also connected to an on/off switch control 502.

The CU's 202 are each associated with a vector W that represents a value of a preference function of the corresponding CU's input-output pair. To this end, a single CU 202 is capable of determining in an autonomous and digital manner whether or not to establish a communication link between its respective pair of input and output lines. By this embodiment, this determination is accomplished by comparing the CU's W value (hereinafter CU's self W value) with the W values of the other CU's along the row and column communication channels and determining if the CU's self W value is the extreme (e.g. maximum or minimum).

According to one embodiment of the invention, the preference vector W may comprise up to 32 bits. In order to provide the optimal transmission configuration, the value of the vector W depends on the decision criteria, which characterized the overall performance of the switch. Typically, yet not exclusive, decision criteria such as throughput, latency and quality of service may be taken into consideration. Each of the specified decision criteria may be modified or avoided and/or others may be added, all as required depending upon the particular application. By providing a preference vector which may comprise 32 bits, the invention allows for the use of 4.3 billion (2 in power of 32) of different preference levels, thus providing a variety of optimization schemes for the switch performance, according to a variety of application needs.

Thus, in accordance with an embodiment of the invention, the preference factor W is an N-bit long vector constituted by at least one field from the following fields: priority, fairness, timing, machine state, row position, column position. For example, for a given CU, the priority field may includes 4 bits whose value is received in the input line of the CU. Note that by this example, the value of the so received priority bits was set by an external source. Additionally (or instead), internal fairness considerations may be implemented by designation of a field of a desired bit length, which reflects the transmission history for a desired time interval and time resolution.

The machine state field may reflect, per cycle, the ability of the buffer that is associated with the output line of the CU to accommodate a data unit to be transmitted. For example, a first machine state would indicate "full buffer" and a second machine state would indicate "non full buffer" (possibly with different values indicating different degrees of buffer occupancy).

Another field may designate a transmission configuration, in which only one data unit will be transmitted per input line (i.e. unicast transmission), or alternatively, a transmission configuration in which more than one data unit will be transmitted per input line (i.e. multicast transmission).

Note that the invention provides an efficient solution for avoiding or resolving conflicts in the matrix. Such a conflict may arise if two or more CU's (associated with the same row or the same column) determine that they hold an extreme value. In accordance with one embodiment such a conflict is resolved by providing a preference factor that allow the determination of a single extreme value only (in other words, the extreme value is unique). A unique identification field may be designated, for example, by expressing the unique row position and column position of a CU. A suitable decision criterion may also be designated to choose one of the conflicting CUs, for example by preferring the one having higher row and/or column numbers.

By one embodiment each of the CU's is also assigned with a request flag, to denote if its participation in the current computational cycle is required (i.e., if there is a data unit to be transmitted between its' corresponding input-output pair). The request flag may form part of the preference factor W.

Bearing this in mind, attention is drawn again to Fig. 4, showing the CU 202 having the following elements:

• Request flag module 208, for controlling the request flag.

• W module 210, for calculating the W vector value (possibly on the basis of data such as the 4 priority bits, as received at input line 211)

• Two arithmetic function modules 212, for comparing the CU's W factor along the row and column communication channels.

• Control logic module 214 for controlling the operation of the ON/OFF switch control 502. The W vector values may be assigned with different values during the preliminary stages as well as during runtime, either by the user/administrator/supporter or even automatically. Note that accessing the Request

Flag bit and W vector register (for writing or reading their respective values) can be realized in known er se techniques, e.g. parallel bus or serial interface.

The principal operating steps carried out by the switch fabric apparatus 10 in accordance with one embodiment, will be explained now with reference to Figs. 5-7.

Fig. 5A is a flow chart showing the principal operating steps carried out by the switch fabric apparatus 10. Each cycle of operation includes a computation cycle and a transmission cycle. During a computational cycle, the switch determines an optimal transmission configuration, i.e. defines for a participating row communication channel and column communication channel, an input-output pair to be actually linked (for unicast mode) and possibly more than one pair for the multicast mode. During the following transmission cycle, the actual linking is established through the medium according to the predetermined transmission configuration. Preferably, the computational cycle and the transmission cycle are synchronized so that the switch computes a transmission configuration (i.e. performs computational cycle ^') while transmitting data according to the configuration set at the previous computational cycle (i.e. computational cycle i+1).

By this embodiment the computational cycle is divided into three phases.

Phase 1 is the constraints definition phase, in which the CU's set their W factors.

Phase 2 is the resolution phase, in which the switching configuration is resolved by executing successive and rapid comparison iterations to define the optimal transmission configuration, i.e. to define for each row communication channel and for each column communication channel, the input-output pair to be actually connected. In other words, for a participating row and column, the CUs autonomously perform an iterative comparison process until one of them (for the unicast mode) determines itself to hold the extreme value and consequently allows connection between its corresponding input-output pair. At the end of the computation and transmission cycles, the switch performs, a medium configuration phase (constituting Phase 3), in which the medium is set to the new transmission configuration. By this embodiment, during Phase 1 and Phase 2, the medium is available to transmit data according to the transmission configuration set at the previous cycle of operation.

There follows now a more detail description of the various phases. Phase 1 (Step 10): A request flag is set by the request flag module 208, for each CU corresponding to an input-output pair that participates during this cycle. The flag requests are initiated by the input lines, which have data to transfer. Alternatively, the request flag value is received from an intermediate buffer or agent. For all CU whose Request Flag is set, the preference factor for this cycle is calculated and a corresponding W vector is set accordingly, by the W module 210.

The computational steps will be demonstrating in a non-limiting manner with respect to the "maximum embodiment of the invention", in which, as recalled, the scheduler defines per row and column, per computational cycle, at least one computing unit that holds the maximum value of the preference vectors along the corresponding row and column. According to another embodiment (the "minimum embodiment"), the scheduler defines per row and column, per computational cycle, at least one computing unit that holds the minimum value of the preference vectors along the corresponding row and column.

Phase 2: the scheduler resolves the switching configuration by executing successive rapid iterations by the participating CUs. By one embodiment, each iteration is a one-clock interval during which steps 20, 30 and 40 are implemented. The specified steps 20, 30 and 40 implement a so-called 'declare while compare' process. Thus, in Step 20: each CU declares its own W parameter while digitally comparing its own W parameter to the current value of RC (row channel) and CC (column channel). If the W parameter is extreme (i.e. higher or equal) compared to the current value of the RC, then the CU writes W onto the RC. Consequently, W becomes the current value of the RC. Similarly, if the W parameter is extreme (i.e. higher than or equal) compared to the current value of the CC, then the CU writes W onto the CC and consequently W becomes the current value of the CC.

During step 30, two simultaneous sub-steps are performed - steps 30a and 30b. Step 30a: the row arithmetic function module 212 digitally compares the

CU's W value with the current value of RC. If the CU's W value is lower than the current value of RC, then the CU removes its W parameter from the correspondence column communication channel for the next iteration (i.e., the row module disables the column module). This is implemented by a command transmitted from the row module 212 to the column module 212.

Step 30b: the column arithmetic function module 212 digitally compares the CU's W value with the current value of CC. If the CU's W value is lower than the current value of CC, then the CU removes its W parameter from the correspondence row communication channel for the next iteration (i.e., the column module disables the row module). This is implemented by a command transmitted from the column module 212 to the row module 212.

As a result of the specified "declare while compare" process, the row module and the column module exercise a mutual control scheme, to provide the following outcome: A CU unit that has its value as highest in both the row and the column will be called "up" or "selected". The rest CU's along the corresponding row and column are "down" or "unselected".

The state of a CU as "up" or "down", as determined in one iteration can be changed during a subsequent iteration. In the case of large number of input-output pairs, as well as the physical characteristics of the switch fabric (such as delays etc.), several iterations are needed for the extreme value of each row and the extreme value of each column to become stable (i.e. does not change after several iterations). Thus a CU may "flicker" between "up" and "down" status befor resolution is achieved. The "flickering" is allowed by the cross- coupling of the row and column modules, in which one either disables or enables the other, (as the case may be) to the subsequent iteration only. The row module is capable of enabling a disabled corresponding column module in the case that its preference vector value is greater than the preference vector values of other computing units along a common row channel, and the column module is capable of enabling a disabled corresponding row module in the case that its preference vector value is 5 greater than the preference vector values of other computing units along a common column channel.

While in 'disabled' status, the row arithmetic function module 212 digitally compares the CU's W value with the current RC value. If the CU's W value is found to be higher than the current RC value, then the row module enables the

10 column module, and the CU is enabled to declare its W parameter on the correspondence column communication channel for the next iteration.

In the same manner, while in 'disabled' status, the column arithmetic function module 212 digitally compares the CU's W value with the current CC value. If the CU's W value is found to be higher than the current CC value, then the 15 column module enables the row module, and the CU is enabled to declare its W parameter on the correspondence row communication channel for the next iteration.

Step 40: check if end criteria are met. Such end criteria may be the time criterion, stability of the highest values (i.e. no "flickering"), or a number of 20 iterations. The number M+1 may be used, M representing the number of W vectors to be compared (i.e., M is in the order of either m or n). Lower numbers, for example, M/4 may also be used, according to the application needs. Until the end criteria are met, steps 20-40 are iteratively operated.

At phase 3, the medium is set to the new configuration by performing step

25 60.

Step 60: each CU that finds itself at the end of the resolution process with the highest value of W, marks itself as "selected", and consequently, sets (through the medium control) the correspondence switch to the ON state.

For a better understanding, Fig. 5B exemplifies a flickering effect during the 30 operating steps of Fig. 5Ain a simplified 4X4 matrix and simplified start conditions. By this example, The request flag module determines that only the CUs [4,1] (designated 502), [4,4] (designated 504), [2,1] (designated 503), [2,3] (designated 506), [1,2] (designated 507) and [1,4] (designated 505) participate in the shown computational cycle. Fig. 5B(1) shows the start condition of phase 2, i.e. the W value that is assigned to each of the participating CUs. Fig. 5B(2) shows the condition at the end of the first iteration. Thus, the current RC value RCV on row channel no. 4 (RC 4) is 7 since CU [4,1] (502) holds the highest value on RC 4. However, CU [4,1] dose not holds the highest value CCN on column channel no. 1 (CC 1) which is 8 (CU [2,1] - 503). Thus, CU [4,1] is "down", and is removed from CC1 for the next iteration.

CU [4,4] (504), in turn, holds the highest value on CC 4 (6 as compared to 5 of CC 1,4 505). However, CU [4,4] (504) dose not holds the highest value RCV on RC 4, which is 7. Thus, CU [4,4] (504) is "down", and is removed from CC 4 for the next iteration. CU [2,1] (503) holds the highest value CCV on CC 1. However, CU [2,1] dose not hold the highest value RCV on RC 2, which is 9 (CU 2,3, 506). Thus, CU [2,1] (503) is "down", and is removed from CC 1 for the coming iteration.

CU [2,3] (506) holds the highest value - 9 - on both CC 3 and RC 2, and is "up". CU [1,2] (507) holds the highest value CCV on CC 2 (since it is the only participating one in this column). However, CU [1,2] (507) dose not hold the highest value RCV on RC 1, which is 5 (CU 505). Thus, CU [1,2] (507) is "down", and is removed from CC 2 for the next iteration.

Fig. 5B(3) shows the condition at the end of the next (second) iteration. CU [4,1] (502) is disabled on RC 4, but still holds the highest value on CC

4, as CU [2,1] (503) is disabled on CC1. Thus, CU [4,1] is "down", and is able to write its value on RC 4 in the next iteration.

CU [4,4] (504) holds the highest value on CC 4, as CU [4,1] is disabled on RC 4. CU [4,4] is disabled on CC 4. CU [4,4] is "down", and is able to declare its value on CC 4 in the next iteration. CU [2,1] (503) is disabled on CC 1, and dose not holds the highest value RCV on RC 2. Thus, CU [2,1] is "down", and is removed from CC 1 for the next iteration.

CU [2,3] (506) holds the highest value - 9 - on both CC 3 and RC 3, and is "up".

CU [1,2] (507) is disabled on CC 2, but holds the highest value CCV on RC

1, as CU [1,4] is disabled on RC 1. Thus, CU [1,2] is "down", and is able to declare its value on CC 2 in the next iteration.

Fig. 5B(4) shows the condition at the end of the next (third) and last iteration.

CU [4,1] (502) holds the highest value - 7 - on both RC 4and CC 1 (as CU [2,1] (503) is disabled on CC 1), and is "up".

CU [4,4] (504) is disabled on CC 4, and dose not holds the highest value RCV on RC 4, which is 7. Thus, CU [4,4] is "down". CU [2,1] (503) - no change.

CU [2,3] (506) - no change.

CU [1,2] (507) holds the highest value CCV on CC 2, but dose not holds the highest value RCV on RC 1, which is 5. Thus, CU [1,2] is "down".

CU [1,4] (505) holds the highest value on CC 4 (as CU [4,4] is disabled on CC 4), and also holds the highest value on RC 1. Thus, CU [1,4] is "up".

By the end of this iteration, the transmission configuration is resolved: CU

[4,1], [2,3] and [1,4] are "up", and consequently CU [4,1] establishes a communication link between input line 4 and output line 1 ; CU [2,3] establishes a communication link between input line 2 and output line 3, and CU [1,4] establishes a communication link between input line 1 and output line 4.

Fig. 6 is a more detailed schematic illustration of the single computing unit

(CU) according to one embodiment of the invention that includes a 2-dimensional configuration (i.e. row and column of the arithmetic function module 212, for performing the digital 'declare while compare' process of steps 20 - 40 of Fig. 5 A). Each of the modules 212 includes N logic cells LC_N. LC₀, that correspond to the N bits of W, respectively. The logic cells LC_N_ι-LC₀ perform the logical functions, bit-by-bit, and are coupled in a chain. As mentioned above, the row module and the column module are coupled to the RC channel 206 and CC channel 204 respectively and share them with all other modules along these channels. As may 5 be recalled, the two modules 212 are connected in a cross-coupled manner, to provide the mutual control scheme (the outcome of the simultaneous sub-steps 30a and 30b of Fig. 5A or sub-steps 30a-30d of Fig. 5B). Note that the cross-coupled architecture facilitates enabling of each of the modules 212 either by an external signal received from the control logic 214 or by an enabling signal that is received l o from the other module if certain conditions are met.

Each of the arithmetic function modules comprises N-bit logic cells. For m over n matrix (i.e. m rows and n columns - as illustrated e.g. in Fig. 2), all the n arithmetic function modules of the same row share the same bus of N bit long (207 in Fig. 2) (where N corresponding to the number of bits that constitute W). By the

15 same token, all the m arithmetic function modules of the same column share the same bus of N bit long (209 in Fig. 2) (where N corresponding to the number of bits that constitute W). Note that N is substantially independent of the values of m and n.

For a single dimension, i.e. along the row channel or the column channel,

20 the digital 'declare while compare' process is performed in the following manner. Each of the modules along the channel can write its vector on the shared bus at any time so that the modules of other CUs along the channel would "see" it and compare their vector value to the bus value to determine whether it contains the higher (or lowest) value. 5 The "declare while compare" process is done in a digital manner, i.e. bit by bit. The most-significant-bit of the channel is the first bit to be compared. Only those modules that having their vector's most significant bits (MSBs, i.e. bit # N-l) being higher or equal to the current bit value of the bus will stay active and write their MSBs onto the MSB of the bus. This procedure is now repeated for those

30 modules who stay active for bit # N-2, and so on, until bit #0. Note that those modules who will not "stay on" for the j bit (j<N) will be removed in the sense that they will not proceed with testing bits j-1 and onwards. Note that if a module "stays on" until the LSB (bit #0), this means that its W vector value is extreme and due to the writing process the current bus value is W. The conditional and digital character of the above-mentioned 'declare while compare' process allows it to be performed simultaneously by utilizing only a single bus per a single communication channel. This allow the switch fabric to support e.g. a large number of end-points (up to thousands), high bandwidth (up to lOOGbps), low switching times (less than 1 microsecond) and a plurality of decision criteria Fig. 7 is a more detailed schematic illustration of the module of Fig. 6, showing one way to implement it. This implementation utilizes an Active-Low N- lines bus with N static weak or dynamic pullup devices. When no module is active the bus is pulled to high voltage, defining a logic value of zero. Each module can be enabled at any time independently to the others. Since each line of the bus contains the value of zero as a default, a module will write only value of ONEs by pulling down the specific bus line using a local pulldown device.

Fig. 7 also shows the functional structure of the bit-logic cell of the module. As previously mentioned, in order to compare vectors having N-bits, N-bit logic cells are required for each module. The module also includes Boolean Function BF4. Each logic cell includes 3 Boolean Functions BF1-BF3, of which two (BFl and BF2) together with the pull-down transistor are required for the performance of the "declare while compare" process along one dimension. The third Boolean function BF3 as well as the above-mentioned cross-coupling of the paired modules through BF4, are required only when the modules are used in a two-dimensional vector-array.

Each of the logic cells received the following input signals: GEI (Great-Equal-In): When this input signal is high it indicates that the value of the vector composed by most significant bits (i.e.. all the bits to the left side of that specific bit) is either high or equal to the vector composed by the correspondence lines of the bus. GRI (Great-In): When this input signal is high it indicates that the value of the vector composed by most significant bits (i.e. all the bits to the left side of that specific bit) is high in comparison to the vector composed by the corresponding lines of the bus. RE (Wright-Enable): This global signal enables the module and is high when the Request Flag (208 in Fig. 3) is high.

BIT: Contains one bit value of the W vector (210 in Fig. 3).

Each of the Bit Logic cells has the following output signals:

GEO (Great-Equal-Out): This signal is high when the value of the vector, which composed of the bits to the left of this cell (and including the bit value of this cell) is either equal or high to the corresponding bus lines value.

GRO (Great-Out): This signal is high when the value of the vector, which composed of the bits to the left of this cell (and including the bit value of this cell) is higher than the correspondence bus lines value. Each of the Bit Logic cells has the following bi-directional lines:

DL (Data-Low): Each of the bit logic cells interfaces the corresponding bus line through the DL line. The DL signal is used by the bit logic cell for either reading the bus line value or for writing the BIT value to the bus line. The DL in this exemplary implementation, is active low (i.e. zero value is logical one and vice versa).

All the bit logic cells of a single module are connected in a chain, together with the BF4, in the following manner: the GEI input of a certain bit is connected to the GEO output of the left side neighbor. The same applies for the GRI input, which is connected to the GRO output of the left side neighbor. The RE signal is connected in parallel to all bit logic cells. BF4 received the chained GEO and GRO signals as its input, and produce its output signal GE FINAL, which is the output signal of the module as a whole.

The mutual control scheme of the paired module is achieved in the following manner. For the most left bit logic cell, the GRI is connected to ZERO value and the GEI is connected to an enable signal, which is received from the Control Logic function (214 in Fig. 3), and which is the GE_FINAL output of the other module (e.g. for the row module, the "other" module is the column module, and vise versa). By sending a disabling signal, one module (e.g. row) can remove the other (e.g. column) from the channel (Step 30 of Fig. 5). The operation of the Boolean functions will be explained with respect to the bit-logic cell no. I (N-1>=I>=0), as follows.

BFl:

The BFl enables writing value of ONE (i.e. WD is high) to the corresponding bus line I only if following conditions are met: (1) The module is enabled (i.e. RE is high).

(2) The value of the sub-vector composed of the vector bits N-l to 1+1 is either greater or equal to the bus value composed of lines N-l to 1+1 (i.e. GEI is high).

(3) The value of bit I in the vector is ONE (i.e. the BIT value is logic "1").

When WD is high, it enables the pull-down transistor to pull the DL line down to low value, in order to represents logical "1" due to the active low nature of the bus.

BF2 of logic cell I determines whether the sub-vector composed of vector bits N-l to I is greater or equal to the corresponding value of bus lines N-l to I, and sets the signal GEO to ONE if true. This signal is an input to the BF2 of the 1-1 cell. The conditions for setting GEO to ONE are:

(1) The GEO signal of bit-logic 1+1 (defined as GEI) is ONE.

(2) The value of bit I of the vector is not smaller than the value of bus line I. Thus, BF2 sets the GEO output to high if the BIT value is not lower than the correspondence bus line value, and GEI is high.

BF3 reads the bus value and compares the BIT value to the bus value. BF3 sets the GRO output to high if the corresponding bus line value is higher than the

BIT value. But if the GRI is high, then the GRO is set to high independently of the bus line value. Thus, BF3 produces GRO high when the module is disabled and the BIT value of the specific cell as well as the BIT value of the cells to its left is greater than the corresponding bus line values. This Boolean function is require due to the possibility of a lockup situation in which both the row and column modules are disabling each other and avoiding recovery when the buses value changes. A lockup situation may accrue, in which one module (say the row module) disables the other one due to a correct detection of being smaller along the row, but the column module acquire wrong detection along the column, to be changed later on. If the two modules are to be crossed coupled only by the corresponding GEO signals, they will not be able to responds to the status change along the column. BF3 overcomes this problem by detecting situations when the vector value is higher than the bus, even if this vector can't write its W value to the bus (i.e. when GEO is low).

BF4: this function performs logical OR between the last GEO and the chained GRI output signals, to produce the GE_FINAL signal which is used by the Control Logic module 214 to set the GEI signal of the paired module. Thus, BF4 set the GE_FINAL signal to low if GEO is low and GRO is low (i.e. when BIT is lower than the bus value). In all other cases, BF4 sets the GE_FINAL signal to high.

The Control Logic module 214 receives both GE_FINAL signals, from the row module and from the column module. Both signals are high only when GEO is high and GRO is high for both modules. Only in this case, the Control Logic module 214 set the control switch to ON, to allow data transmission.

Reference is again drawn to Fig. 5A, together with Fig. 7, in order to further describe the digital "declare while compare" operation of step 20, as follows: All modules that are allowed to participate in the "declare while compare process" (i.e. when enabled by both EN signal and the cross-coupled GE Final signal), will eventually write their value to the channel either in full, partially, or none, as the case may be. A module will write its MSB bits (from left to right) that are either equal to or greater than the channel value, while all the remaining LSB bits are not allowed to be written. At the end of a single comparison process, only the "inclusive extreme" modules will eventually write their W in full, while all other modules will still partially participate in writing their MSB bits that are equal to the channel value, disabling all other LSB's bits from writing. The process in which a module disables itself from writing to the channel is a bit-by-bit process, which is part of the comparison operation of step 20 of Fig. 5 A, and is performed by the elements BFl and BF2 of Fig. 7.

As mentioned above, the invention can be implemented in one dimension only, by utilizing elements BFl and BF2 of Fig. 7 and performing steps 10, 20, 40 and 60 of Fig. 5 A. By that, according to one embodiment, the invention provides a scheduling module comprising N logic cells that are connected in a chain such that the input signal of the first cell is the input signal of the module and the output signal of the last cell is the output signal of the module. The module is further associated with an N-bit long vector for determining in an autonomous and digital manner if said vector holds an extremity value as compared to the values of M-1 vectors, associated with M-1 scheduling modules respectively, the modules constitute together M scheduling modules that share a communication channel having N lines. Each of the modules is capable of determining if its associated vector holds said extremity value, substantially simultaneous to the operation of the other M-1 scheduling modules, including: each of said N logic cell corresponds to one bit of said associated N-bit vector and is capable of determining the ratio between said bit value and the communication channel bit value as being one of a group consisting of: (i) either greater than or equal to, (ii) either lower than or equal to.

According to one embodiment, each of the N logic cells is capable of participating in the above mentioned 'declare while compare' process, i.e., logic cell number I is capable of writing its corresponding bit value to the I line of said shared communication channel if the value of a sub-vector comprising the vector bits N-l to 1+1 is one of a group consisting of (i) either greater than or equal to the communication channel value composed of lines N-l to 1+1, or (ii) either lower than or equal to the communication channel value composed of lines N-l to 1+1, I being an integer number between 0 to N-l .

It should be noted that in the two-dimension configuration, the cross- coupling disabling signal is an outcome of the entire module operation at the end of an iteration, rather than of the bit-by-bit process as described above.. It should also be noted that the function of BF3 and the purpose of the GR signal are to allow enabling the other module, in case this module is disabled (i.e. its BFl and BF2 are not in operation) and the enabling conditions are met, otherwise the GR signal is redundant to the GE signal. Thus, the module that disables the other is still enabled and continues to participate in the "declare while compare" process.

The operation of the module 212 may be asynchronous in the sense that it can be seen as a whole combinatorial function that does not need a clock or a synchronized signal to control the flow between the logic bits or between different computing units sharing the same channel. The module 212 is instantly responsive to any changes of the bus value, which result from other modules along the channel, being either enabled or disabled, or vector values, which were changed.

The scheduling module and the computing unit of the invention can be implemented on silicon. The computing unit and the switch, enable comparison of a large number of vectors in very fast way, having the number of interconnect lines very low and not depended upon the number of vectors. Moreover, the silicon area that occupied by the arithmetic function module is very small, allowing to compose a module of N bits by chaining N logic cells together with substantially no additional overhead.

The invention has been described here in relation to switching and routing in digital communication systems such as data communication or telecommunication systems. However, the invention is not limited to the above applications and may be utilized to support other applications such as sharing computing resources between processing tasks.

The present invention has been described with a certain degree of particularity, but those versed in the art will readily appreciate that various alterations and modifications may be carried out without departing from the scope of the following Claims:

Claims

CLAIMS:

1. A switch fabric apparatus for establishing communication between switch endpoints of a medium; the endpoints constituting m input lines over n output lines such that a communication link is selectively established between pairs of input and output lines; the switch fabric apparatus comprises:

- a scheduler that includes m over n computing units operating in parallel; each computing unit is associated to an input line from among said n input lines and to an outline from among said m output lines and capable of determining in an autonomous and digital manner whether or not to establish a communication link in said medium between its respective pair of input and output lines.

2. A switch fabric apparatus for establishing communication between endpoints of a medium; the endpoints constituting m input lines over n output lines such that a communication link is selectively established for transmission of data units between pairs of input and output lines during each one of a succession of computational cycles; the switch fabric apparatus comprises: a scheduler that includes m over n computing units operating in parallel and arranged in a matrix of m rows over n columns that correspond to said n input lines and m output lines, constituting m row channels and n column channels; each computing unit is associated to an input line from among said n input lines and to an output line from among said m output lines; each computing unit is selectively associated with a preference vector; each computing unit includes a row module and a column module which are cross-coupled; said row module and column module are capable of determining for each computational cycle whether the associated preference vector value is extreme as compared to the preference vector values of other computing units along the row channel and the column channel, and if in the affirmative to facilitate a communication link between the associated input and output lines; said computational cycle is divided to a succession of computational iterations during each of which, in parallel and in a digital manner: i) the row module is capable of determining whether its preference vector value is inclusive extreme as compared to the preference vector values of other computing units along a common row channel; in the case of

3. A switch fabric apparatus according to claim 2 wherein:

- said preference vector is N-bit long;

- said row channels and m column channels each comprises an N-line sheared bus; - the row module and the column module each comprises N logic cells coupled in a chain; each of the N logic cells of each module is associated with a corresponding one of the N bits of said preference vector;

- each logic cells is capable of determining whether its corresponding bit have an "inclusive extreme" value as compare to the corresponding bit values on the same bus line; in the case of "inclusive extreme" result write its preference vector bit value on the corresponding bus line, and in the case of "no inclusive extreme" result produces a disabling signal to disable the respective cross-coupled module; and - each logic cells is capable of determining whether its corresponding bit have an "exclusive extreme" value as compare to the corresponding bit values on the same bus line and in the case of an "exclusive extreme" result produces an enabling signal to enable the respective cross- coupled module.

4. A switch fabric apparatus according to claim 2 or 3 wherein said row module and column module are capable of determining for each computational cycle whether the associated preference vector value is extreme and unique as compared to the preference vector values of other computing units along the row channel and the column channel, and if in the affirmative to facilitate a communication link between the associated input line and output line.

5. A switch fabric apparatus according to claim 2 to 3 wherein said N-bit long preference vector is constituted by at least one field from the following fields: priority, fairness, timing, machine state, row position, column position.

6. A switch fabric apparatus according to claim 4 wherein at least one of said fields is able to receive different bit values for different computational cycles.

7. A switch fabric apparatus according to any one of claims 2 to 5 wherein said row module and column module are capable of determining for each computational cycle whether the associated preference vector value has maximum value as compared to the preference vector values of other computing units along the row channel and the column channel, and during each of said computational iterations, in parallel and in a digital manner:

(i) the row module is capable of determining whether its preference vector value is greater than or equal to the preference vector values of other computing units along a common row channel; in the case of "inclusive maximum" result write its preference vector value on the row channel, and in the case of "no inclusive maximum" result disable the corresponding column module; (ii) the column module is capable of determining whether its preference vector value is greater than or equal to the preference vector values of other computing units along a common column channel; in the case of

"inclusive maximum " result write its preference vector value on the column channel, and in the case of "no inclusive maximum" result disable the corresponding row module; (iii) the row module is capable of enabling a disabled corresponding column module in the case that its preference vector value is greater than the preference vector values of other computing units along a common row channel; and (iv) the column module is capable of enabling a disabled corresponding row module in the case that its preference vector value is greater than the preference vector values of other computing units along a common column channel.

8. A switch fabric apparatus according to claims 2 to 6 wherein said row module and column module are capable of determining for each computational cycle whether the associated preference vector value has minimum value as compared to the preference vector values of other computing units along the row channel andthe column channel, and during each of said computational iterations, in parallel and in a digital manner:

(i) the row module is capable of determining whether its preference vector value is lower than or equal to the preference vector values of other computing units along a common row channel; in the case of "inclusive minimum" result write its preference vector value on the row channel and in the case of "no inclusive minimum" result disable the corresponding column module;

(ii) the column module is capable of determining whether its preference vector value is lower than or equal to the preference vector values of other computing units along a common column channel; in the case of "inclusive minimum " result write its preference vector value on the column channel and in the case of "no inclusive minimum" result disable the corresponding row module; (iii) the row module is capable of enabling a disabled corresponding column module in the case that its preference vector value is lower than the preference vector values of other computing units along a common row channel; and (iv) the column module is capable of enabling a disabled corresponding row module in the case that its preference vector value is lower than the preference vector values of other computing units along a common column channel.

9. A switch fabric apparatus according to any one of claims 2 to 6 wherein said associated preference vector value is unique along said row channel and column channel.

10. A switch fabric apparatus according to any one of claims 2 to 8 wherein said data unit is a packet.

11. A switch fabric apparatus according to any one of claims 2 to 8 wherein said data unit is an asynchronous mode transmission (ATM) cell.

12. A switch fabric apparatus according to any one of claims 2 to 10 wherein said medium is a crossbar having n over m cross points, each cross point corresponds to a pair of input and output ports, and wherein the communication link between said pair of input and output lines is established by the respective computing unit having direct control over the respective cross point.

13. The switch apparatus according to claim 12 wherein at least one of said input port and output port each constitute a dual input/output port.

14. A switch fabric apparatus according to any one of claims 3 to 13 wherein the number N is substantially independent of the values of m and n.

15. A switch fabric apparatus for establishing communication between endpoints of a medium; the endpoints constituting m input lines over n output lines such that a communication link is selectively established for transmission of a data unit between pairs of input and output lines during each one of a succession of computational cycles; the switch fabric apparatus comprises: a scheduler that includes m over n computing units operating in parallel and arranged in a matrix of m rows over n columns that correspond to said n input lines and m output lines, constituting m row channels and n column channels; each computing unit is associated to an input line from among said n input lines and to an output line from among said m output lines; each computing unit is selectively associated with a preference vector; each computing unit includes a row module and a column module which are cross-coupled; said row module and column module are capable of determining for each computational cycle whether the associated preference vector value is extreme and unique as compared to the preference vector values of other computing units along the row channel and the column channel, and if in the affirmative to facilitate a communication link between the associated input line and output line.

16. The switch fabric apparatus of Claim 15, wherein said computational cycle is divided to a succession of computational iterations during each of which, in parallel and in a digital manner:

(i) the row module is capable of determining whether its preference vector value is inclusive extreme as compared to the preference vector values of other computing units along a common row channel; in the case of

"inclusive extreme" result write its preference vector value on the row channel and in the case of "no inclusive extreme" result disable the corresponding column module; (ii) the column module is capable of determining whether its preference vector value is inclusive extreme as compared to the preference vector values of other computing units along a common column channel; in the case of "inclusive extreme" result write its preference vector value on the column channel and in the case of "no inclusive extreme" result disable the corresponding row module; (iii) the row module is capable of enabling a disabled corresponding column module in the case that its preference vector value is exclusive extreme as compared to the preference vector values of other computing units along a common row channel; and (iv) the column module is capable of enabling a disabled corresponding row module in the case that its preference vector value is exclusive extreme as compared to the preference vector values of other computing units along a common column channel.

17. A switch fabric apparatus for establishing communication between endpoints of a medium; the endpoints constituting m input lines over n output lines such that a communication link is selectively established for transmission of data units between pairs of input and output lines during each one of a succession of computational cycles; the switch fabric apparatus comprises: a scheduler that includes m over n computing units operating in parallel and arranged in a matrix of m rows over n columns that correspond to said n input lines and m output lines, constituting m row channels and n column channels; each computing unit is associated to an input line from among said n input lines and to an output line from among said m output lines; each computing unit is selectively associated with a preference vector; each computing unit includes a row module and a column module which are cross-coupled; said row module and column module are capable of determining for each computational cycle whether the associated preference vector value is extreme as compared to the preference vector values of other computing units along the row channel and the column channel, and if in the affirmative to facilitate a communication link between the associated input and output lines; said computational cycle is divided to a succession of computational iterations during each of which, in parallel and in a digital manner:

(i) disabling an enabled row module of the computing unit if disable conditions are met or enabling a disabled row arithmetic function module of the computing unit if enable conditions are met; and (ii) disabling an enabled column module of the computing unit if disable conditions are met or enabling a disabled column arithmetic function module of the computing unit if enable conditions are met.

18. A switch fabric apparatus according to claim 17 wherein: - said preference vector is N-bit long;

- said row channels and m column channels each comprises an N-line sheared bus;

- the row module and the column module each comprises N logic cells coupled in a chain; each of the N logic cells of each module is associated with a corresponding one of the N bits of said preference vector;

- each logic cells is capable of determining whether its corresponding bit have an "inclusive extreme" value as compare to the corresponding bit values on the same bus line; in the case of "inclusive extreme" result write its preference vector bit value on the corresponding bus line, and in the case of "no inclusive extreme" result produces a disabling signal to disable its own module as well as the respective cross-coupled module; and

- each logic cells is capable of determining whether its corresponding bit have an "exclusive extreme" value as compare to the corresponding bit values on the same bus line and in the case of an "exclusive extreme" result produces an enabling signal to enable its own module as well as the respective cross-coupled module.

19. A switch fabric apparatus according to claim 17 or 18 wherein said N-bit long preference vector is constituted by at least one field from the following fields: priority, fairness, timing, machine state, row position, column position.

20. A switch fabric apparatus according to claim 19 wherein at least one of said fields is able to receive different bit values for different computational cycles.

21. A switch fabric apparatus according to any one of claims 17 to 20 wherein said row module and column module are capable of determining for each computational cycle whether the associated preference vector value has maximum value as compared to the preference vector values of other computing units along the row channel and the column channel, and during each of said computational iterations, in parallel and in a digital manner: (i) the row module is capable of determining whether its preference vector value is greater than or equal to the preference vector values of other computing units along a common row channel; in the case of "inclusive maximum" result write its preference vector value on the row channel, and in the case of "no inclusive maximum" result disable disable the corresponding column module;

(ii) the column module is capable of determining whether its preference vector value is greater than or equal to the preference vector values of other computing units along a common column channel; in the case of

"inclusive maximum " result write its preference vector value on the column channel, and in the case of "no inclusive maximum" result disable the corresponding row module;

(iii) the row module is capable of enabling a disabled corresponding column module in the case that its preference vector value is greater than the preference vector values of other computing units along a common row channel; and

(iv) the column module is capable of enabling a disabled corresponding row module in the case that its preference vector value is greater than the preference vector values of other computing units along a common column channel.

22. A switch fabric apparatus according to claims 17 to 20 wherein said row module and column module are capable of determining for each computational cycle whether the associated preference vector value has minimum value as compared to the preference vector values of other computing units along the row channel and the column channel, and during each of said computational iterations, in parallel and in a digital manner: (i) the row module is capable of determining whether its preference vector value is lower than or equal to the preference vector values of other computing units along a common row channel; in the case of "inclusive minimum" result write its preference vector value on the row channel and in the case of "no inclusive minimum" result disable disable the corresponding column module;

(ii) the column module is capable of determining whether its preference vector value is lower than or equal to the preference vector values of other computing units along a common column channel; in the case of "inclusive minimum " result write its preference vector value on the column channel and in the case of "no inclusive minimum" result the corresponding row module;

(iii) the row module is capable of enabling a disabled corresponding column module in the case that its preference vector value is lower than the preference vector values of other computing units along a common row channel; and

(iv) the column module is capable of enabling a disabled corresponding row module in the case that its preference vector value is lower than the preference vector values of other computing units along a common column channel.

23. A switch fabric apparatus according to any one of claims 17 to 22 wherein said associated preference vector value is unique along said row channel and column channel.

24. A switch fabric apparatus according to any one of claims 17 to 23 wherein said data unit is a packet.

25. A switch fabric apparatus according to any one of claims 17 to 23 wherein said data unit is an asynchronous mode transmission (ATM) cell.

26. A switch fabric apparatus according to any one of claims 17 to 25 wherein said medium is a crossbar having n over m cross points, each cross point corresponds to a pair of input and output ports, and wherein the communication link between said pair of input and output lines is established by the respective computing unit having direct control over the respective cross point.

27. The switch apparatus according to claim 26 wherein at least one of said input port and output port each constitute a dual input/output port.

28. A switch fabric apparatus according to any one of claims 18 to 27 wherein the number N is substantially independent of the values of m and n.

29. A scheduling module comprising N logic cells that are connected in a chain; an input signal of a first cell among said N logic cells is the input signal of said module and an output signal of a last cell among said N logic cells is the output signal of said module; said module is further associated with an N-bit long vector, for determining in an autonomous and digital manner if said vector holds an extremity value as compared to the values of M-1 vectors, associated with M-1 scheduling modules respectively; said module and M-1 modules constitute together M scheduling modules that share a communication channel having N lines; said module is capable of determining if its associated vector holds said extremity value, substantially simultaneous to the operation of said M-1 scheduling modules, including:

- each of said N logic cell corresponds to one bit of said associated N-bit vector and is capable of determining the ratio between said bit value and the communication channel bit value as being one of a group consisting of: (i) either greater than or equal to, (ii) either lower than or equal to.

30. A scheduling module according to claim 29 wherein the number N is substantially independent of the values of the number M.

31. A scheduling module comprising N logic cells that are connected in a chain; an input signal of a first cell among said N logic cells is the input signal of said module and an output signal of a last cell among said N logic cells is the output signal of said module; said module is further associated with an N-bit long vector, for determining in an autonomous and digital manner if said vector holds an extremity value as compare to the values of M-1 vectors, associated with M-1 scheduling module respectively; said module and M-1 module constituting together M scheduling modules that share a communication channel having N lines; said module is capable of determining if said vector holds said extremity value including:

- each logic cell corresponds to one bit of said associated vector and is capable of determining the ratio between said bit value and the communication channel bit value as being one of a group consisting of: equal to, higher than, lower than; and

- logic cell number I is capable of writing its corresponding bit value to the I line of said shared communication channel if the value of a sub-vector comprising the vector bits N-l to 1+1 is one of a group consisting of (i) either greater than or equal to the communication channel value composed of lines N-l to 1+1, or

(ii) either lower than or equal to the communication channel value composed of lines N-l to 1+1, I being an integer number between 0 to N-l .

32. A scheduling module according to claim 31 wherein the number N is substantially independent of the values of the number M.