WO2003030261A1

WO2003030261A1 - Semiconductor memory device and corresponding manufacturing method

Info

Publication number: WO2003030261A1
Application number: PCT/EP2001/011344
Authority: WO
Inventors: Massimo Atti; Christoph Deml
Original assignee: Infineon Technologies Ag
Priority date: 2001-10-01
Filing date: 2001-10-01
Publication date: 2003-04-10
Also published as: EP1433205A1

Abstract

This invention provides a semiconductor memory device and a corresponding manufacturing method. The semiconductor memory device comprises a semiconductor substrate (21) having a first conductivity (p) type; a plurality of trenches (29) provided in said substrate (21) running in parallel in a first direction (y), said trenches being filled with an isolation material (215; 215a-e); said trenches (29) defining a plurality of strip regions (220a-f, 301) of said substrate (21) lying between each pair of adjacent trenches (29); a plurality of gate structures (230, 240, 250; 230, 240', 250'; 230, 240, 270, 250'') for storing charge in a non-volatile manner arranged above the surface of the semiconductor substrate (21) and electrically isolated therefrom; said plurality of gate structures (230, 240, 250; 230, 240', 250'; 230, 240, 270, 250'') being arranged in strips (ST1-3) running in parallel in a second direction (x) and crossing said strip regions (220a-f, 301); a plurality of wordlines (WL1'-WL9'; 260, 260', 260''), a respective one being arranged on each of said gate structures (230, 240, 250; 230, 240', 250'; 230, 240, 270, 250''); and a plurality of active regions (S1'-S6') of the second conductivity (n+) type, each of said active regions (s1'-S6') being arranged at one end of a corresponding strip (220a-f, 301) and being electrically connectable to the gate structures (230, 240, 250; 230, 240', 250'; 230, 240, 270, 250'') of said corresponding strip (220a-f, 301).

Description

DESCRIPTION

Semiconductor Memory Device and corresponding Manufacturing Method

The present invention relates to a semiconductor memory device and a corresponding manufacturing method.

S. K. Lahiri: MNOS/Floating-Gate Charge Coupled Devices for High Density EEPROMs: A New Concept, Physics of Semiconductor Devices, V. Kumar and S. K. Agarwal (eds.), Narosa Publishing House, New Dehli, India, 1998, pages 951 - 956, the basic idea of CCD EEPROMS is known. Particularly, this conference paper discloses the general idea to arrange EEPROM gate structures each having a floating and a control (CCD) gate above a substrate in rows separated by rails of active areas or injectors provided in said substrate. However, S. K. Lahiri fails to disclose a suitable memory address scheme for such a CCD EEPROM taking into consideration a dynamic clocking. Moreover, this document also fails to disclose appropriate cells layouts and operation modi.

For example, CCD devices are known from W. S. Boyle, G. E. Smith: Charge Coupled Semiconductor Devices. The Bell Sys- tern Technical Journal. American Telephone and Telegraph

Company: New York, April 1970. Pages 587-593; Rudolf Mϋl- ler: Bauelemente der Halbleiter-Elektronik. Springer Ver- lag: Berlin, Heidelberg, New York, London, Paris, Tokyo 1987. Seiten 192-195; Kurt Hoffmann: VLSI-Entwurf . Modelle und Schaltungen. Oldenbourg Verlag: Munchen, Wien 1996. Seiten 296-297; and Lev I. Berger: Semiconductor Materials. CRC-Press: 1997. Page 445.

EEPROM devices are generally well known in the state of the art. EEPROM cells are used to store information, which should be still accessable after switching the power supply off and on again, while being able to modify the stored information multiple times by pure electrical means. EEPROM cells usually have source and drain contacts forming a MOS transistor. Information is read out by measuring the attributes of the output characteristic, which is dependent of the information stored in a gate structure having floating and control gate.

The overall transfer characteristic (programming conditions to read current) is highly nonlinear and strong dependent on several side effects and production fluctuations. I.e. the Fowler Nordheim tunneling current is more than exponentially dependent on the electric field across the oxide. So the programming voltage and the oxide thickness have severe influence on the programming process. Thus, these parameters must be adjusted with high precision. These accuracy problems limit the multilevel ability of known cell concepts to 2 bits per cell.

Fast cells are critical and must be handled with complex algorithms. Usually, only cells of a single wordline can be programmed at the same time. During sensing, there is a static current consumption through S and D of the MOS tran- sistor. During parallel programming of cells in the test phase, there is a static current due to the gate induced drain leakage, which must be supplyed by a charge pump. This current driving pump is area consuming.

Using drain and source contacts, the cell area of typical cells in embedded EEPROM modules results in 22*F² to 70*F². The world record for cells with drain and source contacts is 8.8*F².

Nowadays new applications for non-volatile memories are borne, one of that is the possibility to store photos or music in solid state device. In this kind of application is required a sequential data access to the memory.

Therefore, it is an object of the present invention to provide an improved semiconductor memory device and a corresponding manufacturing method.

According to the present invention this object is achieved by the device defined in claim 1 and the method defined in claim 11.

The idea underlying the present invention is to combine the charge shifting, receiving or providing (from now on de- noted only by shifting) ability and the possibility to store charge non-volatile in an oxide or on a floating gate (EEPROM) or a similar structure. The device or memory cells according to the invention will therefore be called charge coupled EEPROM cells or CC-EEPROM cells hereinbelow. In fact, by combining CCD and EEPROM technologies, it is possible to increase the density of the memory and - at the same time - to build a non-volatile memory that is sequentially addressable itself and even usable as a volatile memory.

CCD technique is known to operate with 8 bit resolution. In combination with the linear transfer characteristic of the charge coupled EEPROM and the self limiting programming, this should provide deep multilevel ability. Fast cells do not have any influence on the programming process, because the programming stops, when all charge carriers tunneled to the floating gate. It is possible, to shift charge carriers into the cell area and to program a huge number of wordli- nes in parallel. This cuts the programming time of some order of magnitude. There is no static current consumption during read. Minimum size cells (4F²) are possible, because the cell does not have drain or source contacts. Reduction of logic in the bitline and wordline section result in less chip area. There is an additional volatile memory functionality (i.e. using the same technology, it is also possible to implement high density memory buffer) .

Preferred embodiments are listed in the respective depend- ent claims.

According to a preferred embodiment, said gate structures include a stack of a tunnel oxide, a floating gate, and an isolation structure. According to another preferred embodiment, said active regions are arranged at different ends of neighboring strips.

According to another preferred embodiment, said active re- gions are electrically connectable to the gate structures of said corresponding strip by means of a respective control gate structure.

According to another preferred embodiment, said respective control gate structure runs in parallel with the respective outermost gate structures at the corresponding end.

According to another preferred embodiment, every third of said wordlines is connected to a common wiring line.

According to another preferred embodiment, said second and first directions are perpendicular to each other.

According to another preferred embodiment, the doping con- centration of the substrate is varied in a surface region of the strip regions.

According to another preferred embodiment, a region of the second conductivity type is buried in the substrate along the strip regions.

According to another preferred embodiment, said gate structures, said wordlines and said trenches have minimum design width F forming a cell dimension of 4F². According to another preferred embodiment, there are the steps of providing said trenches by means of an etching process using a hard mask, providing an oxide layer on the inner surface of said trenches; depositing a layer of said isolation material on the resulting structure; planarizing said layer of said isolation material by a chemical-mechanical polishing process such that it levels with said hard mask.

According to another preferred embodiment, there are the steps of removing said hard mask, providing a tunnel oxide layer and a first polysilicon layer over the resulting structure, and planarizing said first polysilicon layer by a chemical-mechanical polishing process such that it levels with said isolation material for forming a floating gate region.

According to another preferred embodiment, there are the steps of providing a third polysilicon layer over the re- suiting structure, and patterning said third polysilicon layer for forming an extension of said floating gate region.

According to another preferred embodiment, there are the steps of providing an isolation layer having contact holes between the first and third polysilicon layer, said contact holes being arranged for providing an electrical connection between said first and third polysilicon layer. This has the advantage that in the patterning step of the third polysilicon layer the isolation layer may act as etching stop preventing damage of the first polysilicon layer, if there is a mask misalignment.

According to another preferred embodiment, there are the steps of removing said hard mask, providing a tunnel oxide layer and a first polysilicon layer over the resulting structure, and patterning said first polysilicon layer for forming a floating gate region which partly overlaps said isolation material in said trenches.

According to another preferred embodiment, there are the steps of providing an isolation layer and a second polysilicon layer for forming a control gate region over the resulting structure; and forming said plurality of gate structures by patterning said tunnel oxide layer, first polysilicon layer, isolation layer and second polysilicon layer.

According to another preferred embodiment, there is at least one of the steps of enhancing the doping concentration of the substrate in a surface region of the strip regions by means of a first implantation step and burying a region of the second conductivity type in the substrate along the strip regions by means of a second implantation step.

Embodiments of the present invention are illustrated in the accompanying drawings and described in detail in the following. In the Figures:

Fig. 1 shows a CC-EEPROM cell arrangement;

Fig. 2 shows the erase mode for a specific gate structure of the CC-EEPROM cell arrangement;

Fig. 3 shows the channel hot electron programming mode £αr__a_specif1c_gate_s_trucjtur_e_oE_th.e_CC_-EEPROM__ cell arrangement;

Fig. 4 shows the Fowler Nordheim programming mode for a specific gate structure of the CC-EEPROM cell arrangement;

Fig. 5a, b show the adjust charge mode for programming a limited charge for a specific gate structure of the CC-EEPROM cell arrangement;

Fig. 6a-c show the charge shifting mode for shifting a limited charge for a specific gate structure of the CC-EEPROM cell arrangement;

Fig. 7 shows the Fowler Nordheim programming mode for programming a limited charge for a specific gate structure of the CC-EEPROM cell arrangement;

Fig. 8 shows the NAND reading mode for a specific gate structure of the CC-EEPROM cell arrangement; Fig. 9a,b show the adjust charge mode for reading a limited charge for a specific gate structure of the CC- EEPROM cell arrangement; and

Fig.lOa-c show the charge sink and sense amplifier for a specific gate structure of the CC-EEPROM cell arrangement;

Fig. 11 shows a_ possible two-dimensional CC-EEPROM __.cell_ arrangement;

Fig. 12a-j show a schematic cross-sectional illustration of processing steps for manufacturing the two- dimensional CC-EEPROM cell arrangement according to a first embodiment of the present invention in the wordline direction;

Fig. 13 shows a schematic cross-sectional illustration corresponding to the process status of Fig. 12j perpendicular to the wordline direction;

Fig. 14 shows a top view of a two-dimensional CC-EEPROM cell arrangement according to the first embodi- ment of the present invention;

Fig. 15a, b show a schematic cross-sectional illustration of processing steps for manufacturing the two- dimensional CC-EEPROM cell arrangement according to a second embodiment of the present invention in the wordline direction; and

Fig. 16a-c show a schematic cross-sectional illustration of processing steps for manufacturing the two- dimensional CC-EEPROM cell arrangement according to a third embodiment of the present invention in the wordline_diχection.₁_

Throughout the figures the same reference numbers indicate the same or funtionally equivalent means. It should be noted that the individual figures for explaining specific modes of operation do not include all details, but just the details needed for explaining the respective mode.

Fig. 1 shows a CC-EEPROM cell arrangement in a schematic representation.

In Fig. 1, reference sign 1 denotes a p-type semiconductor substrate, f.e. a silicon substrate, having an n⁺-type source and drain region 10 and 20, respectively, and having a p⁺-type body contact 30.

Between the n⁺-type source and drain regions 10, 20 there is a plurality of aligned gate structures. The gate structures include floating gates FG1, FG2, ..., FGn-1, and FGn above the substrate surface and electrically isolated therefrom. Moreover, each of the floating gates FG1, FG2, ..., FGn-1, and FGn has a corresponding control gate CGI, CG2, ..., CGn-1, CGn which is electrically isolated therefrom. Thus the gate structures are similar to the gate structure of an EEPROM, however, here a plurality of gate structures each consisting of a floating and control gate pair is aligned with preferably equidistant spacing.

S, Gl, G2, ..., Gn-1, Gn, D, B denote respective contacts of the corresponding source, drain, bulk, and gate regions. JDnly_ schematically shown in_Fig.. 1 is a voltage generation means 100 for applying individual voltages between said gate structures CGI, FG1; ...; CGn, FGn and said active regions 10, 20 and body contact 30 such that charge may be programmed, read, shifted, and erased from said gate structures CGI, FG1; ...; CGn, FGn. The voltage generation means 100 is connected to the respective contacts of the corresponding source, drain, bulk, and gate regions S, Gl, G2, ..., Gn-1, Gn, D, B. The associated functions will be described later.

The direction SD pointing from the source region 10 to the drain region 20 along the gate structures is called shifting direction. In this shifting direction SD, the intermediate cell gate structures are not flanked by a heavy source/drain doping like in normal EEPROM cells or MOS transistors - otherwise the charge isolating and conserving capability for the adjusted charge to be described later would vanish. However, to a certain limit, light source/ drain doping may be acceptable. The CC-EEPROM cell arrangement of Fig. 1 is arranged in a way, that charge can be shifted from one gate structure to another, i.e. CCD like. The cell arrangement contains a minimum of one non-volatile cell. Gate structures of this arrangement need not all to be non-volatile cells (f.e. there may be gates just for shifting, gates just supplying volatile memory or gates next to a heavy source or drain doping) or need not all to be used for non-volatile storing

.(j..e t2ιere_may _be_dummy-_ce Ls..o _;_ga-te.S-.nejχt- t.o_.a. heav_y_ source or drain doping) . The gate alignment needs not to have straight line characteristic, but meander, tree, parallel, ... structures are also possible.

The arrangement normally has a minimum of one contacted or uncontacted source/drain doping, which can act as a charge source or sink. This doping can be located on the beginning or end (edge) of the arrangement. There might be a bulk contact. Bulk can but needs not to be isolated from the substrate by any means (junction, oxide, insulator) . A minimum cell area is feasible due to the minimum number of drain and source contacts.

Doping is somehow a subject for trade off (see below) and can be done non-uniformly or differently under the tunnel oxide on the one hand and under the spacing between two gates of the other. However, also uniform doping is possible.

For shifting inversion charge from one gate structure to the other, the depletion regions, which are induced by these gates, must touch laterally. This is achieved at relatively low or medium voltages, when the effective doping between these gates is low. Thus, a low intrinsic bulk doping or a contra doping is preferred.

Programming voltage is shared by the inter poly oxide (between floating and control gate) , the tunnel oxide (both effects known from normal EEPROM cells) and an unwanted, extending_jdepletion _rs,gion..undex_the_c-@lJ-_._

In order to achieve the electrical field in the tunnel oxide, needed for Fowler Nordheim tunneling, at a minimum programming voltage, this depletion region can be limited by a heavy doping beneath the tunnel oxide, eventually spaced to the semiconductor surface.

Heavy doping is in contradiction to the need mentioned above regarding charge shifting. Therefore, the above mentioned trade-off should be found in practice. In any case, low doping is needed only at the surface.

Generation and recombination limit the available time after start of adjusting charge quantities to completion of reading or programming. The burried CCD approch known from R. H. Walden, R. H. Krambeck, R. J. Strain, J. McKenna, N. L. Schryer, G. E. Smith: The Buried Channel Charge Coupled Devices. The Bell System Technical Journal. American Telephone and Telegraph Company: New York, September 1972. Pages 1635-1640; and D. J. Burt : Basic Operation of the Charge Coupled Device. Proc. Int. Conf. Technol. Applic. CCD. Edinburgh University: Edinburgh 1974, Pages 1-12, which is used to cope with the high generation and recombination at the semiconductor/oxide interface, increases the read immunity and requires increased program voltage.

Fig. 2 shows the erase mode for a specific single gate structure CGI, FG1 of the CC-EEPROM cell arrangement.

In prder_ to _explain_, that__this example is compatible with normal non-volatile memory operation, here it is showed, how to erase one cell having control gate CGI and floating gate FG1 or all in parallel, applying appropriate bias and using the well known Fowler Nordheim tunneling.

Erasing is done by applying an electrical field to the tunnel oxide in the orientation, that majority charge carriers, here holes (+) , are accumulating on the semiconductor surface in an accumulation region AC. Thereby, electrons (-) stored in the floating gate FG1 may be extracted. Therefore, an erase voltage V_er is applied across a minimum of one CCD cell line bulk on the one hand and a minimum or one cell control gate on the other. This erase voltage V_er of typically 16-18 V physically adds to the source-bulk- voltage V_SB of typically > -0,7 V. It should be mentioned that here and in the following description all voltages are referred to the source voltage, however, this is just one of several possibilities. Erase is not self-limiting and cells behave differently, so one or more read verify plus program cycles may complete the erase step.

Next, programming of the CC-EEPROM cells will be explained. In known memory devices, programming was always performed with unlimited charge for a predetermined time period. However, according to this example programming can either be done with unlimited charge or with limited charge.

Particularly, programming with an unlimited charge source provides a random access possibilty.

Programming voltage and/or programming time adjust the amount of charge, which is tunneling from the inversion layer through the tunnel oxide to the floating gate (Fowler Nordheim tunneling) or is injected into the tunnel oxide (channel hot electron) .

Fig. 3 shows the channel hot electron programming mode for a specific gate structure of the CC-EEPROM cell arrangement.

This structure is operated somehow similar to a NAND CHE (channel hot electron) EEPROM. The source/drain doping in- between two cells is functionally substituted by supplying an appropriate V_seι to all cells, which should not be programmed, so that the gaps between cells have a continuous inversion layer INV. The cell having the gate structure FG3, CG3 to be programmed is supplied with a programming voltage V_pr which is smaller than V_seι, while V_seι is greater than V_DS. These voltages add to the source-bulk-voltage V_SB.

By supplying these voltages, a charge density CDE is cre- ated below the gate structure FG3, CG3. At the location where this charge density CDE is nearly zero, a channel hot electron region CHE is created from where hot electrons can enter into the floating gate FG3.

It should be noted that when using channel hot electron programming, it is also possible to use a SONOS gate structure leaving out the floating gate, as described in Boaz Eitan, Paolo Pavan, liar Bloom, Efraim Aloni, Aviv Frommer, David Finzi: NROM: A Novel Localized Trapping, 2-Bit Non- volatile Memory Cell. IEEE Electron Device Letters, Vol. 21, No. 11. IEEE: November 2000. Pages 543-545.

Fig. 4 shows the Fowler Nordheim programming mode for a specific gate structure of the CC-EEPROM cell arrangement with unlimited charge source.

An inversion layer INV is built up from the source 10 to the cell having the gate structure FG3, CG3 which should be programmed. This can be done by selecting and deselecting other cells in an appropriate manner or by another special gate structure, which is placed near by every cell (f.e. in the third dimension) .

Here, the select voltage V_seι is applied to the two left hand cells and a deselect voltage V_deSei is applied to the right hand neighbor cell. The cell having the gate structure FG3, CG3 to be programmed is supplied with a programming voltage V'_pr which is greater than V_pr in the case of channel hot electron programming. Fowler Nordheim program- ming mode has the advantage that it is current saving in comparison to channel hot electron programming, because no current flow exists between source and drain 10, 20.

Next,—programming wi-t-h a limited eha-rge will be explained. Programming with a limited charge source is done in three steps: adjusting charge quantity, shifting the charge to the cell to be programmed and finally programming, which means that this charge is tunneled to the floating area of the cell to be programmed.

Adjusting and shifting charge can be done in parallel, so that a huge fraction of the sector can be filled with this information carrying charge quantities, which can finally be programmed in parallel (burst programming) . In other words, having a two-dimensional array of CC EEPROM cells, first the information of all cells may be shifted under the array, and then all the information may be programmed in a single step. Because programming is time consuming (several milliseconds for Fowler Nordheim tunneling) , this parallel programming dramatically speeds up the memory filling with a continuous data stream (burst) .

There is no need for a special page buffer, which results in a smaller chip area due to the reduced logic in the bitline section. The programming of a cell ends automatically, when all charge beneath the tunnel oxide is tunneled to the floating gate. A self-limiting programming is achieved, supplying a multilevel ability, even in case of fast cells.

Fig. 5a, b show the adjust charge mode for programming a limited charge for a specific gate structure of the CC- EEPROM cell -arrangement .

Techniques for adjusting the charge quantity which will be programmed later on are well known from charge coupled devices (CCD filters) .

First, as illustrated in Fig. 5a a continuous inversion layer INV is built up from the source 10 to the adjusting gate structure CG2, FG2 by selecting the gate structure CGI, FG1 inbetween. Moreover, the right hand neighbor gate structure CG3, FG3 is deselected.

The amount of charge Q_Ipr is adjusted by the program adjust voltage V_prad which is linearly related by the following formula:

Q_Ipr = ^~ A ⁽C„ ' ' ⁽V_prad -V_FB ^~2 Φ_F) - pqε₀ε_SiN_Λ ⁽2 φ, + γ_SB ^{)) (}0⁾

which is valid in the case that the adjusting MOSFET does not have a floating gate. Here Φ_F is the Fermi potential, V_FB the flatband voltage, V_SB the source-bulk voltage, and the remaining terms are constants. If the adjusting MOSFET has a floating gate, then formula 11 below applies.

Then, with reference to Fig. 5b this adjusted charge is separated from the source 10 by deselecting the gate structure CGI, FG1 between the source 10 and the adjusting gate structure CG2, FG2.

Insjtead._of__adjusting .the charge quantity by the_V_Prad voltτ__ age, the desired charge amount could also be brought in via the source contact S (see Fig. 1) which would not be at a fixed potential in this case. The charge can also be delivered by a charge adjusting circuitry which is connected to the source contact.

The cell having the gate structure CGI, FG1 next to the source 10 is a dummy cell (no information storage is possible in limited charge programming mode) and in principle needs not to have a floating gate. The next cell, to which V_prad is applied, could also be a dedicated transistor.

Adjusting can be done in parallel to reading another word- line as explained later.

Fig. 6a-c show the charge shifting mode for shifting a limited charge for a specific gate structure of the CC-EEPROM cell arrangement. Charge shifting from one cell to another is well known and vastly documented for charge coupled devices (CCD camera, CCD filter) .

The easiest way to achieve this is to interconnect the control gate of every third cell. This results in only three wordlines, which must be driven in an appropriate manner. So, a corresponding wordline section needs less control logic__.and _lesis^driving_jιni_t^_,_-_res lt_ing_ in__a reduced chip area.

As shown in Fig. 6a, the starting situation is identical with the situation of Fig. 5b. Additionally shown is the gate structure having control gate CG4 and floating gate FG4 which is also deselected.

Having regard to Fig. 6b, the gate structure CG3, FG3 is then selected by applying selection voltage V_seι. As a consequence, inversion layer INV expands to the gate structure CG3, FG3.

Now, as shown in Fig. 6c, the gate structure CG2, FG2 is deselected by applying deselection voltage V_deseι- As a consequence, inversion layer INV contracts to the gate struc- ture CG3, FG3 which remains selected.

By the above process sequence, the limited charge quantity is shifted from one cell to the other. Fig. 7 shows the Fowler Nordheim programming mode for programming a limited charge for a specific gate structure of the CC-EEPROM cell arrangement.

Non-volatile programming is done by applying programming voltage V_pr to the control gates of cell having the gate structure CG3, FG3 which should be programmed, leaving the neighbor cells deselected.

The equation for the Fowler Nordheim tunneling current density according to Georg Tempel: Reprogrammable Silicon- based Non Volatile Memories. Infineon Technologies AG. CPD IPD RC IMEC: Leuven, Belgium 2001. Page 1-29, reads:

' FG "i

^tox (2 ) ^dtox

m α = (3) m * SπhΦ_b

with

h 6. 6 - 10^"34Js Planck ' s constant

Φ_b 3. 2eV energy barrier ( Si-Si0₂ ) at injecting interface q 1 . 6 - 10^"19C charge of single electron m 9 . 1 - 10^"31kg mass of free electron m* 0 . 42m effective mass of

( Si0₂ ) electron in band gap

and was originally derived under the assumption that the conduction band is filled with charge carriers .

However, when using the CCD principle for shifting charge beneath the floating gate in order to program, this charge is limited and steadily decreasing when charge carriers tunnel onto the floating gate during programming phase. Therefore it is assumed that the tunneling probability for each charge carrier is identical. This results in an approximately exponential tunneling current drop by time (neglecting electric field reduction due to charging of the floating gate) .

Thus, using the CCD principle, a single programming procedure will approximately take 3 times longer than usually as rule of thumb. However, using burst programming, there will be still an enormous time saving compared to conventional programming time.

The limited charge programming procedure may also be done in two steps, namely first program adjust beneath the cell to be programmed (like read adjust in Fig. 5) and secondly program the charge to the floating gate as mentioned above. Next, reading of the cells will be explained. There are two different possible reading modes, the NAND mode and the CCD mode.

The NAND mode reading provides a random access. The situation of reading in NAND mode is very similar to channel hot electron programming. Only the applied read voltage V_read is different.

Fig. 8 shows the NAND reading mode for a specific gate structure of the CC-EEPROM cell arrangement.

As a consequence of the applied voltages, namely V_seι to the cells not to be read and V_read to the cell to be read, there is a static current flow I_s which may be sensed by a sense amplifier SA.

In analogy with the CCD programming mode, the CCD reading mode consists of three operation procedures: adjusting read charge, shifting charge towards the output and sensing the charge. There is no static current consumption. As a consequence of the shifting procedure, there is only a burst reading without a random access possibility.

Here, the charge density CDE in the reading region RR depends on the information stored in the cell.

Fig. 9a, b show the adjust charge mode for reading a specific gate structure of the CC-EEPROM cell arrangement. Adjusting the reading charge is a preparation phase for the reading. It can be done in parallel to reading another wordline.

According to Fig. 9a, an inversion layer INV is built up from the source 10 to the cell having gate structure CG3, FG3 which is to be prepared. This can be done by selecting and deselecting other cells in an appropriate manner or by another special gate structure, which is placed near by every cell.

Here, the select voltage V_seι is applied to the two left hand cells and a deselect voltage V_dΘSei is applied to the right hand neighbor cell. The cell having the gate struc- ture FG3, CG3 to be prepared is supplied with a read adjust voltage V_readad such that the charge of the inversion layer INV under the cell is a function of the charge on the floating gate. V_seι is greater than V_readad_f so that the depletion region under the shifting cell is independent of the stored charge on the floating gate of other cells.

According to Fig. 9b, the inversion layer charge is finally separated from the continuous inversion layer INV to the source 10 by deselecting the neighbour gate having the gate structure CG2, FG2.

After adjusting the charge for reading, the charge must be shifted towards the output node by the shifting mode explained above with regard to Fig. 6. Fig. lOa-c show the charge sink and sense amplifier for a specific gate structure of the CC-EEPROM cell arrangement.

Sensing is done in parallel to the charge shifting. The sense amplifier SA is connected to the output node, which acts as a charge sink for the shifted charge. As the output node, either the drain 20 or the source 10 can be used. The cell next to the drain 10 is a dummy cell and needs not to have a floating gate (i.e. floating gate may be omitted or floating gate and control gate may be shorted) .

Sensing is well known and documented for charge coupled devices such as CCD camera, CCD filter etc.. These known sensing devices proved to be capable sensing at an 8 bit resolution, and facilitate deep multilevel sensing ability for CC-EEPROM cells according to this example.

According to Fig. 10a, the cell having gate structure CG2, FG2 is deselected, and the cells having gate structures CG3, FG3 and CG4, FG4 are selected. So, the charge to be read is shifted to the drain 20 from the gate structure FG3, CG3.

According to Fig. 10b, the cell having gate structure CG4, FG4 is selected, and the cells having gate structures CG2, FG2 and CG3, FG3 are deselected. So, the charge to be read is isolated at the drain 20 from the gate structure FG3, CG3. According to Fig. 10c, the cell having gate structure CG2, FG2 is selected, and the cells having gate structures CG3, FG3 and CG4, FG4 are deselected. So, new charge to be read coming from gate structure CGI, FGl (not shown in Fig. 10c) is transferred to the gate structure FG2, CG2.

Next, the read transfer characteristic will be evaluated.

Heretofore, the following physical quantities must be considered:

Ctox tunnel oxide capacitance o,abs absolute depletion region capacitance

C_sp inter poly capacitance

C_fr fringing capacitance Q_A ambient charge

Q_CG control gate charge

Q_D depletion region charge

Q_FG floating gate charge

Qi inversion layer charge V_A ambient voltage

V_CG control gate voltage

V_FG floating gate voltage

Vi inversion layer voltage

V_b bulk voltage

V_CG = V_adj_USt - V_FB + V_b + V_SB control gate potential

(where Vadj ust is the respective adj ust voltage )

V_FB = -kT/q ln (N_A N_{D/ CG}/ni²) flat band voltage Vi = 2 Φ_F + V_SB + V_b inversion layer potential

Φ_F = kT/q ln(N_A/nι) Fermi potential

In order to be neutral outside of the structure, the sum of all charges must be zero.

Q_FG + QCG + Q_A + Q_I + Q_D = 0 (5)

The equations for the oxide capacitances are

QCG = C_ip(VcG - V_FG) (6)

Q_A = C_fr(V_A - V_FG) (7)

Qi + QD = C_t0χ(Vι - VFG) (8)

Equation (8) is rewritten to be

The equation for the depletion region capacitance is

^Q° = ^~p<<lZ^£si^NSV V_b A_0X do⁾

where C_D,_abs denotes an absolute capacitance. Equations (6), (7), (9) and (10) inserted in equation (5) result in

C,

12 : c_tox + c_ip + c_fr

with

- γc_ip (v_adjust - v_FB - 2 Φ_F)

- γC_fr(V_A - 2 Φ_F - V_SB - V_b) (13)

This equation shows that the inversion layer charge is linear dependent of the floating gate charge. This clearly reveals the multilevel ability of of the CC-EEPROM cell arrangement .

A volatile memory functionality of unused memory sectors is achieved by the following steps: adjusting charge quantity, shifting this charge under the desired gate structure, storage phase, shifting the charge to the output node and finally sensing the charge. This storage mode has either a first in first out or a first in last out behaviour, namely dependent on what the output node is, i.e. source or drain. It can be used e.g. for storing the data to be programmed in another sector in order to realize a target programming algorithm.

Fig. 11 shows a possible two-dimensional top view of a CC- EEPROM cell arrangement. In Fig. 11, reference signs WL1-W5 denote five different wordlines arranged in parallel and equidistantly. S1-S4 and D1-D4 denote respective source and drain regions.

Between source SI and drain Dl, there are five gate structures each consisting of a floating gate and a control gate, the control gates being formed by the wordlines L1- WL5 at overlapping points Kll, K21, K31, K41, K51 with the floating gates.

Between source S2 and drain D2, there are five gate structures each consisting of a floating gate and a control gate, the control gates being formed by the wordlines WL1- WL5 at overlapping points K12, K22, K32, K42, K52 with the floating gates.

Between source S3 and drain D3, there are five gate structures each consisting of a floating gate and a control gate, the control gates being formed by the wordlines WL1- WL5 at overlapping points K13, K23, K33, K43, K53 with the floating gates.

Between source S4 and drain D4, there are five gate struc- tures each consisting of a floating gate and a control gate, the control gates being formed by the wordlines WL1- L5 at overlapping points K14, K24, K34, K44, K54 with the floating gates. Not shown in Fig. 11 for simplification are isolation structures between shifting channels.

By sequentially applying appropriate voltages to the word- lines WL1-WL5 and to the source and drain regions S1-S4 and D1-D4, information can be shifted in parallel along the shiftig direction SD under the gate structures of wordline WL2 and WL4 and simultaneouly be programmed with a single progamming burst. In analogy reading may be performed by shifting out the information in parallel along the shifting direction SD to the drains D1-D4.

Fig. 12a-j show a schematic cross-sectional illustration of processing steps for manufacturing the two-dimensional CC- EEPROM cell arrangement according to a first embodiment of the present invention in the wordline direction.

In Figure 12a reference sign 21 denotes a P-type silicon substrate, f. e. a silicon wafer substrate. Provided on said substrate 21 are a thermal pad oxide layer 25 and a pad nitride layer 28.

With reference to Figure 12b the pad nitride layer 28 and pad oxide layer 25 are structured into the form of a hard mask by a conventional photolithographic process. In a next process step said hard mask is used as a mask in an etching process for forming trenches 29 in said substrate 21. The etching process is for example an anisotropic plasma etching process. Thus, the structure shown in Figure 12b is ob- tained. In a next step, a thermal oxidation is performed to build up a trench oxide layer 102 in the interior of said trenches 29 in order to relax the silicon stress after the trench etch. This results to the structure shown in Figure 12c.

It should be noted that the trenches 29 in said substrate 21 run in parallel in a first direction (y in Figure 14) and define a plurality of strip regions (220 a-f in Figure 14) of said substrate 21 lying between each pair of adjacent trenches 29. The width of the trenches 29 and the width of the intervening strip regions can be equal and amount to the minimum design width F of the used process.

In a next process step, as illustrated in Figure 12d, a CVD oxide layer 215 is deposited over the resulting structure (CVD = Chemical Vapour Deposition) and the surface is pla- narised by means of a CMP process (CMP = Chemical Mechani- cal Polishing) using the pad nitride layer 28 as stopping layer.

Thereafter, as shown in Figure 12e said pad nitride layer 28 is removed by means of an appropriate wet etch process.

Next, a first implantation step II is performed, using said pad oxide layer 25 as a scattering layer. This first implantation step II is a p-type implantation to enhance the doping concentration of said substrate 21 in a surface re- gion 220 of said strip regions (220 a-f in Figure 14) be- tween said trenches 29 filled with said isolation oxide 215.

Next, a second implantation step 12 is performed with n- type ions. The second implantation step 12 provides a buried region 225 in said substrate 21, the depths of which approximately equals to or is less than the depths of said trenches 29, as also illustrated in Figure 12f, forming an insulated region 301.

These implantation steps II, 12 are optional and only used in the case that it is mandatory to isolate the shifting area from the substrate in order to obtain very limited shifting areas.

In a next step, as illustrated in Figure 12g, also the pad oxide layer 25 is removed by a wet etch step.

Figure 12h illustrates that a tunnel oxide layer 230 is grown on the strip regions 220 in order to form the tunnel oxide of gate structures to be built up between the field isolation trenches 29.

In a next process step, a first conductive polysilicon layer 240 is deposited on the resulting structure which serves as floating gate polysilicon layer.

In a subsequent process step, said first polysilicon layer 240 is partly removed by means of a chemical mechanical polishing step using the trench isolation 215 as stopping layer or using a combination between process time and chemical stop as stopping layer. Anyhow, the STI height can be calibrated to adjust this step. This results to the structure shown in Figure 12i.

According to Figure 12j, an insulation structure 250 in form of an ONO layer (ONO = Oxide-Nitride-Oxide) and thereafter a second conductive polysilicon layer 260 are deposited over the resulting structure. Then, a not shown mask is formed on the resulting structure, and the layers 230, 240, 250, 260 are patterned to form strips STI, ST2, ST3 running in parallel to a second direction (x in Figure 14) which perpendicularly crosses said strip regions 220 and accordingly said isolated trench regions 215.

Fig. 13 shows a schematic illustration corresponding to the process status of Fig. 12j perpendicular to the wordline direction.

Figure 13 illustrates the result of said etching steps.

Thus, gate structures comprising a tunnel oxide, floating gate, and isolation structure having worldlines on top in form of strips are obtained, where is clear that region 301 (p silicon) is insulated from the substrate 21 by the n- type layer 225 and is adjacent to two parallel STI trenches 215.

Fig. 14 shows top view of a two-dimensional CC-EEPROM cell arrangement according to the first embodiment of the pres- ent invention. In the top view of Figure 14, the widths of the trench isolation regions 220 a-f and the distance of the wordlines WL1'-WL9' has been depicted with doubled width in order to enhance clarity. This leads to a cell size of 9 F², as shown in cell Z in Fig. 14.

Of course, the said gate structures 230, 240, 250, said wordlines WL1'-WL9' and the space therebetween, and said trenches 29 may have minimum design width F which enables forming a minimum cell dimension of 4F².

As may be further obtained from Figure 14, a plurality of active regions SI'- S6' of the n⁺-type is provided at the end of a corresponding strip 220 a-f and is electrical connectable to the gate structures of the corresponding strip by means of an intervening control gate line CLl, CL2. Said control gate lines CLl, CL2 are formed as normal MOSFET- gates, and not as gates including a floating gate. Said ac- tive regions Sl'-S6' are arranged at different ends of neighbouring strips 220 a-f and connected to wiring lines LSl'-LSβ¹. This arrangement also helps to realize the connection.

Moreover, every third wordline of the wordlines denoted as WL1'-WL9' is connected to a common wiring line L147, L369, L258, respectively. This connection scheme for the wordlines which are made of the second polysilicon layer 260 in Figure 12a-j and 13 is in accordance with the shifting scheme for operation of said semiconductor memory device as explained above.

It should be noted that the crosses in Figure 14 denote contact holes for connecting the wirings to the respective semiconductor regions. Not shown in Fig. 14 are p⁺-type bulk contacts at the end of the strips for electrically connecting said regions 301.

Fig. 15a, b show a schematic cross-sectional illustration of processing steps for manufacturing the two-dimensional CC- EEPROM cell arrangement according to a second embodiment of the present invention in the wordline direction.

According to the second embodiment shown in Figure 15, the chemical mechanical polishing step shown in Figure 12i is replaced by a photolithographic patterning step resulting in the structure shown in Figure 15a. This photolithographic patterning step provides an overlay of the floating gate regions 240' over the isolating regions 215, i.e. a floating gate having a larger width.

The following process steps as illustrated in Figure 15b including the deposition of the ONO isolation structure 250' and the deposition of the second polysilicon layer

260' and thereafter the not illustrated patterning step of the gate structures are the same as in the first embodiment explained above. It should be noted that the process flow according to the second embodiment increases the minimum achievable cell size, namely to 6F². However, it exhibits the advantage of a simple process flow and the advantage that the area of the junction between the wordline 260' and the ONO isolation structure 250' is larger than the area between the floating gate 240' and the tunnel oxide. The latter results in electrical advantages during operation of said semiconductor memory device.

Fig. 16a-c show a schematic cross-sectional illustration of processing steps for manufacturing the two-dimensional CC- EEPROM cell arrangement according to a third embodiment of the present invention in the wordline direction.

According to the third embodiment illustrated in Figure 16 a-c, the process is modified after the CMP step used to form the floating gate regions of the first polysilicon layer 240. Namely, a third polysilicon layer 270 is depos- ited over the resulting structure of Figure 12i, as illustrated in Figure 16a. Said third polysilicon layer 270 is patterned for forming an extension of said floating gate regions of said first polysilicon layer, as illustrated in Figure 16b.

Here it should be noted that due to the presence of the isolation regions 215, a certain offset of the photomask of said process for patterning said third polysilicon layer 270 is not detrimental to the manufacture process. In a next process step, the ONO isolation structure 250'' and the second polysilicon layer 260'' for forming the worldlines WL1'-WL9' are deposited and structures as explained above. The third embodiment exhibits the above men- tioned electrical advantage of the second embodiment and furthermore the advantage that cell dimensions as small as 4F² may be obtained.

In order to prove the most critical aspects to work - charge transfer, charge isolation and applying programming voltage - a device simulation was done. This simulation showed that it is possible to build up such a structure, which can shift charge, isolate it and apply a programming voltage while the quantity of isolated charge is only hardly altered by leakage current and thermal generation.

Although the present invention has been described with regard to specific embodiments, it is not limited thereto, but may be modified in many ways.

Particularly, CC-EEPROM cells or arrangements can also be mixed with other, well known EEPROM cells or cell elements in order to bring in their functionality.

Just for generality, it is possible to add some more gates or doping profiles to the arrangement mentioned above, which are added perpendicular to (or better: not in the same direction of) the shifting direction SD. These means can provide additional functionality. The floating gates of a CC-EEPROM cell can be routed out of the cell shifting area and can be connected to other structures (gate, flanked doping, transistor, tunnel oxide, ... ) , in order to provide additional functionality or to combine known NVM (non-volatile memory) principles (channel hot electron, Fowler Nordheim tunneling, reading via MOS- FET, ...) or charge shifting principles (CCD) with the CC- EEPROM cell principle. So, a minimum of one CCD principle is used in order to erase, program, read non-volatile mem- ory.

REFERENCE SIGNS

Claims

1. A semiconductor memory device comprising:

a semiconductor substrate (21) having a first conductivity (p) type;

a plurality of trenches (29) provided in said substrate (21) running in parallel in a first direction (y) , said trenches being filled with an isolation material (215; 215a-e) ;

said trenches (29) defining a plurality of strip regions (220a-f, 301) of said substrate (21) lying between each pair of adjacent trenches (29) ;

a plurality of gate structures (230, 240, 250; 230, 240', 250'; 230, 240, 270, 250") for storing charge in a nonvolatile manner arranged above the surface of the semicon- ductor substrate (21) and electrically isolated therefrom;

said plurality of gate structures (230, 240, 250; 230, 240', 250'; 230, 240, 270, 250") being arranged in strips (ST1-3) running in parallel in a second direction (x) and crossing said strip regions (220a-f, 301) ;

a plurality of wordlines (WL1' -WL9' ; 260, 260', 260"), a respective one being arranged on each of said gate structures (230, 240, 250; 230, 240', 250'; 230, 240, 270, 250"); and a plurality of active regions (Sl'-S6') of the second conductivity (n⁺) type, each of said active regions (Sl'-S6') being arranged at one end of a corresponding strip (220a-f, 301) and being electrically connectable to the gate structures (230, 240, 250; 230, 240', 250'; 230, 240, 270, 250") of said corresponding strip (220a-f, 301).

2. The semiconductor memory device according to claim 1, wherein said gate structures (230, 240, 250; 230, 240',

250'; 230, 240, 270, 250") include a stack of a tunnel oxide (230), a floating gate (240; 240'; 240, 270), and an isolation structure (250, 250', 250").

3. The semiconductor memory device according to claim 1 or 2, wherein said active regions (Sl'-S6') are arranged at different ends of neighboring strips (220a-f, 301) .

4. The semiconductor memory device according to one of the preceding claims, wherein said active regions (Sl'-S6') are electrically connectable to the gate structures (230, 240, 250; 230, 240', 250'; 230, 240, 270, 250") of said corresponding strip (220a-f, 301) by means of a respective control gate structure (CLl, CL2) .

5. The semiconductor memory device according to claim 4, wherein said respective control gate structure (CLl, CL2) runs in parallel with the respective outermost gate structures (230, 240, 250; 230, 240', 250'; 230, 240, 270, 250") at the corresponding end.

6. The semiconductor memory device according to one of the preceding, wherein every third of said wordlines (WL1'- WL9' ) is connected to a common wiring line (L147, L369, L258).

7. The semiconductor memory device according to one of the preceding claims, wherein said second and first directions

(x, y) are perpendicular to each other.

8. The semiconductor memory device according to one of the preceding claims, wherein the doping concentration of the substrate (21) is varied in a surface region (220) of the strip regions (220a-f, 301) .

9. The semiconductor memory device according to one of the preceding claims, wherein a region (225) of the second conductivity type (n) is buried in the substrate (21) along the strip regions (220a-f, 301) .

10. The semiconductor memory device according to one of the preceding claims, wherein said gate structures (230, 240, 250; 230, 240', 250'; 230, 240, 270, 250"), said wordlines (WL1'-WL9') and said trenches (29) have minimum design width F forming a cell dimension of 4F².

11. A method for manufacturing a semiconductor memory device, comprising the steps of: providing a semiconductor substrate (21) having a first conductivity (p) type;

providing a plurality of trenches (29) in said substrate (21) running in parallel in a first direction (y) , said trenches (29) defining a plurality of strip regions (220a- f, 301) of said substrate (21) lying between each pair of adjacent trenches (29) ;

filling said trenches (29) with an isolation material (215; 215a-e) ;

providing a plurality of gate structures (230, 240, 250; 230, 240', 250'; 230, 240, 270, 250") for storing charge in a non-volatile manner above the surface of the semiconductor substrate (21) and electrically isolated therefrom, said plurality of gate structures (230, 240, 250; 230, 240', 250'; 230, 240, 270, 250") being arranged in strips (STl-3) running in parallel in a second direction (x) and crossing said strip regions (220a-f, 301) ;

providing a plurality of wordlines (WL1'-WL9'; 260, 260', 260"), a respective one being arranged on each of said gate structures (230, 240, 250; 230, 240', 250'; 230, 240, 270, 250"); and

providing a plurality of active regions (Sl'-S6') of the second conductivity (n⁺) type, each of said active regions (Sl'-S6') being arranged at one end of a corresponding strip (220a-f, 301) and being electrically connectable to the gate structures (230, 240, 250; 230, 240', 250'; 230, 240, 270, 250") of said corresponding strip (220a-f, 301).

12. The method according to claim 11, comprising the steps of providing said trenches (29) by means of an etching process using a hard mask (25, 28), providing an oxide layer (102) on the inner surface of said trenches (29) ; depositing a layer of said isolation material (215) on the resulting structure; planarizing said layer of said isolation ma- terial (215) by a chemical-mechanical polishing process such that it levels with said hard mask (25, 28) .

13. The method according to claim 12, further comprising the steps of removing said hard mask (25, 28), providing a tunnel oxide layer (230) and a first polysilicon layer

(240) over the resulting structure, and planarizing said first polysilicon layer (240) by a chemical-mechanical polishing process such that it levels with said isolation material (215) for forming a floating gate region.

14. The method according to claim 13, further comprising the steps of providing a third polysilicon layer (270) over the resulting structure, and patterning said third polysilicon layer (240) for forming an extension of said float- ing gate region.

15. The method according to claim 14, further comprising the steps of providing an isolation layer having contact holes between the first and third polysilicon layer (240, 270) , said contact holes being arranged for providing an electrical connection between said first and third polysilicon layer (240, 270) .

16. The method according to claim 12, further comprising the steps of removing said hard mask (25, 28), providing a tunnel oxide layer (230) and a first polysilicon layer (240') over the resulting structure, and patterning said first polysilicon layer (240) for forming a floating gate region which partly overlaps said isolation material (215) in said trenches (29) .

17. The method according to claim 13, 14 or 15, further comprising the steps of providing an isolation layer (250, 250', 250") and a second polysilicon layer (260, 260', 260'') for forming a control gate region over the resulting structure; and forming said plurality of gate structures (230, 240, 250; 230, 240', 250'; 230, 240, 270, 250") by patterning said tunnel oxide layer (230) , first polysilicon layer (240, 240'), isolation layer (250, 250', 250") and second polysilicon layer (260, 260', 260").

18. The method according to one of claims 11 to 17, further comprising at least one of the steps of enhancing the doping concentration of the substrate (21) in a surface region (220) of the strip regions (220a-f, 301) by means of a first implantation step (II) and burying a region (225) of the second conductivity type (n) in the substrate (21) along the strip regions (220a-f, 301) by means of a second implantation step (12) .