WO2003032492A3 - A reconfigurable integrated circuit with a scalable architecture - Google Patents

A reconfigurable integrated circuit with a scalable architecture Download PDF

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Publication number
WO2003032492A3
WO2003032492A3 PCT/EP2002/011075 EP0211075W WO03032492A3 WO 2003032492 A3 WO2003032492 A3 WO 2003032492A3 EP 0211075 W EP0211075 W EP 0211075W WO 03032492 A3 WO03032492 A3 WO 03032492A3
Authority
WO
WIPO (PCT)
Prior art keywords
crossbar
integrated circuit
fbs
subset
crossbar devices
Prior art date
Application number
PCT/EP2002/011075
Other languages
French (fr)
Other versions
WO2003032492A2 (en
Inventor
Frederic Reblewski
Olivier Lepape
Original Assignee
M2000
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by M2000 filed Critical M2000
Priority to CA002461540A priority Critical patent/CA2461540C/en
Priority to AU2002347046A priority patent/AU2002347046A1/en
Priority to JP2003535333A priority patent/JP4191602B2/en
Priority to EP02782816.9A priority patent/EP1433257B1/en
Publication of WO2003032492A2 publication Critical patent/WO2003032492A2/en
Publication of WO2003032492A3 publication Critical patent/WO2003032492A3/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/64—Distributing or queueing
    • H04Q3/68—Grouping or interlacing selector groups or stages
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/1302—Relay switches
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/1304—Coordinate switches, crossbar, 4/2 with relays, coupling field
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13109—Initializing, personal profile
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13322—Integrated circuits

Abstract

An integrated circuit (IC) includes a number of function blocks (FB), of which at least one is re-configurable. Each of the FBs may be a reconfigurable function or a non-reconfigurable function or recursively expanded with additional 'nested' function blocks. The IC further includes a number of input pins, a number of output pins, and a number of crossbar devices. The elements, at least at the IC level, are coupled in a manner such that all input signals are provided to the FBs through a first subset of the crossbar devices, all internal signals are routed from one FB to another FB through a second subset of crossbar devices, and all output signals are routed from the FBs to the output pins through a third subset of crossbar devices. To increase routability and speed each of the crossbar device output has a single fanout. Additionally, each of the crossbar devices may provide only one input to each other crossbar device.
PCT/EP2002/011075 2001-10-04 2002-10-02 A reconfigurable integrated circuit with a scalable architecture WO2003032492A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CA002461540A CA2461540C (en) 2001-10-04 2002-10-02 A reconfigurable integrated circuit with a scalable architecture
AU2002347046A AU2002347046A1 (en) 2001-10-04 2002-10-02 A reconfigurable integrated circuit with a scalable architecture
JP2003535333A JP4191602B2 (en) 2001-10-04 2002-10-02 Reconfigurable integrated circuit with scalable architecture
EP02782816.9A EP1433257B1 (en) 2001-10-04 2002-10-02 A reconfigurable integrated circuit with a scalable architecture

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/971,349 US6594810B1 (en) 2001-10-04 2001-10-04 Reconfigurable integrated circuit with a scalable architecture
US09/971,349 2001-10-04

Publications (2)

Publication Number Publication Date
WO2003032492A2 WO2003032492A2 (en) 2003-04-17
WO2003032492A3 true WO2003032492A3 (en) 2004-02-26

Family

ID=25518256

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2002/011075 WO2003032492A2 (en) 2001-10-04 2002-10-02 A reconfigurable integrated circuit with a scalable architecture

Country Status (6)

Country Link
US (1) US6594810B1 (en)
EP (1) EP1433257B1 (en)
JP (1) JP4191602B2 (en)
AU (1) AU2002347046A1 (en)
CA (1) CA2461540C (en)
WO (1) WO2003032492A2 (en)

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US6978186B2 (en) * 2002-03-22 2005-12-20 International Rectifier Corporation Modular functional block for an electronic control system
US6975139B2 (en) * 2004-03-30 2005-12-13 Advantage Logic, Inc. Scalable non-blocking switching network for programmable logic
US7698118B2 (en) * 2004-04-15 2010-04-13 Mentor Graphics Corporation Logic design modeling and interconnection
US7460529B2 (en) * 2004-07-29 2008-12-02 Advantage Logic, Inc. Interconnection fabric using switching networks in hierarchy
US7224184B1 (en) * 2004-11-05 2007-05-29 Xilinx, Inc. High bandwidth reconfigurable on-chip network for reconfigurable systems
US7263456B2 (en) * 2006-01-10 2007-08-28 M2000 On circuit finalization of configuration data in a reconfigurable circuit
US7274215B2 (en) * 2006-01-17 2007-09-25 M2000 Sa. Reconfigurable integrated circuits with scalable architecture including one or more adders
US7768301B2 (en) * 2006-01-17 2010-08-03 Abound Logic, S.A.S. Reconfigurable integrated circuits with scalable architecture including a plurality of special function elements
US7368943B2 (en) * 2006-03-28 2008-05-06 Advantage Logic, Inc. Enhanced scheme to implement an interconnection fabric using switching networks in hierarchy
US7739647B2 (en) * 2006-09-12 2010-06-15 Infosys Technologies Ltd. Methods and system for configurable domain specific abstract core
US7714611B1 (en) * 2008-12-03 2010-05-11 Advantage Logic, Inc. Permutable switching network with enhanced multicasting signals routing for interconnection fabric
US7705629B1 (en) * 2008-12-03 2010-04-27 Advantage Logic, Inc. Permutable switching network with enhanced interconnectivity for multicasting signals
US7999570B2 (en) * 2009-06-24 2011-08-16 Advantage Logic, Inc. Enhanced permutable switching network with multicasting signals for interconnection fabric
US8341580B2 (en) * 2009-09-28 2012-12-25 Advantage Logic, Inc. Modular routing fabric using switching networks
JP2017169118A (en) 2016-03-17 2017-09-21 株式会社東芝 Integrated circuit and electronic equipment

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Also Published As

Publication number Publication date
EP1433257B1 (en) 2013-09-11
JP2005505978A (en) 2005-02-24
JP4191602B2 (en) 2008-12-03
CA2461540C (en) 2005-08-30
CA2461540A1 (en) 2003-04-17
EP1433257A2 (en) 2004-06-30
WO2003032492A2 (en) 2003-04-17
AU2002347046A1 (en) 2003-04-22
US6594810B1 (en) 2003-07-15

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