WO2003034494A1 - Module component - Google Patents
Module component Download PDFInfo
- Publication number
- WO2003034494A1 WO2003034494A1 PCT/JP2002/010591 JP0210591W WO03034494A1 WO 2003034494 A1 WO2003034494 A1 WO 2003034494A1 JP 0210591 W JP0210591 W JP 0210591W WO 03034494 A1 WO03034494 A1 WO 03034494A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- coil
- pattern
- module
- wiring circuit
- insulating resin
- Prior art date
Links
- 229920005989 resin Polymers 0.000 claims abstract description 36
- 239000011347 resin Substances 0.000 claims abstract description 36
- 239000004020 conductor Substances 0.000 claims abstract description 24
- 239000000696 magnetic material Substances 0.000 claims abstract description 6
- 239000003990 capacitor Substances 0.000 claims description 19
- 229910052802 copper Inorganic materials 0.000 claims description 8
- 239000003985 ceramic capacitor Substances 0.000 claims description 4
- 229910052709 silver Inorganic materials 0.000 claims description 4
- 238000009413 insulation Methods 0.000 abstract description 8
- 239000000758 substrate Substances 0.000 description 39
- 239000010410 layer Substances 0.000 description 22
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 14
- 239000004065 semiconductor Substances 0.000 description 11
- 239000011889 copper foil Substances 0.000 description 9
- 229910000679 solder Inorganic materials 0.000 description 9
- 239000010949 copper Substances 0.000 description 8
- 238000000034 method Methods 0.000 description 7
- 239000003822 epoxy resin Substances 0.000 description 6
- 229920000647 polyepoxide Polymers 0.000 description 6
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000003475 lamination Methods 0.000 description 4
- 229910000859 α-Fe Inorganic materials 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 239000002344 surface layer Substances 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910002092 carbon dioxide Inorganic materials 0.000 description 2
- 239000001569 carbon dioxide Substances 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 230000004907 flux Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000011256 inorganic filler Substances 0.000 description 2
- 229910003475 inorganic filler Inorganic materials 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000004804 winding Methods 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 239000004698 Polyethylene Substances 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 150000001879 copper Chemical class 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000007606 doctor blade method Methods 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000004898 kneading Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000035699 permeability Effects 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- -1 polyethylene Polymers 0.000 description 1
- 229920000573 polyethylene Polymers 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
- G06K19/07773—Antenna details
- G06K19/07777—Antenna details the antenna being of the inductive type
- G06K19/07779—Antenna details the antenna being of the inductive type the inductive antenna being a coil
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
- G06K19/07773—Antenna details
- G06K19/07777—Antenna details the antenna being of the inductive type
- G06K19/07779—Antenna details the antenna being of the inductive type the inductive antenna being a coil
- G06K19/07783—Antenna details the antenna being of the inductive type the inductive antenna being a coil the coil being planar
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
- G06K19/07773—Antenna details
- G06K19/07777—Antenna details the antenna being of the inductive type
- G06K19/07784—Antenna details the antenna being of the inductive type the inductive antenna consisting of a plurality of coils stacked on top of one another
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F17/00—Fixed inductances of the signal type
- H01F17/0006—Printed inductances
- H01F17/0013—Printed inductances with stacked layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5388—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates for flat cards, e.g. credit cards
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/645—Inductive arrangements
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
- H05K1/165—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed inductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F17/00—Fixed inductances of the signal type
- H01F17/0006—Printed inductances
- H01F17/0013—Printed inductances with stacked layers
- H01F2017/0026—Multilayer LC-filter
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/40—Structural association with built-in electric component, e.g. fuse
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05541—Structure
- H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/2401—Structure
- H01L2224/2402—Laminated, e.g. MCM-L type
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/08—Magnetic details
- H05K2201/083—Magnetic materials
- H05K2201/086—Magnetic materials for inductive purposes, e.g. printed inductor with ferrite core
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10227—Other objects, e.g. metallic pieces
- H05K2201/10416—Metallic blocks or heatsinks completely inserted in a PCB
Definitions
- the present invention relates to a module with a built-in circuit component, and more particularly to, for example, a module component with a multilayer wiring board having a circuit component built in an insulating substrate.
- a build-up method for forming a multilayered board is known.
- a photosensitive resin is applied to the surface of a core substrate made of a double-sided copper-clad glass epoxy or the like on which wiring is formed by means such as etching of a copper foil, exposure and development are performed, and insulation having a through hole is provided.
- a layer is formed.
- electroless copper plating is applied to the surface, and resist coating, etching, and resist removal are sequentially performed on the surface.
- a through-hole conductor and a wiring circuit layer are formed, and a plating layer is formed in the through-hole, and the wiring circuit layers between the layers are connected.
- a coil is a module component formed by a coil pattern made of a conductor on an insulating resin layer, and the coil pattern is sandwiched between magnetic materials provided on the insulating resin layer above and below.
- FIG. 1 is a cross-sectional view illustrating a configuration of a module component according to an embodiment of the present invention.
- FIG. 2A is a front view of the electrically insulating substrate 3 in FIG.
- FIG. 2B is a sectional view taken along the line AA ′ of FIG. 2A.
- FIG. 2C is a rear view of the electrically insulating substrate 3 in FIG.
- FIG. 3A is a front view of the electrically insulating substrate 5 in FIG.
- FIG. 3B is a cross-sectional view taken along the line BB ′ of FIG. 3A.
- FIG. 3C is a back view of the electrically insulating substrate 5 in FIG.
- FIG. 4 is an exploded perspective view of the module component in FIG. BEST MODE FOR CARRYING OUT THE INVENTION
- FIG. 1 is a cross-sectional view illustrating a configuration of a module component according to the present embodiment.
- the electrically insulating substrates 1 to 7 are formed by laminating a plurality of layers of an insulating resin such as an epoxy resin mixed with an inorganic filler. That is, a laminated body is formed by laminating a plurality of insulating resin layers.
- an insulating resin such as an epoxy resin mixed with an inorganic filler.
- the semiconductor bare chip 8 is an active component such as an IC or an LSI, and is formed of a conductor containing copper (hereinafter, also referred to as Cu) or silver (hereinafter, also referred to as Ag) formed on the insulating substrate 3. Is electrically connected to the wiring circuit pattern 1 A via the solder bump 21.
- An underfill resin 22 made of an insulating resin such as an epoxy resin is injected and hardened into a gap between the semiconductor bare chip 8 and the electric insulating substrate 3.
- the chip component 9 is a passive component including a resistor, a capacitor, an inductor, and the like, and is electrically connected to a wiring circuit pattern 15 D formed on the electrically insulating substrate 5 by a solder 24. Further, an underfill resin 22 is injected and hardened in the gap between the chip component 9 and the electrically insulating substrate 5.
- the large-capacity capacitor 10 is mounted on the electrically insulating substrate 1. Assuming that this module functions, for example, as a DCZDC converter, which is a device that converts DC power to DC power of a different voltage, a large-capacity capacitor 10 is used to stabilize voltage fluctuations. It is.
- An electric insulating resin 16 made of an epoxy resin or a phenol resin covers the large-capacity capacitor 10. As the large capacity capacitor 10, a sheet capacitor / ceramic capacitor is used.
- the external connection electrode 25 is formed on the electrically insulating substrate 7 for external connection as a module component.
- Each of the electrically insulating substrates 1 to 7 is electrically connected via a via-hole conductor 27.
- Via-hole conductor 1 2, 14, 18, and 27 form connection conductors for electrically connecting circuits.
- the coil portion 26 includes spiral coil patterns 11A to 11D formed on both surfaces of the electrically insulating substrates 3 and 5, and an adhesive 20 such as epoxy or silicon on one surface of the electrically insulating substrates 2 and 6. It is composed of magnetic materials 13A and 13B made of ferrite which sandwich the spiral coil pins 11A to 11D.
- the coil part 26 of the module component configured as described above will be specifically described with reference to FIGS. 1, 2A, 2B, 2C, 3A, 3B, and 3C. I do.
- FIG. 2A is a front view of the electrically insulating substrate 3
- FIG. 2B is a cross-sectional view of the electrically insulating substrate 3 taken along the line A—A ′
- FIG. 2C is a rear view of the electrically insulating substrate 3
- FIG. 3B is a cross-sectional view taken along line BB ′ of the electrically insulating substrate 5, and FIG.
- spiral coil patterns 11A to 11D are made of a conductor containing Cu or Ag, and are formed on both surfaces of electrically insulating substrates 3 and 5, respectively.
- Electrodes 17A to 17G are formed at the ends of the spiral coil patterns 11A to 11D to electrically connect the individual spiral coil patterns 11A to 11D.
- Electrode 17A and electrode 17C, electrode 1'7D and electrode 17E, and electrodes 17F and 17G are connected to via-hole conductors 12 provided on electrically insulating substrates 3, 4, and 5, respectively. , 14 and .18, one coil is formed by these four spiral coil patterns.
- spiral coil patterns 11A to 11D are formed on a plurality of electrically insulating substrates, and each end thereof is connected with a via-hole conductor. Thereby, a coil portion having a larger magnetic flux can be formed.
- these spiral coil patterns 11A to 11D are sandwiched between magnetic materials 13A and 13B made of ferrite or the like to increase the magnetic permeability and secure a predetermined inductance value. Can be.
- a predetermined circuit is configured by mounting coil components, active components, passive components, etc. with a large external shape and mounting area on a limited circuit board area, conventionally, miniaturization has been required to connect the components to the surface layer of the board. difficult.
- wiring connection cannot be made only by wiring wiring on the surface layer, wiring connection was made possible by using a multilayered substrate. However, as a result, the wiring length becomes longer and parasitic capacitance, resistance and inductance are generated, and it has been difficult to secure required circuit characteristics.
- a coil pattern is formed on a part of a wiring circuit pattern on which an active component and a passive component provided on a plurality of insulating resin layers are mounted, and these are laminated to electrically connect each insulating resin layer. Connecting ⁇ Form a coil component in the laminate. In this way, miniaturization is possible. Furthermore, by configuring a coil pattern as a part of the wiring pattern, the wiring length with active components and passive components can be minimized, eliminating parasitic capacitance and resistance inductance that have impeded circuit characteristics and achieving high density. Therefore, high-performance module parts can be realized.
- a paste-like mixture obtained by kneading an epoxy resin, filler (a powder of 3i02 from 0.1 m to 100/111) and a hardening agent is mixed with a 75-m-thick polyethylene blade by a doctor blade method. After a predetermined thickness is coated on the telephoto film, it is dried and an uncured (B stage) 80 m thick insulating sheet is formed. After that, it is cut to a predetermined size and a via hole is formed using a carbon dioxide laser. A through hole (0.15 mm in diameter) for connection is formed.
- the through holes may be formed by using various lasers such as a YAG laser or an excimer laser or a puncher in addition to the carbon dioxide laser.
- the through-holes are filled with a conductive resin paste by a screen printing method, and via-hole conductors 12, 14, and 18 are formed.
- a copper foil of 70 m is used as a carrier-transferred copper foil, and a copper foil of 9 m is formed on one side of the carrier via a release layer mainly composed of chromium (hereinafter, referred to as Cr). You. At that time, the surface of the 9 / m copper foil opposite to the release layer was roughened. Spiral coil patterns 11A, 11B, 11C by etching 9 copper foils of this copper carrier transfer copper foil (trade name: Furukawa Electric epipable copper foil) by photolithography process and etching process , 11 D and wiring circuit patterns 15 A, 15 B, 15 C are formed.
- both surfaces Pas evening one emission surface of the copper Kiyari ⁇ transfer copper foil formed on the wiring circuit pattern of the insulating sheet positioning heat press by the press temperature 1 2 0 ° C, a pressure l O k gZcm 2 For 5 minutes. Since the press temperature is lower than the curing temperature, the thermosetting resin in the insulation sheet softens and the wiring circuit pattern is embedded in the insulation sheet, and then the copper carrier is peeled off from the insulation sheet to provide electrical insulation. Substrates 1 to 7 are formed.
- predetermined circuit components are mounted on the individual wiring circuit patterns 15A to 15C of the electric insulating substrates 1 to 7, and electrical connection is performed.
- solder bump mounting which is one of the bare chip mounting
- the electrode coordinates on the semiconductor bare chip 8 and the corresponding coordinates of the wiring circuit pattern 15 A on the electrically insulating substrate 3 are aligned by optical and electrical system image processing, and the semiconductor bare chip 8 is placed on the electrically insulating substrate 3. And pressurized and heated for electrical connection.
- an underfill resin 22 made of an epoxy resin is injected into the gap between the semiconductor bare chip 8 and the electric insulating substrate 3 and is cured.
- an epoxy resin is mixed with an appropriate amount of an inorganic filler such as silica to reduce the stress generated due to the difference in the coefficient of thermal expansion between the semiconductor bare chip 8 and the electrically insulating substrate 3. Be improved.
- the bare chip mounting is not limited to the solder bumps 21, but may be ACF mounting using an anisotropic conductive resin sheet.
- anisotropic conductive resin is placed on the wiring circuit pattern 15A, gold bumps are formed on the electrodes of the semiconductor bare chip 8 instead of the solder bumps 21, and electrical connection is made by heating under pressure. Yes, there is no need to inject the underfill resin 22 into the gap between the semiconductor base chip 8 and the electrically insulating substrate 3 for solder bump connection.
- the chip component mounting is not limited to the solder mounting using the solder paste, and the electrical connection may be performed using a conductive adhesive.
- the individual electric insulating substrates 1 to 7 are superimposed as shown in Fig. 1, and the heating temperature is increased to 1 75 Heated and pressurized at 150 ° C., 150 kg Z cm 2 for 120 minutes. Then, the insulating sheet and the conductive paste are hardened, and the wiring circuit pattern and the insulating sheet are mechanically and firmly connected. At the same time, the via-hole conductors 12, 14, 18 embedded with the conductive resin paste and the wiring circuit patterns 15 A, 15 B, 15 C are electrically connected to form a laminated body.
- through holes 28 corresponding to the projected areas of the individual components are formed in the electrical insulating substrates 2 and 6 mounted on the electrical insulating substrates 3 and 5 on which the components are mounted. .
- the provision of the through-holes 28 can reduce the compressive stress that occurs in individual components during lamination, and can prevent deterioration of electrical characteristics.
- via-hole conductors 27, electrodes, wiring circuit patterns, etc. were formed on the electrically insulating substrates 2 and 6, forming the through-holes 28 softened the electrically insulating substrates 2 and 6 at the time of lamination and the via holes.
- the height of the magnetic material 13 A, 13 B and the semiconductor bare chip 8 or chip component 9 after mounting on the same surface are different, use an electrically insulating substrate provided with through holes 28 corresponding to the respective projected areas. Use multiple boards and stack them so that the thickness of the electrically insulating board is about 5% of the mounting thickness of each board.
- a large-capacity capacitor 10 is electrically connected to the uppermost layer of the laminate by solder 24.
- an adhesive 20 is applied to a gap between the large-capacity capacitor 10 and the electrically insulating substrate 1. Thereby, it is possible to prevent the entrapment of air when the large-capacity capacitor 10 and the electric insulating resin are applied, and the generation of an air pocket between the gaps.
- an electrically insulating resin 16 is applied flat so as to cover the large capacity capacitor 10.
- the module with a built-in circuit component of the present invention includes a laminate in which a plurality of insulating resin layers are laminated in multiple layers, and a wiring provided in the laminate.
- the coil has a coil pattern in which a conductor pattern is formed continuously in a laminated body, and has a configuration in which the coil pattern is sandwiched between ferrite layers. Since the IC chip and chip components that were conventionally mounted on the surface can be embedded in the laminate, and the coil part with a large external shape and mounting area can be formed in the laminate, a small Z Module parts can be realized.
- it has a configuration in which a plurality of coil patterns are formed in the same laminated body, and one end of each coil pattern is electrically connected to one end of a coil pattern of another layer.
- a thin coil can be formed inside the laminate, and the module can be made thinner and smaller.
- each coil pattern of the coil portion and one end of the coil pattern of the other layer are electrically connected via a via-hole conductor, so that a connection portion can be formed at an arbitrary position.
- the module components can be made thinner and smaller.
- the coil pattern is made of a conductor pattern including Cu and Ag, so that it is possible to realize a module component having lower electric resistance and lower resistance.
- the large-capacitance capacitor has a configuration consisting of a sheet capacitor or a ceramic capacitor.
- Sheet capacitors have a high capacity per unit volume, and can realize small and thin module components.
- Ceramic capacitors have low ESR and can realize module components with low module power consumption.
- the large-capacitance condenser has a configuration that covers a part or all of the large-capacitance condenser with insulating resin, and can be used as an adsorption surface when mounting the laminate on a single mother board, realizing module parts with excellent mountability. can do.
- active components semiconductor devices, LSIs, ICs, etc.
- passive components capacitors, resistors, filters, oscillating devices, coils, etc.
- It can be built-in, and can provide a small module component with a built-in high-density circuit component.
- an IC chip and a chip component can be built in the laminate.
- a coil component having a large external shape and a large mounting area can be formed in the laminate, thereby realizing a small and high-density module component.
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/433,843 US6828670B2 (en) | 2001-10-15 | 2002-10-11 | Module component |
EP02801549A EP1365451A4 (en) | 2001-10-15 | 2002-10-11 | MODULE COMPONENT |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001-316407 | 2001-10-15 | ||
JP2001316407A JP2003124429A (ja) | 2001-10-15 | 2001-10-15 | モジュール部品 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2003034494A1 true WO2003034494A1 (en) | 2003-04-24 |
Family
ID=19134429
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2002/010591 WO2003034494A1 (en) | 2001-10-15 | 2002-10-11 | Module component |
Country Status (5)
Country | Link |
---|---|
US (1) | US6828670B2 (ja) |
EP (1) | EP1365451A4 (ja) |
JP (1) | JP2003124429A (ja) |
CN (1) | CN100382309C (ja) |
WO (1) | WO2003034494A1 (ja) |
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- 2002-10-11 CN CNB028031830A patent/CN100382309C/zh not_active Expired - Fee Related
- 2002-10-11 WO PCT/JP2002/010591 patent/WO2003034494A1/ja active Application Filing
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Also Published As
Publication number | Publication date |
---|---|
CN100382309C (zh) | 2008-04-16 |
JP2003124429A (ja) | 2003-04-25 |
US20040021218A1 (en) | 2004-02-05 |
EP1365451A1 (en) | 2003-11-26 |
CN1476636A (zh) | 2004-02-18 |
EP1365451A4 (en) | 2010-06-23 |
US6828670B2 (en) | 2004-12-07 |
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