WO2003038861A3 - A method of stacking layers containing encapsulated integrated circuit chips with one or more overlying interconnect layers - Google Patents
A method of stacking layers containing encapsulated integrated circuit chips with one or more overlying interconnect layers Download PDFInfo
- Publication number
- WO2003038861A3 WO2003038861A3 PCT/US2002/034339 US0234339W WO03038861A3 WO 2003038861 A3 WO2003038861 A3 WO 2003038861A3 US 0234339 W US0234339 W US 0234339W WO 03038861 A3 WO03038861 A3 WO 03038861A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- integrated circuit
- chip
- interconnect assembly
- test pad
- interconnect
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5388—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates for flat cards, e.g. credit cards
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1064—Electrical connections provided on a side surface of one or more of the containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1433—Application-specific integrated circuit [ASIC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
Abstract
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AT02789292T ATE444564T1 (en) | 2001-10-30 | 2002-10-25 | STACKABLE LAYERS INCLUDING ENCAPSULATED INTEGRATED CIRCUIT CHIPS WITH ONE OR MORE OVERLYING INTERCONNECT LAYERS AND METHODS FOR PRODUCING THEREOF |
AU2002353894A AU2002353894A1 (en) | 2001-10-30 | 2002-10-25 | A method of stacking layers containing encapsulated integrated circuit chips with one or more overlying interconnect layers |
EP02789292A EP1576649B1 (en) | 2001-10-30 | 2002-10-25 | Stackable layers containing encapsulated integrated circuit chips with one or more overlying interconnect layers and a method of making the same |
DE60233902T DE60233902D1 (en) | 2001-10-30 | 2002-10-25 | STACKABLE LAYERS INCLUDE THE ENCAPSULATED INTEGRATED CIRCUITING SCHIPS WITH ONE OR MORE CONNECTING LINES THEREOF, AND METHOD FOR THE PRODUCTION THEREOF |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/938,686 US6797537B2 (en) | 2001-10-30 | 2001-10-30 | Method of making stackable layers containing encapsulated integrated circuit chips with one or more overlaying interconnect layers |
US09/938,686 | 2001-10-30 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2003038861A2 WO2003038861A2 (en) | 2003-05-08 |
WO2003038861A3 true WO2003038861A3 (en) | 2005-12-29 |
Family
ID=25471798
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2002/034339 WO2003038861A2 (en) | 2001-10-30 | 2002-10-25 | A method of stacking layers containing encapsulated integrated circuit chips with one or more overlying interconnect layers |
Country Status (6)
Country | Link |
---|---|
US (3) | US6797537B2 (en) |
EP (3) | EP2101349A3 (en) |
AT (1) | ATE444564T1 (en) |
AU (1) | AU2002353894A1 (en) |
DE (1) | DE60233902D1 (en) |
WO (1) | WO2003038861A2 (en) |
Families Citing this family (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7440449B2 (en) * | 2000-10-06 | 2008-10-21 | Irvine Sensors Corp. | High speed switching module comprised of stacked layers incorporating t-connect structures |
US7242082B2 (en) | 2002-02-07 | 2007-07-10 | Irvine Sensors Corp. | Stackable layer containing ball grid array package |
SG115459A1 (en) * | 2002-03-04 | 2005-10-28 | Micron Technology Inc | Flip chip packaging using recessed interposer terminals |
US7777321B2 (en) | 2002-04-22 | 2010-08-17 | Gann Keith D | Stacked microelectronic layer and module with three-axis channel T-connects |
US6806559B2 (en) * | 2002-04-22 | 2004-10-19 | Irvine Sensors Corporation | Method and apparatus for connecting vertically stacked integrated circuit chips |
US6998328B2 (en) * | 2002-11-06 | 2006-02-14 | Irvine Sensors Corp. | Method for creating neo-wafers from singulated integrated circuit die and a device made according to the method |
US7198965B2 (en) * | 2002-11-06 | 2007-04-03 | Irvine Sensors Corp. | Method for making a neo-layer comprising embedded discrete components |
US20050184368A1 (en) * | 2003-01-21 | 2005-08-25 | Huang Chien P. | Semiconductor package free of substrate and fabrication method thereof |
EP1652233A4 (en) * | 2003-08-08 | 2009-11-25 | Aprolase Dev Co Llc | Stackable layers containing ball grid array packages |
CN101044610A (en) * | 2004-08-20 | 2007-09-26 | 皇家飞利浦电子股份有限公司 | Method of detaching a thin semiconductor circuit from its base |
US7268012B2 (en) * | 2004-08-31 | 2007-09-11 | Micron Technology, Inc. | Methods for fabrication of thin semiconductor assemblies including redistribution layers and packages and assemblies formed thereby |
EP1724835A1 (en) | 2005-05-17 | 2006-11-22 | Irvine Sensors Corporation | Electronic module comprising a layer containing integrated circuit die and a method for making the same |
US7919844B2 (en) * | 2005-05-26 | 2011-04-05 | Aprolase Development Co., Llc | Tier structure with tier frame having a feedthrough structure |
US7768113B2 (en) * | 2005-05-26 | 2010-08-03 | Volkan Ozguz | Stackable tier structure comprising prefabricated high density feedthrough |
JP5065586B2 (en) * | 2005-10-18 | 2012-11-07 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
JP2007115958A (en) * | 2005-10-21 | 2007-05-10 | Seiko Epson Corp | Semiconductor device |
US8432026B2 (en) * | 2006-08-04 | 2013-04-30 | Stats Chippac Ltd. | Stackable multi-chip package system |
US7622333B2 (en) * | 2006-08-04 | 2009-11-24 | Stats Chippac Ltd. | Integrated circuit package system for package stacking and manufacturing method thereof |
US7645638B2 (en) * | 2006-08-04 | 2010-01-12 | Stats Chippac Ltd. | Stackable multi-chip package system with support structure |
US8110899B2 (en) * | 2006-12-20 | 2012-02-07 | Intel Corporation | Method for incorporating existing silicon die into 3D integrated stack |
KR100843718B1 (en) * | 2007-01-25 | 2008-07-04 | 삼성전자주식회사 | Semiconductor packages having immunity against void due to adhesive material and methods of forming the same |
KR100887475B1 (en) * | 2007-02-26 | 2009-03-10 | 주식회사 네패스 | Semiconductor package and fabrication method thereof |
US7714426B1 (en) | 2007-07-07 | 2010-05-11 | Keith Gann | Ball grid array package format layers and structure |
US7863918B2 (en) | 2007-11-13 | 2011-01-04 | International Business Machines Corporation | Disposable built-in self-test devices, systems and methods for testing three dimensional integrated circuits |
TWI455263B (en) * | 2009-02-16 | 2014-10-01 | Ind Tech Res Inst | Chip package structure and chip package method |
US9431275B2 (en) | 2010-09-17 | 2016-08-30 | Pfg Ip Llc | Wire bond through-via structure and method |
US8609473B2 (en) | 2010-09-17 | 2013-12-17 | ISC8 Inc. | Method for fabricating a neo-layer using stud bumped bare die |
US8649820B2 (en) | 2011-11-07 | 2014-02-11 | Blackberry Limited | Universal integrated circuit card apparatus and related methods |
USD703208S1 (en) | 2012-04-13 | 2014-04-22 | Blackberry Limited | UICC apparatus |
US8936199B2 (en) | 2012-04-13 | 2015-01-20 | Blackberry Limited | UICC apparatus and related methods |
USD701864S1 (en) * | 2012-04-23 | 2014-04-01 | Blackberry Limited | UICC apparatus |
US9196504B2 (en) | 2012-07-03 | 2015-11-24 | Utac Dongguan Ltd. | Thermal leadless array package with die attach pad locking feature |
US9023690B2 (en) * | 2012-11-19 | 2015-05-05 | United Test And Assembly Center | Leadframe area array packaging technology |
US9564387B2 (en) | 2014-08-28 | 2017-02-07 | UTAC Headquarters Pte. Ltd. | Semiconductor package having routing traces therein |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6184060B1 (en) * | 1996-10-29 | 2001-02-06 | Trusi Technologies Llc | Integrated circuits and methods for their fabrication |
US6235552B1 (en) * | 1999-07-09 | 2001-05-22 | Samsung Electronics Co., Ltd. | Chip scale package and method for manufacturing the same using a redistribution substrate |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE69231785T2 (en) * | 1992-09-14 | 2001-11-15 | Shellcase Ltd | METHOD FOR PRODUCING INTEGRATED CIRCUIT ARRANGEMENTS |
US5953588A (en) | 1996-12-21 | 1999-09-14 | Irvine Sensors Corporation | Stackable layers containing encapsulated IC chips |
US6329832B1 (en) * | 1998-10-05 | 2001-12-11 | Micron Technology, Inc. | Method for in-line testing of flip-chip semiconductor assemblies |
US6117704A (en) * | 1999-03-31 | 2000-09-12 | Irvine Sensors Corporation | Stackable layers containing encapsulated chips |
JP2001144218A (en) * | 1999-11-17 | 2001-05-25 | Sony Corp | Semiconductor device and method of manufacture |
-
2001
- 2001-10-30 US US09/938,686 patent/US6797537B2/en not_active Expired - Lifetime
-
2002
- 2002-10-25 AT AT02789292T patent/ATE444564T1/en not_active IP Right Cessation
- 2002-10-25 WO PCT/US2002/034339 patent/WO2003038861A2/en not_active Application Discontinuation
- 2002-10-25 EP EP09164532A patent/EP2101349A3/en not_active Withdrawn
- 2002-10-25 EP EP13199181.2A patent/EP2711976A2/en not_active Withdrawn
- 2002-10-25 EP EP02789292A patent/EP1576649B1/en not_active Expired - Lifetime
- 2002-10-25 DE DE60233902T patent/DE60233902D1/en not_active Expired - Lifetime
- 2002-10-25 AU AU2002353894A patent/AU2002353894A1/en not_active Abandoned
- 2002-11-21 US US10/302,680 patent/US6784547B2/en not_active Expired - Lifetime
-
2004
- 2004-09-28 US US10/951,990 patent/US7239012B2/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6184060B1 (en) * | 1996-10-29 | 2001-02-06 | Trusi Technologies Llc | Integrated circuits and methods for their fabrication |
US6235552B1 (en) * | 1999-07-09 | 2001-05-22 | Samsung Electronics Co., Ltd. | Chip scale package and method for manufacturing the same using a redistribution substrate |
Also Published As
Publication number | Publication date |
---|---|
DE60233902D1 (en) | 2009-11-12 |
EP1576649A4 (en) | 2006-11-15 |
EP1576649B1 (en) | 2009-09-30 |
EP1576649A2 (en) | 2005-09-21 |
US6784547B2 (en) | 2004-08-31 |
US20030080419A1 (en) | 2003-05-01 |
AU2002353894A1 (en) | 2003-05-12 |
US20030127735A1 (en) | 2003-07-10 |
EP2101349A3 (en) | 2011-08-17 |
EP2101349A2 (en) | 2009-09-16 |
US6797537B2 (en) | 2004-09-28 |
EP2711976A2 (en) | 2014-03-26 |
US20050037540A1 (en) | 2005-02-17 |
US7239012B2 (en) | 2007-07-03 |
WO2003038861A2 (en) | 2003-05-08 |
ATE444564T1 (en) | 2009-10-15 |
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