WO2003044658A3 - Context scheduling - Google Patents

Context scheduling Download PDF

Info

Publication number
WO2003044658A3
WO2003044658A3 PCT/US2002/036687 US0236687W WO03044658A3 WO 2003044658 A3 WO2003044658 A3 WO 2003044658A3 US 0236687 W US0236687 W US 0236687W WO 03044658 A3 WO03044658 A3 WO 03044658A3
Authority
WO
WIPO (PCT)
Prior art keywords
instruction
condition signals
logic
sampled
scheduling
Prior art date
Application number
PCT/US2002/036687
Other languages
French (fr)
Other versions
WO2003044658A2 (en
Inventor
John Wishneusky
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to EP02797114A priority Critical patent/EP1449071B1/en
Priority to DE60228116T priority patent/DE60228116D1/en
Priority to AU2002361634A priority patent/AU2002361634A1/en
Priority to CA002465015A priority patent/CA2465015C/en
Publication of WO2003044658A2 publication Critical patent/WO2003044658A2/en
Publication of WO2003044658A3 publication Critical patent/WO2003044658A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming

Abstract

A programmable processing system that executes multiple instruction contexts includes an instruction memory for storing instructions that are executed by the system, fetch logic for determining an address of an instruction, with the fetch logic including scheduling logic that schedules execution of the instruction contexts based on condition signals indicating an availability of a hardware resource, with the condition signals being divided into groups of condition signals, which are sampled in turn by the scheduling logic to provide a plurality of scan sets of sampled conditions.
PCT/US2002/036687 2001-11-19 2002-11-13 Context scheduling WO2003044658A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP02797114A EP1449071B1 (en) 2001-11-19 2002-11-13 Context scheduling
DE60228116T DE60228116D1 (en) 2001-11-19 2002-11-13 CONTEXT-SCHEDULING
AU2002361634A AU2002361634A1 (en) 2001-11-19 2002-11-13 Context scheduling
CA002465015A CA2465015C (en) 2001-11-19 2002-11-13 Context scheduling

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/989,482 2001-11-19
US09/989,482 US6901507B2 (en) 2001-11-19 2001-11-19 Context scheduling

Publications (2)

Publication Number Publication Date
WO2003044658A2 WO2003044658A2 (en) 2003-05-30
WO2003044658A3 true WO2003044658A3 (en) 2004-02-26

Family

ID=25535148

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/036687 WO2003044658A2 (en) 2001-11-19 2002-11-13 Context scheduling

Country Status (8)

Country Link
US (2) US6901507B2 (en)
EP (1) EP1449071B1 (en)
AT (1) ATE403903T1 (en)
AU (1) AU2002361634A1 (en)
CA (1) CA2465015C (en)
DE (1) DE60228116D1 (en)
TW (1) TWI248019B (en)
WO (1) WO2003044658A2 (en)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6047284A (en) 1997-05-14 2000-04-04 Portal Software, Inc. Method and apparatus for object oriented storage and retrieval of data from a relational database
US8099393B2 (en) 2002-03-22 2012-01-17 Oracle International Corporation Transaction in memory object store
US20040034759A1 (en) * 2002-08-16 2004-02-19 Lexra, Inc. Multi-threaded pipeline with context issue rules
DE102004059972B4 (en) * 2004-12-13 2010-07-01 Infineon Technologies Ag Thread scheduling method, and thread list scheduler device
US7713330B2 (en) * 2004-12-22 2010-05-11 Oreck Holdings, Llc Tower ionizer air cleaner
US7631132B1 (en) * 2004-12-27 2009-12-08 Unisys Corporation Method and apparatus for prioritized transaction queuing
US8223935B2 (en) 2005-04-30 2012-07-17 Oracle International Corporation Revenue management systems and methods
EP1935152A4 (en) 2005-06-28 2010-08-04 Oracle Int Corp Revenue management system and method
CA2616194C (en) 2005-07-28 2015-02-17 Oracle International Corporation Revenue management system and method
US8223777B2 (en) 2005-11-15 2012-07-17 Oracle International Corporation Gateway for achieving low latency and high availability in a real time event processing system
TW200945205A (en) * 2008-04-18 2009-11-01 Inventec Corp A divided disk command processing system and method thereof
US8561072B2 (en) * 2008-05-16 2013-10-15 Microsoft Corporation Scheduling collections in a scheduler
CN103761073A (en) * 2014-01-08 2014-04-30 东南大学 ARMv7-oriented prediction-based dynamic instruction scheduling method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0942366A2 (en) * 1998-03-10 1999-09-15 Lucent Technologies Inc. Event-driven and cyclic context controller and processor employing the same
US6092180A (en) * 1997-11-26 2000-07-18 Digital Equipment Corporation Method for measuring latencies by randomly selected sampling of the instructions while the instruction are executed

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4975828A (en) 1987-08-05 1990-12-04 Cirrus Logic, Inc. Multi-channel data communications controller
US6728959B1 (en) * 1995-08-08 2004-04-27 Novell, Inc. Method and apparatus for strong affinity multiprocessor scheduling
US6073159A (en) * 1996-12-31 2000-06-06 Compaq Computer Corporation Thread properties attribute vector based thread selection in multithreading processor
US6493741B1 (en) * 1999-10-01 2002-12-10 Compaq Information Technologies Group, L.P. Method and apparatus to quiesce a portion of a simultaneous multithreaded central processing unit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6092180A (en) * 1997-11-26 2000-07-18 Digital Equipment Corporation Method for measuring latencies by randomly selected sampling of the instructions while the instruction are executed
EP0942366A2 (en) * 1998-03-10 1999-09-15 Lucent Technologies Inc. Event-driven and cyclic context controller and processor employing the same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
ANANT AGARWAL ET AL: "SPARCLE: AN EVOLUTIONARY PROCESSOR DESIGN FOR LARGE-SCALE MULTIPROCESSORS", IEEE MICRO, IEEE INC. NEW YORK, US, vol. 13, no. 3, 1 June 1993 (1993-06-01), pages 48 - 61, XP000380339, ISSN: 0272-1732 *

Also Published As

Publication number Publication date
WO2003044658A2 (en) 2003-05-30
DE60228116D1 (en) 2008-09-18
TW200302979A (en) 2003-08-16
US20060026596A1 (en) 2006-02-02
EP1449071B1 (en) 2008-08-06
AU2002361634A1 (en) 2003-06-10
EP1449071A2 (en) 2004-08-25
US6901507B2 (en) 2005-05-31
ATE403903T1 (en) 2008-08-15
TWI248019B (en) 2006-01-21
CA2465015C (en) 2010-01-05
US20030097547A1 (en) 2003-05-22
CA2465015A1 (en) 2003-05-30
AU2002361634A8 (en) 2003-06-10

Similar Documents

Publication Publication Date Title
WO2003044658A3 (en) Context scheduling
WO2006095184A3 (en) Data processing system
ATE514998T1 (en) CLOCKED PORTS
WO2006083543A3 (en) Multithreading processor including thread scheduler based on instruction stall likelihood prediction
WO2005103887A3 (en) Methods and apparatus for address map optimization on a multi-scalar extension
WO2011081704A3 (en) Handling operating system (os) transitions in an unbounded transactional memory (utm) mode
WO2005050445A3 (en) An apparatus and method for an automatic thread-partition compiler
WO2003058447A3 (en) A method and apparatus for suspending execution of a thread until a specified memory access occurs
WO2011063396A3 (en) Stream-based software application delivery and launching system
EP0994413A3 (en) Data processing system with conditional execution of extended compound instructions
WO2010078017A3 (en) Interrupt techniques
EP2339455A3 (en) Multithreaded processor with interleaved instruction pipelines
WO2006018307A3 (en) Operating systems
WO2001082075A3 (en) System and method for scheduling execution of cross-platform computer processes
TW200719275A (en) Method for an interruptible graphics processing unit to process multi-programs and graphics processing unit
EP1696317A3 (en) Programmable delayed dispatch in a multi-threaded pipeline
AU2003223374A1 (en) Registers for data transfers within a multithreaded processor
TW200834323A (en) Tier-based memory read/write micro-command scheduler
CN106030559A (en) Syncronization of interrupt processing to reduce power consumption
WO2006116046A3 (en) Asynchronous processor
US8522242B2 (en) Conditional batch buffer execution
ATE463011T1 (en) HIERARCHICAL PROCESSOR ARCHITECTURE FOR VIDEO PROCESSING
TW200702985A (en) Method and system of changing a startup list of programs to determine whether computer system performance increases
WO2021101246A3 (en) Method for preloading application and electronic device supporting same
EP1808766A3 (en) Microcomputer provided with instruction cache memory

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ OM PH PL PT RO RU SD SE SG SI SK SL TJ TM TN TR TT TZ UA UG UZ VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR IE IT LU MC NL PT SE SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
WWE Wipo information: entry into national phase

Ref document number: 2465015

Country of ref document: CA

WWE Wipo information: entry into national phase

Ref document number: 2002797114

Country of ref document: EP

WWP Wipo information: published in national office

Ref document number: 2002797114

Country of ref document: EP

NENP Non-entry into the national phase

Ref country code: JP

WWW Wipo information: withdrawn in national office

Country of ref document: JP