WO2003047091A2

WO2003047091A2 - A data processing circuit

Info

Publication number: WO2003047091A2
Application number: PCT/GB2002/005141
Authority: WO
Inventors: John Reeve; Alan Plews
Original assignee: Ubinetics Limited
Priority date: 2001-11-22
Filing date: 2002-11-14
Publication date: 2003-06-05
Also published as: GB2382506B; GB0128039D0; GB2382506A; AU2002339162A8; WO2003047091A3; AU2002339162A1

Abstract

A data processing circuit for a communication receiver comprises an input path (23), a control (27), a sign modifying module (29), first and second delay elements (31, 33), first and second multiplying means (35, 37) and a summing module (39). The control module (27) is arranged to generate control signals for controlling the operation of the sign modifying module (29), by means of control line (41), and the first and second multiplying means, by means of respective control lines (43, 45). In operation, input samples (e.g. from an ADC) are fed at a clock rate to an input of the sign modifying module (29). The sign modifying module (29) acts to modify the sign of the value of incoming samples in accordance with a control signal from the control module (27). The output of the sign modifying module (29) splits into two paths (30a, 30b). The first path (30a) includes the first and second delay elements (31, 33) and the first multiplying means (35). The second path (30b) includes the second multiplying means (37). In the first path (30a), samples outputted from the sign modifying module are delayed by two clock periods by the first and second delay elements (31, 33), each delay element delaying throughput of the samples by one clock period. The first and second multiplying means (35, 37) are arranged to multiply applied input samples by one of two different weighting factors. Finally, the outputted samples from the first and second multiplying means (35, 37) are each fed to the summing module (39) whereby the value of the output samples are added together.

Description

A Data Processing Circuit

This invention relates to a data processing circuit, and particularly to a data processing circuit for a digital communications receiver.

The use of digital signal processing elements in modern communications receivers is well known. Typically, analogue signal processing elements are replaced with digital signal processing equivalents, which equivalents have particular advantages in terms of overcoming, or at least reducing, problems associated with component imperfection and variation. The use of digital signal processing elements results in improved system performance, high reliability, and enables high manufacturing yields to be achieved.

Figure 1 is a block diagram of a known digital receiver circuit. At an input stage of the receiver (not shown) a high frequency analogue signal is received, e.g. by means of an antenna, after which the signal is sampled and quantised by a high speed analogue-to-digital converter (ADC). The digital data output from the ADC is transferred along an input line 1 at a predetermined clock rate. A digital phase accumulator 3 is provided, connected to a digital sine wave generator 5 and a digital cosine wave generator 7. The accumulator 3 outputs a phase signal which increases by a fixed increment for each clock pulse received. The phase signal, when input to the sine and cosine wave generators 5, 7 cause digital values representative of a sine and cosine wave to be output from a look-up table. The frequencies of the sine and cosine waves are identical and can be adjusted by altering the phase increment of the accumulator 3. The sine and cosine waves are separately multiplied with the data from the ADC by means of a first and second digital multipliers 9, 11. As will be understood, the output of the first and second digital multipliers 9, 11 comprises the sum and difference frequencies of the digitised data, output from the ADC and the sine and cosine waves. By using the sine and cosine waves, both in-phase (I) and quadrature phase (Q) data is outputted. First and second digital filters 13, 15 are provided at the respective outputs of the first and second multipliers 9, 11. These filters 13, 15 can be based on a finite impulse response (FIR) or a cascaded integrator (often called a CIC) arrangement. The filters 13, 15 are used to eliminate the sum frequencies, leaving only the difference frequencies. Separation into the I and Q components enables the information contained in the full bandwidth to be resolved using the difference frequencies only. For the convenience of further processing, the I and Q data can then be decimated by two using first and second decimators 17, 19, connected to the respective outputs of the first and second filters 13, 15. The decimated signals are then multiplexed by a multiplexer 21 to form a data stream comprising alternate I and Q data at the same sample rate as the clock.

In order to implement the circuit of Figure 1, a large number of digital gates and flip-flops are required, and consequently, there is a high power consumption. A modification of the circuit of Figure 1 is shown is Figure 2. As will be seen from Figure 2, the only difference between the circuit shown and that shown in Figure 1 is that the accumulator 3 and the sine and cosine wave generators 5, 7 have been replaced with modified sine and cosine wave generators 6, 8. The modified sine and cosine wave generators 6, 8 are restricted to output values at exactly one quarter of the sample clock rate. A sine wave will follow the pattern 0, 1, 0, -1, whilst at the same time, the cosine wave will follow the pattern 1, 0, -1, 0. This results in a significant simplification of the sine and cosine wave generators 6, 8 and also allows simplification of the multipliers 9, 11 since these are only required to multiply by 1, -1, and 0. Although the receiver is restricted to signals at one quarter of the sample rate, and the associated alias frequencies, the saving on digital gates resulting in a reduced complexity and power consumption make this architecture attractive in many applications.

In terms of resources required, assuming the input data (i.e. from the ADC) to be 14 bits long, it is estimated that the circuit of Figure 1 will require 1000 flip flops plus an 8k by 14 bit memory. It is estimated that the circuit of Figure 2 will require 300 flip-flops.

Although the circuit shown in Figure 2 provides an improvement, it is still desirable to be able to simplify such architectures. According to one aspect of the invention, there is provided a data processing circuit for use in a digital receiver, the data processing circuit comprising: an input for receiving data samples at a predetermined clock rate; sign modifying means connected to the input, the sign modifying means being arranged to (i) modify the sign of the value of two successive data samples, (ii) to leave the sign of the value of the subsequent two successive data samples unmodified, and (iii) to repeat steps (i) and (ii) for subsequent samples, the data samples being outputted on first and second data paths; wherein the first data path includes (a) delay means arranged such that data samples on the first path are delayed by at least one clock period in relation to the same data samples on the second path, and (b) first weighting means arranged to weight the value of the data samples by the either a first or second predetermined amount, and wherein the second data path comprises a second weighting means arranged to weight the value of the data samples by either the first or second predetermined amount; the first and second data paths being connected to an adding means for adding the value of the weighted samples together.

In the context of this application, the term 'weight' is intended to mean that the value of the data samples is multiplied by some factor (which can be One'). It will be appreciated that, in terms of implementation, weighting can be achieved in a number of ways, e.g. multiplication, repeated addition, shifting binary digits, and so on.

The data processing circuit has been found to have particular advantages in that the circuit is able to perform the required data processing in a communications receiver whilst using a simplified circuit architecture. In particular, less gates are used and so power dissipation will be reduced. As will become clear below, the circuit effectively combines the digital frequency conversion and filtering operations to enable a simplified circuit arrangement to be used.

In the preferred embodiment, the first and second weighting means are arranged such that the first and second predetermined amounts, by which the data samples are weighted, are, respectively, one and three. As indicated above, any one of the first and second weighting means can be provided in the form of digital multipliers. In an alternative configuration, any one of the first and second weighting means can comprise: an adder arranged to receive the data samples and to weight the value of the data samples by the second predetermined amount; and a multiplexing means arranged to receive the data samples and the weighted output from the adder, the multiplexing means being arranged so as to output either one of (a) the value of the data samples, or (b) the value of the data samples weighted by the second predetermined amount.

A control module may be provided for generating a first control signal for input to the sign modifying means thereby to control the performance of steps (i), (ii) and (iii), mentioned above, and to output second and third control signals for input to, respectively, the first and second weighting means thereby to control whether the value of the data samples is to be weighted by the first or second predetermined amount.

The input can be connected to an ADC stage.

Preferably, at any given clock period, the first weighting means is arranged to weight the value of the data sample at its input by the first predetermined amount, and the second weighting means is arranged to weight the value of the data sample at its input by the second predetermined amount, and at the following clock period, the first weighting means is arranged to weight the value of the data sample at its input by the second predetermined amount, and the second weighting means is arranged to weight the value of the data sample at its input by the first predetermined amount.

According to a second aspect of the invention, there is provided a data processing circuit for use in a digital receiver, the data processing circuit comprising: an input for receiving data samples at a predetermined clock rate; sign modifying means connected to the input, the sign modifying means being arranged to (i) modify the sign of the value of two successive data samples, (ii) to leave the sign of the value of the subsequent two successive data samples unmodified, and (iii) to repeat steps (i) and (ii) for subsequent samples, the data samples being outputted on first and second data paths; wherein the first data path includes (a) delay means arranged such that data samples on the first data path are delayed by at least one clock period in relation to the same data samples on the second data path, and (b) first weighting means arranged to weight the value of the data samples by either one or three, and wherein the second data path includes second weighting means arranged to weight the value of the data samples by three when the data samples on the first data path are weighted by one, and by one when the data samples on the first data path are weighted by three, the first and second data paths being connected to an adding means for adding the value of the weighted samples together.

According to a third aspect of the invention, there is provided a data processing circuit for use in a digital receiver, the data processing circuit comprising: an input for receiving data samples at a predetermined clock rate; sign modifying means connected to the input, the sign modifying means being arranged to (i) modify the sign of the value of two successive data samples, (ii) to leave the sign of the value of the subsequent two successive data samples unmodified, and (iii) to repeat steps (i) and (ii) for subsequent samples, the data samples being outputted on first and second data paths; wherein the first data path includes (a) delay means arranged such that data samples on the first path are delayed by at least one clock period in relation to the same data samples on the second path, and (b) first weighting means arranged to weight the value of the data samples by a first fixed amount, and wherein the second data path comprises a second weighting means arranged to weight the value of the data samples by a second fixed amount; the first and second data paths being connected to an adding means for adding the value of the weighted samples together.

In some commercially available ADCs, samples are demultiplexed within the ADC and routed onto two buses which operate at half the speed, thus enabling convenient routing to subsequent digital processing hardware. Alternate samples can be present on the two buses.

According to a fourth aspect of the invention, there is provided A data processing circuit for use in a digital receiver, the data processing circuit comprising: an input arranged to receive data samples at a predetermined clock rate, and means arranged to demultiplex alternate data samples onto first and second data paths, the first and second data paths operating at a data rate substantially half that of the predetermined clock rate; first and second sign modifying means respectively connected to the first and second data paths, each sign modifying means being arranged to modify the sign of the value of every other data sample on the first and second data paths and to output the data samples onto first and second sub-paths of each data path; wherein the first sub-path of the first data path is arranged to weight the value of the data samples by a first amount, and wherein the second sub-path of the first data path (i) includes delay means for delaying the data samples by a predetermined number of clock period(s), and (ii) is arranged to weight the value of the data samples by a second amount; wherein the first sub-path of the second data path is arranged to weight the value of the data samples by the second amount, and wherein the second sub-path of the second data path (i) includes a delay means for delaying the data samples by the predetermined number of clock period(s), and (ii) is arranged to weight the value of the data samples by the first amount; the first and second sub-paths of the first and second data paths being connected to adding means for adding the value of the samples on the first and second sub-paths together.

According to a fifth aspect of the invention, there is provided a data processing circuit for use in a digital receiver, the data processing circuit comprising: an input for receiving data samples at a predetermined clock rate; means arranged to effect a filtering operation on the data samples, the filtering means having predetermined coefficients; means arranged to down-convert the data samples by one-quarter of the clock rate; and means arranged to decimate the data samples by two.

The data processing circuit can be fabricated in an integrated circuit (IC) package. The data processing circuit could be conveniently implemented as part of an application specific integrated circuit (ASIC). A programmable device, such as a Field Programmable Gate Array (FPGA), may also be programmed so as to incorporate such a data processing circuit. In a sixth aspect of the invention, there is provided a method of processing data in a digital receiver circuit, the method comprising: receiving an input signal and generating therefrom data samples at a predetermined clock rate; applying the data samples to a digital filter having predetermined coefficients; down-converting the frequency of the samples outputted from the digital filter by one-quarter of the clock rate; and decimating the samples, at the down-converted frequency, by two.

Preferably, the coefficients 1, 3, 3 and 1 are used. In this respect, it is found that by using the coefficients 1, 3, 3 and 1, a substantial reduction in devices is achieved.

The invention will now be described, by way of example, with reference to Figures 3 to 9 of the accompanying drawings, in which:

Figure 3 is a table showing relative attenuation against frequency for a digital filter having particular filter coefficients;

Figure 4 is a table showing the output from a sine and a cosine generator at different clock periods;

Figure 5 is a table showing the expected I and Q output data from a digital processing circuit at different clock periods;

Figure 6 is a table showing how expected I and Q output data can be calculated using a reduced number of samples;

Figure 7 is a block diagram showing the main functional blocks in a data processing circuit according to a preferred embodiment of the invention;

Figure 8 is a block diagram showing circuit components arranged so as to implement the data processing circuit of Figure 7 in an improved manner; Figure 9 is a block diagram showing circuit components arranged so as to implement the data processing circuit of Figure 7 in a further improved manner; and

Figure 10 is a block diagram showing the main functional blocks in a data processing circuit which includes a dual input bus.

A preferred circuit architecture will be described below. This circuit architecture is designed to implement a data processing operation in a communications receiver, a similar operation having been described above with reference to Figures 1 and 2. Figures 3 to 6 are tables showing calculated data values at various parts of the data processing operation. Although calculated using some example values, e.g. the sample rate, bandwidth of the signal etc., analysis of the calculated results has enabled design of a circuit architecture for achieving the required operation. It may be useful to refer to the description relating to Figure 1 when considering the results shown in Figures 3 to 6.

In an example application using a communications receiver, at an input stage of the receiver, a 14-bit ADC is provided at an input stage of the receiver, the ADC sampling incoming data at 100 Mega samples per second (100 MSPS). The analogue input signal has a centre frequency of 25 MHz, i.e. one quarter of the sample rate, and a bandwidth of 5 MHz. The first function of the circuit is to multiply the incoming samples (output from the ADC) by a sine wave and by a cosine wave, say with a frequency of 25 MHz. Resulting I and Q data will contain information relating to both the sum and difference frequencies present. In this example, and with the above values, the difference frequencies occupy a band of 0 - 2.5 MHz and the sum frequencies occupy a band of 47.5 - 50 MHz. It will be noted that the sum and difference frequencies occupy only half of the bandwidth of the original signal. As will be appreciated by those skilled in the art, separation into the I and Q data allows the information contained in the full bandwidth to be resolved using only the difference frequencies. The Nyquist sampling criteria define that the minimum sampling rate which is capable of representing the difference frequencies is twice the bandwidth (of the difference frequencies), and so the minimum sampling rate will be 5 MSPS. However, the I and Q data must be sampled at 100 MSPS in order to represent both the sum and difference frequencies. As a consequence, the sampling rate of the I and Q signals can be reduced providing the sum frequencies are removed using a suitable (in this case digital) filter.

In this example, an FIR filter is envisaged, the transfer function of which is:

where /is the frequency, fsamp is the sample rate (100 MSPS in the above example) and d is the decimation factor, which is chosen to be two here. In the preferred embodiment, the filter part is intended to utilise the coefficients 1, 3, 3, 1.

In order to show the expected gain of the filter using the figures stated above, the following equation is used:

Decibelresponse = 20. logl^— J (2)

At zero frequency, the gain of the filter will be equal to the sum of the coefficients, i.e. eight.

Figure 3 shows the values for relative attenuation versus frequency (calculated using equations (1) and (2) above). It will be seen that the wanted difference frequencies (at 2.5 Mhz) are attenuated by less than 0.08 dB and the sum frequencies are attenuated by greater than 66.32 dB. Thus, the coefficients 1, 3, 3, 1 will provide a suitable filter response for removing the sum frequencies, whilst passing the difference frequencies.

In the next stage, it is required to reduce the sample rate of the filtered I and Q signals by a factor of two. This is achieved by discarding half of the I and Q samples so as to yield two separate sample streams at 50 MSPS. It is convenient to multiplex the I and

Q sample streams together so that only one data stream is presented to subsequent processing blocks. The output will then be at 100 MSPS formatted as serial I and Q sample pairs, each having a sample rate of 50 MSPS.

The method by which the frequency conversion and filtering operations can be integrated so as to enable a simplified circuit architecture to be used, will now be described.

Figure 4 is a table showing values of the sine and cosine waves at particular sample times. The first input sample, sO, will be received first, followed by si, s2 and so on. As the Figure shows, the value of the cosine waveform lags behind that of the sine waveform by one sample period.

Figure 5 shows how the outputs from the filter stage can be calculated at each time period using the sine and cosine values shown in Figure 4, and knowledge of the filter coefficients. The filter output is calculated by summing the coefficients multiplied by the input samples multiplied by the sine or cosine waveforms. This is equivalent to a weighted moving average with the weights being the filter coefficients (in this case 1, 3, 3, 1). Multiplication by the sine wave yields the I output, whilst multiplication by the cosine wave yields the Q output. In order to calculate, for example, the I output at time period '0' it will be understood that the first sample, sO, will be applied to the filter coefficient '1', si to filter coefficient '3', s2 to filter coefficient '3', and s3 to filter coefficient '1'. Accordingly, at time period '0' the I output will be s0x(0 ) + slx(lx3) + s2_x(03) + s3x(- l) which equals 3_*sl - s3. The Q output will be sOx( l) + s (0χ3) + s2x(-lx3) + s3x(0xl) which equals sO - 3_xs2. At time period '1' si will be applied to filter coefficient '1', s2 to filter coefficient to '3', s3 to filter coefficient '3' and s4 to filter coefficient '1' and the calculations are performed as before. Table 5 shows the calculated outputs for both I and Q up to time period '7'.

By analysing the table shown in Figure 5, taking the first computed Q sample, i.e. that computed at time period '0', as 'Q0', it is noted that the result is -3χs2 + sO. Taking s2 as the current input sample, then sO is simply a delayed input sample from two periods previous. The first computed I sample, '10', is then -s3 + 3_xsl which is also computed from the current input sample (si) and that delayed by two periods previous. Given that it is desirable to decimate by two at the output of the filter, it is only necessary to calculate the half of the I and Q samples since the others will be discarded. Hence, the next Q sample will be 3_xs4 - s2, followed by the I sample s5 - 3xs3. Figure 6 shows a table illustrating how the output samples can be computed on the above basis.

Analysis of the table shown in Figure 6 shows that the output can be calculated by adding the current sample multiplied by '+' or '-' and by 1 or 3 with the sample from two time periods previous, itself multiplied by '+' or '-' and by 1 or 3. The pattern of multiplication factors repeats every four time periods. Also, it is observed that the samples si, s4, s5 and s9 are always positive and the samples s2, s3, s6 and s7 are always negative.

Having noted the above relationship, a suitable circuit can now be implemented. A block diagram of such a circuit is shown in Figure 7.

Referring to Figure 7, a data processing circuit for a communications receiver comprises an input path 23, a control module (in the form of a state machine) 27, a sign modifying module 29, first and second delay elements 31, 33, first and second multiplying means 35, 37 and a summing module 39. The control module 27 is arranged to generate control signals for controlling the operation of the sign modifying module 29, by means of control line 41, and the first and second multiplying means, by means of respective control lines 43, 45. The control module 27 is synchronised by a clock signal, received on path 25. The clock signal also synchronises the operation of the first and second delay elements 31, 33.

In operation, input samples (e.g. from an ADC) are fed at the clock rate to an input of the sign modifying module 29. The sign modifying module 29 acts to modify the sign of the value of incoming samples in accordance with a control signal from the control module 27. Specifically, if the control signal is a '1' then the value of the input sample is multiplied by '-!', effectively reversing its current sign, and if the control signal is a '0' the value of the input sample is multiplied by '1' thereby leaving the sign unchanged.

The output of the sign modifying module 29 splits into two paths 30a, 30b. The first path 30a includes the first and second delay elements 31, 33 and the first multiplying means 35. The second path 30b includes the second multiplying means 37. In the first path 30a, samples outputted from the sign modifying module are delayed by two clock periods by the first and second delay elements 31, 33, each delay element delaying throughput of the samples by one clock period.

The first and second multiplying means 35, 37 are arranged to multiply applied input samples by one of two different weighting factors. In this case, given the analysis performed using the table shown in Figure 6, the weighting factors are ' 1' and '3'. Again, the control module 27 is used to control which weighting factor is applied to the current input sample. In the present case, for both multiplying means 35, 37, if the control signal is a '0' then the input sample is multiplied by ' 1 ' and if the control signal is a ' 1 ' then the input sample is multiplied by '3 ' .

Finally, the outputted samples from the first and second multiplying means 35, 37 are each fed to the summing module 39 whereby the value of the output samples are added together.

In order to implement the required digital processing operation required to produce the results shown in Figure 5, and analysed in Figure 6, the control module outputs the control signal '1, 1, 0, 0, 1, 1, 0, etc' on control line 41 to the sign modifying module 29, the control signal '0, 1, 0, 1, 0, 1, etc' on control line 43 to the first multiplying means 35, and the control signal '1, 0, 1, 0, 1, 0, etc' on control line 45 to the second multiplying means 37. Effectively, at a given clock period, it is noted that the weighting value applied to the first multiplying means 35 is different from that applied to the second multiplying means 37, the values alternating for subsequent clock periods. It will be appreciated that these control signal enable the circuit arrangement of Figure 7 to take advantage of the relationship noted in Figure 6 and so provide an implementation for generating the results in Figure 5.

Device-level implementations of the circuit shown in Figure 7 are shown in Figures 8 and 9.

Referring to Figure 8, it will be seen that the circuit comprises a number of modules which are synchronised by a clock signal and which are under the control of a control module (e.g. a state machine) 41. The circuit also comprises a negate element 42, a first multiplexer 44, a two-period delay element 46, first and second adders 48, 50, second and third muliplexers 52, 54, and a third adder 56. The first multiplexer 44 receives, at a first input, the output signal from the negate element 42, and at a second input, the input samples directly from the input. The first multiplexer 44 is controlled so as to switch its output between the negated version of the input samples, outputted from the negate element 42, and the unmodified version of the input samples, taken directly from the input Din. Two paths 45a, 45b are provided at the output of the first multiplexer 44, the first path comprising the two-period delay element 46, the first adder and the second multiplexer 52. The two-period delay element 46 delays the sample present at its input by two clock periods, before transferring the sample to an input of the first adder 48 and the second multiplexer 52. The first adder 48 weights the value of the input samples by three (e.g. by performing addition and then right-shifting the bits). The control signal applied to the second multiplexer 52 causes it to select the output as being either the output from the two-period delay element 46 (this effectively being weighted by 'one') or the value outputted from the adder 48 (being weighted by three). The second path 45b operates in the same way as the first path 45a, except that the two-period delay element 46 is not present. The outputs from the second and third multiplexers 52, 54 are inputted to the adder 56 which generates the output Dout.

It will be appreciated that the implementation of Figure 8 is based directly on the circuit of Figure 7. The number of gates and flip-flops required is kept to a low level. In Figure 9, the implementation shown is a modified version of that shown in Figure 8. The negate element 42, the state machine 41 and the first multiplexer 44 are the same modules used in Figure 8, except that the state machine will output different control signals. In this modified circuit, the upper branch provides delayed and current input samples whilst the lower branch provides delayed and current input samples multiplied by three.

The structure of Figure 9 provides the same operation as that shown in Figure 8, but is more suitable for implementation in a programmable device, such as an FPGA, where a higher sample rate is required.

In terms of resources required, assuming the input data to be 14 bits long, it is estimated that the circuit of Figure 8 will require only 65 flip-flops, whilst the circuit of Figure 9 will require in the region of 92 flip-flops. Compared with the resource requirements of the circuits shown in Figures 1 and 2, there is clearly a large saving. The implementations have also been simulated using Xilinx FPGA simulation tools to determine the maximum operating rate. Implementing the design in a Nirtex 50-6 FPGA device, the circuit in Figure 8 has a maximum sample rate of 120 MSPS and the circuit in Figure 9 has a maximum sample rate of 180 MSPS. These values may differ for different devices.

In some commercially available, very high speed, ADCs, samples are de-multiplexed within the ADC and routed onto two buses which operate at half the speed. This enables the digital signals to be conveniently routed from the ADC to subsequent digital processing hardware. Even samples are present on one bus, whilst odd samples are present on the other bus. To take advantage of this fact, a further circuit, shown in Figure 10, is provided. The architecture shown here uses duplicated versions of the previously described circuits (Figures 8 or 9) for each data stream 72, 73. Since each data stream 72, 73 is operating at half of the overall sample rate, only one delay register 74, 75 is required, instead of two. Also, the delay branch and current sample branches now have fixed gains of either one or three. The output of first and second final adders 76, 77 now consists of I samples for the even sample path, and Q samples for the odd sample path. The maximum achievable sample rate is twice that of the circuit shown in Figure 8.

Claims

1. A data processing circuit for use in a digital receiver, the data processing circuit comprising: an input for receiving data samples at a predetermined clock rate; sign modifying means connected to the input, the sign modifying means being arranged to (i) modify the sign of the value of two successive data samples, (ii) to leave the sign of the value of the subsequent two successive data samples unmodified, and

(iii) to repeat steps (i) and (ii) for subsequent samples, the data samples being outputted on first and second data paths; wherein the first data path includes (a) delay means arranged such that data samples on the first path are delayed by at least one clock period in relation to the same data samples on the second path, and (b) first weighting means arranged to weight the value of the data samples by the either a first or second predetermined amount, and wherein the second data path comprises a second weighting means arranged to weight the value of the data samples by either the first or second predetermined amount; the first and second data paths being connected to an adding means for adding the value of the weighted samples together.

2. A data processing circuit according to claim 1, wherein, at a given clock period, the first weighting means is arranged to weight the value of the data sample at its input by the first predetermined amount, and the second weighting means is arranged to weight the value of the data sample at its input by the second predetermined amount, and at the following clock period, the first weighting means is arranged to weight the value of the data sample at its input by the second predetermined amount, and the second weighting means is arranged to weight the value of the data sample at its input by the first predetermined amount.

3. A data processing circuit according to claim 1 or claim 2, wherein the first and second weighting means are arranged such that the first and second predetermined amounts, by which the data samples are weighted, are, respectively, one and three.

4. A data processing circuit according to any preceding claim, wherein the first and second weighting means are provided in the form of digital multipliers.

5. A data processing circuit according to any of claims 1 to 3, wherein any one of the first and second weighting means comprises: an adder arranged to receive the data samples and to weight the value of the data samples by the second predetermined amount; and a multiplexing means arranged to receive the data samples and the weighted output from the adder, the multiplexing means being arranged so as to output either one of (a) the value of the data samples, or (b) the value of the data samples weighted by the second predetermined amount.

6. A data processing circuit for use in a digital receiver, the data processing circuit comprising: an input for receiving data samples at a predetermined clock rate; sign modifying means connected to the input, the sign modifying means being arranged to (i) modify the sign of the value of two successive data samples, (ii) to leave the sign of the value of the subsequent two successive data samples unmodified, and (iii) to repeat steps (i) and (ii) for subsequent samples, the data samples being outputted on first and second data paths; wherein the first data path includes (a) delay means arranged such that data samples on the first data path are delayed by at least one clock period in relation to the same data samples on the second data path, and (b) first weighting means arranged to weight the value of the data samples by either one or three, and wherein the second data path includes second weighting means arranged to weight the value of the data samples by three when the data samples on the first data path are weighted by one, and by one when the data samples on the first data path are weighted by three, the first and second data paths being connected to an adding means for adding the value of the weighted samples together.

7. A data processing circuit according to any preceding claim, further comprising a control module for generating a first control signal for input to the sign modifying means thereby to control the performance of steps (i), (ii) and (iii), and to output second and third control signals for input to, respectively, the first and second weighting means thereby to control whether the value of the data samples is to be weighted by the first or second predetermined amount.

8. A data processing circuit for use in a digital receiver, the data processing circuit comprising: an input for receiving data samples at a predetermined clock rate; sign modifying means connected to the input, the sign modifying means being arranged to (i) modify the sign of the value of two successive data samples, (ii) to leave the sign of the value of the subsequent two successive data samples unmodified, and

(iii) to repeat steps (i) and (ii) for subsequent samples, the data samples being outputted on first and second data paths; wherein the first data path includes (a) delay means arranged such that data samples on the first path are delayed by at least one clock period in relation to the same data samples on the second path, and (b) first weighting means arranged to weight the value of the data samples by a first fixed amount, and wherein the second data path comprises a second weighting means arranged to weight the value of the data samples by a second fixed amount; the first and second data paths being connected to an adding means for adding the value of the weighted samples together.

9. A data processing circuit for use in a digital receiver, the data processing circuit comprising: an input arranged to receive data samples at a predetermined clock rate, and means arranged to demultiplex alternate data samples onto first and second data paths, the first and second data paths operating at a data rate substantially half that of the predetermined clock rate; first and second sign modifying means respectively connected to the first and second data paths, each sign modifying means being arranged to modify the sign of the value of every other data sample on the first and second data paths and to output the data samples onto first and second sub-paths of each data path; wherein the first sub-path of the first data path is arranged to weight the value of the data samples by a first amount, and wherein the second sub-path of the first data path (i) includes delay means for delaying the data samples by a predetermined number of clock period(s), and (ii) is arranged to weight the value of the data samples by a second amount; wherein the first sub-path of the second data path is arranged to weight the value of the data samples by the second amount, and wherein the second sub-path of the second data path (i) includes a delay means for delaying the data samples by the predetermined number of clock period(s), and (ii) is arranged to weight the value of the data samples by the first amount; the first and second sub-paths of the first and second data paths being connected to adding means for adding the value of the samples on the first and second sub-paths together.

10. A data processing circuit according to claim 9, wherein the first amount by which samples are weighted is three, and the second amount by which samples are weighted is one.

11. A data processing circuit for use in a digital receiver, the data processing circuit comprising: an input for receiving data samples at a predetermined clock rate; means arranged to effect a filtering operation on the data samples, the filtering means having predetermined coefficients; means arranged to down-convert the data samples by one-quarter of the clock rate; and means arranged to decimate the data samples by two.

12. A data processing circuit according to claim 11, wherein the predetermined coefficients are 1, 3, 3 and 1.

13. A integrated circuit (IC) package fabricated so as to include a data processing circuit according to any preceding claim.

14. A method of processing data in a digital receiver circuit, the method comprising: receiving an input signal and generating therefrom data samples at a predetermined clock rate; applying the data samples to a digital filter having predetermined coefficients; down-converting the frequency of the samples outputted from the digital filter by one-quarter of the clock rate; and decimating the samples, at the down-converted frequency, by two.

15. A method according to claim 14, wherein the predetermined coefficients are 1, 3, 3, and 1.