WO2003047099A3 - Digitally controlled pulse width adjusting circuit - Google Patents

Digitally controlled pulse width adjusting circuit Download PDF

Info

Publication number
WO2003047099A3
WO2003047099A3 PCT/CA2002/001439 CA0201439W WO03047099A3 WO 2003047099 A3 WO2003047099 A3 WO 2003047099A3 CA 0201439 W CA0201439 W CA 0201439W WO 03047099 A3 WO03047099 A3 WO 03047099A3
Authority
WO
WIPO (PCT)
Prior art keywords
pulse width
input pulse
adjusting circuit
width adjusting
digitally controlled
Prior art date
Application number
PCT/CA2002/001439
Other languages
French (fr)
Other versions
WO2003047099A2 (en
Inventor
Paul W Demone
Original Assignee
Mosaid Technologies Inc
Paul W Demone
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mosaid Technologies Inc, Paul W Demone filed Critical Mosaid Technologies Inc
Priority to AU2002328228A priority Critical patent/AU2002328228A1/en
Priority to DE60221893T priority patent/DE60221893T2/en
Priority to EP02762187A priority patent/EP1451930B1/en
Priority to KR1020047007866A priority patent/KR100937066B1/en
Publication of WO2003047099A2 publication Critical patent/WO2003047099A2/en
Publication of WO2003047099A3 publication Critical patent/WO2003047099A3/en

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01Details
    • H03K3/017Adjustment of width or dutycycle of pulses
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01Shaping pulses
    • H03K5/04Shaping pulses by increasing duration; by decreasing duration
    • H03K5/06Shaping pulses by increasing duration; by decreasing duration by the use of delay lines or other analogue delay elements

Abstract

A circuit selectively adjusts the width of an input pulse. The circuit comprises two stages. The first stage delays a leading edge of the input pulse with respect to a trailing edge of the input pulse in accordance with a first control input. The second stage delays the trailing edge of the input pulse with respect to the leading edge of the input pulse in accordance with a second control input. The input pulse width is adjusted in accordance with a difference between the delay of the leading edge and the delay of the trailing edge.
PCT/CA2002/001439 2001-11-23 2002-09-20 Digitally controlled pulse width adjusting circuit WO2003047099A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
AU2002328228A AU2002328228A1 (en) 2001-11-23 2002-09-20 Digitally controlled pulse width adjusting circuit
DE60221893T DE60221893T2 (en) 2001-11-23 2002-09-20 DIGITALLY CONTROLLED PULSE WIDTH SETTING CIRCUIT
EP02762187A EP1451930B1 (en) 2001-11-23 2002-09-20 Digitally controlled pulse width adjusting circuit
KR1020047007866A KR100937066B1 (en) 2001-11-23 2002-09-20 Digitally controlled pulse width adjusting circuit

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US33199001P 2001-11-23 2001-11-23
US60/331,990 2001-11-23
US10/084,620 US6538465B1 (en) 2001-11-23 2002-02-28 Digitally controlled pulse width adjusting circuit
US10/084,620 2002-02-28

Publications (2)

Publication Number Publication Date
WO2003047099A2 WO2003047099A2 (en) 2003-06-05
WO2003047099A3 true WO2003047099A3 (en) 2004-01-15

Family

ID=26771200

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CA2002/001439 WO2003047099A2 (en) 2001-11-23 2002-09-20 Digitally controlled pulse width adjusting circuit

Country Status (9)

Country Link
US (1) US6538465B1 (en)
EP (1) EP1451930B1 (en)
KR (1) KR100937066B1 (en)
CN (1) CN100477523C (en)
AT (1) ATE370549T1 (en)
AU (1) AU2002328228A1 (en)
DE (1) DE60221893T2 (en)
TW (1) TW567675B (en)
WO (1) WO2003047099A2 (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10337084B4 (en) * 2003-08-12 2006-01-12 Infineon Technologies Ag Device for generating standard-compliant signals
US7310752B2 (en) * 2003-09-12 2007-12-18 Micron Technology, Inc. System and method for on-board timing margin testing of memory modules
US7120743B2 (en) 2003-10-20 2006-10-10 Micron Technology, Inc. Arbitration system and method for memory responses in a hub-based memory system
US7453306B2 (en) * 2005-11-07 2008-11-18 Jds Uniphase Corporation Pulse shaping circuit
CN101465633B (en) * 2007-12-21 2012-05-23 瑞昱半导体股份有限公司 Device for generating signal
US7809521B1 (en) * 2008-02-29 2010-10-05 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Precise delay measurement through combinatorial logic
US8299833B2 (en) * 2010-06-09 2012-10-30 International Business Machines Corporation Programmable control clock circuit including scan mode
TWI532323B (en) 2013-08-14 2016-05-01 財團法人工業技術研究院 Digital pulse width generator and generation method thereof
JP7002378B2 (en) * 2018-03-19 2022-01-20 株式会社東芝 Digital time converter and information processing equipment
US10581382B2 (en) * 2018-06-07 2020-03-03 Texas Instruments Incorporated Pulse blanking in an amplifier
CN108599746B (en) * 2018-06-29 2024-04-05 长江存储科技有限责任公司 Self-adaptive pulse width adjusting circuit and flash memory
US11764760B1 (en) * 2022-04-12 2023-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Pulse width control apparatus and method

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5389828A (en) * 1991-08-29 1995-02-14 Nec Corporation Programmable delay generator for independently controlling leading and trailing edges of delayed pulse
EP0712204A2 (en) * 1994-10-25 1996-05-15 Mitsubishi Denki Kabushiki Kaisha Variable delay circuit, ring oscillator, and flip-flop circuit
US5703515A (en) * 1995-04-20 1997-12-30 Yokogawa Electric Corporation Timing generator for testing IC
US5821793A (en) * 1996-02-15 1998-10-13 Mitsubishi Denki Kabushiki Kaisha Variable delay circuit and a variable pulse width circuit
US5969555A (en) * 1997-04-25 1999-10-19 Advantest Corp. Pulse width forming circuit

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5638016A (en) * 1995-04-18 1997-06-10 Cyrix Corporation Adjustable duty cycle clock generator
US5764090A (en) * 1996-08-26 1998-06-09 United Microelectronics Corporation Write-control circuit for high-speed static random-access-memory (SRAM) devices
US6366115B1 (en) * 2001-02-21 2002-04-02 Analog Devices, Inc. Buffer circuit with rising and falling edge propagation delay correction and method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5389828A (en) * 1991-08-29 1995-02-14 Nec Corporation Programmable delay generator for independently controlling leading and trailing edges of delayed pulse
EP0712204A2 (en) * 1994-10-25 1996-05-15 Mitsubishi Denki Kabushiki Kaisha Variable delay circuit, ring oscillator, and flip-flop circuit
US5703515A (en) * 1995-04-20 1997-12-30 Yokogawa Electric Corporation Timing generator for testing IC
US5821793A (en) * 1996-02-15 1998-10-13 Mitsubishi Denki Kabushiki Kaisha Variable delay circuit and a variable pulse width circuit
US5969555A (en) * 1997-04-25 1999-10-19 Advantest Corp. Pulse width forming circuit

Also Published As

Publication number Publication date
CN1605155A (en) 2005-04-06
EP1451930B1 (en) 2007-08-15
EP1451930A2 (en) 2004-09-01
KR100937066B1 (en) 2010-01-15
DE60221893T2 (en) 2008-05-08
WO2003047099A2 (en) 2003-06-05
ATE370549T1 (en) 2007-09-15
CN100477523C (en) 2009-04-08
AU2002328228A1 (en) 2003-06-10
AU2002328228A8 (en) 2003-06-10
TW567675B (en) 2003-12-21
DE60221893D1 (en) 2007-09-27
US6538465B1 (en) 2003-03-25
KR20040053363A (en) 2004-06-23

Similar Documents

Publication Publication Date Title
WO2003047099A3 (en) Digitally controlled pulse width adjusting circuit
WO1999006845A3 (en) Impedance control circuit
WO2004027983A3 (en) Saturated power amplifier with selectable and variable output power levels
EP1189348A3 (en) Clock controlling method and circuit
AU6146398A (en) Synchronous clock generator including delay-locked loop
AU2003287661A1 (en) Direct conversion with variable amplitude lo signals
AU2001274989A1 (en) Adaptive control system having direct output feedback and related apparatuses and methods
AU2002306172A1 (en) Optimizing mergeability and datapath widths of data-flow-graphs
WO2002059385A3 (en) Laser peening of components of thin cross-section
WO2003032137A3 (en) Deskewing global clock skew using localized adjustable delay circuits
EP1408611A3 (en) Balanced programmable delay element
WO2004061635A3 (en) Adaptive power control
AU2003214221A1 (en) Variable delay compensation for data-dependent mismatch in characteristic of opposing devices of a sense amplifier
EP1150427A3 (en) Clock control circuit and method
CA2139005A1 (en) Feedforward amplifier for detecting distortion of an input signal
AU2002318128A1 (en) Control of transmission by adjustment of delay between amplitude and phase components
EP1447908A4 (en) Power amplifier
EP1291844A3 (en) Audio signal processor
EP1467343A3 (en) Capacitive load driving circuits and plasma display apparatuses with improved timing and reduced power consumption
MY124076A (en) Contour correction circuit and contour correction method.
CA2258939A1 (en) Pulse signal output circuit
EP0342671A3 (en) Agc delay on an integrated circuit
AU2003209431A1 (en) Group delay equalizer integrated with a wideband distributed amplifier monolithic microwave integrated circuit
WO2002013201A3 (en) Circuit and method for multi-phase alignment
EP1309082A3 (en) Feedforward amplifier with dual loop

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ OM PH PL PT RO RU SD SE SG SI SK SL TJ TM TN TR TT TZ UA UG US UZ VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR IE IT LU MC NL PT SE SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 1020047007866

Country of ref document: KR

WWE Wipo information: entry into national phase

Ref document number: 2002762187

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 2002825225X

Country of ref document: CN

WWP Wipo information: published in national office

Ref document number: 2002762187

Country of ref document: EP

NENP Non-entry into the national phase

Ref country code: JP

WWW Wipo information: withdrawn in national office

Ref document number: JP

WWG Wipo information: grant in national office

Ref document number: 2002762187

Country of ref document: EP