WO2003047109A3 - Bit-detection arrangement and apparatus for reproducing information - Google Patents

Bit-detection arrangement and apparatus for reproducing information Download PDF

Info

Publication number
WO2003047109A3
WO2003047109A3 PCT/IB2002/004486 IB0204486W WO03047109A3 WO 2003047109 A3 WO2003047109 A3 WO 2003047109A3 IB 0204486 W IB0204486 W IB 0204486W WO 03047109 A3 WO03047109 A3 WO 03047109A3
Authority
WO
WIPO (PCT)
Prior art keywords
signal
output
clock signal
output signal
analog
Prior art date
Application number
PCT/IB2002/004486
Other languages
French (fr)
Other versions
WO2003047109A2 (en
Inventor
Josephus A H M Kahlman
Original Assignee
Koninkl Philips Electronics Nv
Josephus A H M Kahlman
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv, Josephus A H M Kahlman filed Critical Koninkl Philips Electronics Nv
Priority to AU2002339626A priority Critical patent/AU2002339626A1/en
Priority to DE60209774T priority patent/DE60209774T2/en
Priority to US10/496,709 priority patent/US7430239B2/en
Priority to KR1020047007996A priority patent/KR100899180B1/en
Priority to EP02777675A priority patent/EP1459447B1/en
Priority to JP2003548408A priority patent/JP4339121B2/en
Publication of WO2003047109A2 publication Critical patent/WO2003047109A2/en
Publication of WO2003047109A3 publication Critical patent/WO2003047109A3/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0334—Processing of samples having at least three levels, e.g. soft decisions
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider

Abstract

Described is an invention relating to a bit-detection arrangement able to convert an analog signal (AS) into a digital signal (DS). The analog signal (AS) is fed to a quantizer (11). After the quantizer (11) the output signal S1 is fed to a phase detector PD1 (12). Also samples are taken of the output signal S1. The output signal PH2 of the phase detector PD1 (12) is dependent on the phase difference between the output signal S1 and the clock signal C2. If the frequency of the clock signal C2 is approximately equal to the frequency of the output signal S1 then the output signal PH2 of the phase detector PD1 (12) varies slowly. The analog to digital converter ADC (13) can therefore sample the output at a slow rate, dictated by the clock signal C1. The clock signal C1 is derived from C2 by dividing clock signal C2 by a factor n, whereby n is greater than one. To obtain the phase differences at clock periods of clock signal C2, the processed signal PrS of the analog to digital converter ADC (13) is interpolated. This can be done in different ways. A special embodiment comprises a digital phase locked loop DPLL (2) with discrete time oscillators. The obtained phase differences are used by the bit decision unit (3) to output the samples.
PCT/IB2002/004486 2001-11-30 2002-10-24 Bit-detection arrangement and apparatus for reproducing information WO2003047109A2 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
AU2002339626A AU2002339626A1 (en) 2001-11-30 2002-10-24 Bit-detection arrangement and apparatus for reproducing information
DE60209774T DE60209774T2 (en) 2001-11-30 2002-10-24 BITDETEKTIONSANORDNUNG AND DEVICE FOR PLAYING INFORMATION
US10/496,709 US7430239B2 (en) 2001-11-30 2002-10-24 Bit-detection arrangement and apparatus for reproducing information
KR1020047007996A KR100899180B1 (en) 2001-11-30 2002-10-24 Bit-detection arrangement and apparatus for reproducing information
EP02777675A EP1459447B1 (en) 2001-11-30 2002-10-24 Bit-detection arrangement and apparatus for reproducing information
JP2003548408A JP4339121B2 (en) 2001-11-30 2002-10-24 Bit detection configuration and device for reproducing information

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP01204622 2001-11-30
EP01204622.3 2001-11-30

Publications (2)

Publication Number Publication Date
WO2003047109A2 WO2003047109A2 (en) 2003-06-05
WO2003047109A3 true WO2003047109A3 (en) 2003-10-23

Family

ID=8181333

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2002/004486 WO2003047109A2 (en) 2001-11-30 2002-10-24 Bit-detection arrangement and apparatus for reproducing information

Country Status (9)

Country Link
US (1) US7430239B2 (en)
EP (1) EP1459447B1 (en)
JP (1) JP4339121B2 (en)
KR (1) KR100899180B1 (en)
CN (1) CN100417025C (en)
AT (1) ATE320110T1 (en)
AU (1) AU2002339626A1 (en)
DE (1) DE60209774T2 (en)
WO (1) WO2003047109A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006526924A (en) * 2003-06-04 2006-11-24 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ Bit detection device and information reproduction device
FR3042877A1 (en) * 2015-10-22 2017-04-28 Commissariat Energie Atomique METHOD AND DEVICE FOR DETERMINING THE PHASE OF A PERIODIC SIGNAL

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0342736A1 (en) * 1988-05-16 1989-11-23 Koninklijke Philips Electronics N.V. Phase-locked-loop cicuit and bit-detection arrangement comprising such a phase-locked-loop circuit
US6100661A (en) * 1997-12-22 2000-08-08 U.S. Philips Corporation Time-discrete phase-locked loop
US6134064A (en) * 1997-05-20 2000-10-17 Matsushita Electric Industrial Co., Ltd. Playback clock extracting apparatus

Family Cites Families (20)

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Publication number Priority date Publication date Assignee Title
NL8303561A (en) * 1983-10-17 1985-05-17 Philips Nv REGULATED OSCILLATOR SHIFT.
US4847876A (en) * 1986-12-31 1989-07-11 Raytheon Company Timing recovery scheme for burst communication systems
US5291500A (en) * 1990-05-22 1994-03-01 International Business Machines Corporation Eight-sample look-ahead for coded signal processing channels
US5195110A (en) * 1991-04-01 1993-03-16 Nec America, Inc. Clock recovery and decoder circuit for a CMI-encoded signal
DE69204144T2 (en) 1991-11-25 1996-03-21 Philips Electronics Nv Phase locked loop with frequency deviation detector and decoding circuit with such a phase locked loop.
JP3255179B2 (en) * 1992-02-14 2002-02-12 ソニー株式会社 Data detection device
US5559840A (en) * 1994-09-27 1996-09-24 Inernational Business Machines Corporation Digital timing recovery method and apparatus for a coded data channel
JPH08167841A (en) * 1994-12-13 1996-06-25 Pioneer Electron Corp Digital pll circuit
JP3360990B2 (en) * 1995-09-20 2003-01-07 株式会社東芝 Data reproduction processing device of disk recording / reproduction device
US6385257B1 (en) * 1997-01-21 2002-05-07 Sony Corporation Frequency demodulating circuit, optical disk apparatus thereof and preformating device
JP3094976B2 (en) * 1997-11-19 2000-10-03 日本電気株式会社 Synchronous circuit
GB2333214A (en) * 1998-01-09 1999-07-14 Mitel Semiconductor Ltd Data slicer
GB2333916B (en) 1998-01-09 2001-08-01 Plessey Semiconductors Ltd A phase detector
WO1999056283A2 (en) * 1998-04-28 1999-11-04 Koninklijke Philips Electronics N.V. Apparatus for reproducing information from a record carrier
DE10022486C1 (en) * 2000-05-09 2002-01-17 Infineon Technologies Ag Digital phase locked loop
DE10033109C2 (en) * 2000-07-07 2002-06-20 Infineon Technologies Ag Clock signal generator
US6990163B2 (en) * 2000-11-21 2006-01-24 Lsi Logic Corporation Apparatus and method for acquiring phase lock timing recovery in a partial response maximum likelihood (PRML) channel
US6876616B2 (en) * 2001-03-13 2005-04-05 Victor Company Of Japan, Ltd. Digital signal reproducing apparatus
US6496556B1 (en) * 2002-01-15 2002-12-17 Motorola, Inc. Step-down clock control and method for improving convergence for a digitally controlled self-calibrating VCO
US7124153B2 (en) * 2002-03-18 2006-10-17 Genesis Microchip Inc. Frequency converter and methods of use thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0342736A1 (en) * 1988-05-16 1989-11-23 Koninklijke Philips Electronics N.V. Phase-locked-loop cicuit and bit-detection arrangement comprising such a phase-locked-loop circuit
US6134064A (en) * 1997-05-20 2000-10-17 Matsushita Electric Industrial Co., Ltd. Playback clock extracting apparatus
US6100661A (en) * 1997-12-22 2000-08-08 U.S. Philips Corporation Time-discrete phase-locked loop

Also Published As

Publication number Publication date
DE60209774T2 (en) 2006-11-02
CN100417025C (en) 2008-09-03
EP1459447A2 (en) 2004-09-22
CN1636321A (en) 2005-07-06
EP1459447B1 (en) 2006-03-08
KR20040065566A (en) 2004-07-22
WO2003047109A2 (en) 2003-06-05
JP2005510936A (en) 2005-04-21
JP4339121B2 (en) 2009-10-07
ATE320110T1 (en) 2006-03-15
KR100899180B1 (en) 2009-05-27
DE60209774D1 (en) 2006-05-04
US7430239B2 (en) 2008-09-30
US20050018776A1 (en) 2005-01-27
AU2002339626A1 (en) 2003-06-10

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