WO2003052939A3 - Sigma delta a/d converter with firdac converter - Google Patents

Sigma delta a/d converter with firdac converter Download PDF

Info

Publication number
WO2003052939A3
WO2003052939A3 PCT/IB2002/004781 IB0204781W WO03052939A3 WO 2003052939 A3 WO2003052939 A3 WO 2003052939A3 IB 0204781 W IB0204781 W IB 0204781W WO 03052939 A3 WO03052939 A3 WO 03052939A3
Authority
WO
WIPO (PCT)
Prior art keywords
converter
firdac
sigma delta
bit
output signal
Prior art date
Application number
PCT/IB2002/004781
Other languages
French (fr)
Other versions
WO2003052939A2 (en
Inventor
Bas M Putter
Original Assignee
Koninkl Philips Electronics Nv
Bas M Putter
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv, Bas M Putter filed Critical Koninkl Philips Electronics Nv
Priority to AU2002348901A priority Critical patent/AU2002348901A1/en
Publication of WO2003052939A2 publication Critical patent/WO2003052939A2/en
Publication of WO2003052939A3 publication Critical patent/WO2003052939A3/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
    • H03M3/464—Details of the digital/analogue conversion in the feedback path
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M3/324—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement
    • H03M3/344—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by filtering other than the noise-shaping inherent to delta-sigma modulators, e.g. anti-aliasing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
    • H03M3/422—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only
    • H03M3/424—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only the quantiser being a multiple bit one

Abstract

The invention relates to a Sigma Delta A/D converter (2) for generating an N-bit digital output signal (4) on the basis of an analog input signal (6), comprising a control loop which comprises an N-bit A/D converter (2) for generating the N-bit digital output signal, wherein the Sigma Delta A/D converter (2) comprises a FIRDAC (22) in a feedback loop of the control loop, wherein the FIRDAC (22) comprises a multiple of 1-bit D/A converters which are connected in a delay line forming a FIR-filter, and wherein the FIRDAC (22) generates a first analog version (12) of the N-bit digital output signal (4).
PCT/IB2002/004781 2001-12-18 2002-11-13 Sigma delta a/d converter with firdac converter WO2003052939A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2002348901A AU2002348901A1 (en) 2001-12-18 2002-11-13 Sigma delta a/d converter with firdac converter

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP01204950.8 2001-12-18
EP01204950 2001-12-18

Publications (2)

Publication Number Publication Date
WO2003052939A2 WO2003052939A2 (en) 2003-06-26
WO2003052939A3 true WO2003052939A3 (en) 2004-01-22

Family

ID=8181457

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2002/004781 WO2003052939A2 (en) 2001-12-18 2002-11-13 Sigma delta a/d converter with firdac converter

Country Status (2)

Country Link
AU (1) AU2002348901A1 (en)
WO (1) WO2003052939A2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6842129B1 (en) * 2003-10-22 2005-01-11 Northrop Grumman Corporation Delta-sigma analog-to-digital converter
US7414557B2 (en) 2006-12-15 2008-08-19 Telefonaktiebolaget Lm Ericsson (Publ) Method and apparatus for feedback signal generation in sigma-delta analog-to-digital converters
US7852249B2 (en) 2009-02-27 2010-12-14 Freescale Semiconductor, Inc. Sigma-delta modulator with digitally filtered delay compensation
US7880654B2 (en) 2009-02-27 2011-02-01 Freescale Semiconductor, Inc. Continuous-time sigma-delta modulator with multiple feedback paths having independent delays

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0369630A2 (en) * 1988-11-15 1990-05-23 Sony Corporation Signal processing apparatus
EP0399738A2 (en) * 1989-05-26 1990-11-28 Gec-Marconi Limited Analogue to digital converter
EP0543618A2 (en) * 1991-11-20 1993-05-26 Gec-Marconi Limited Analogue-to-digital converter
US5323157A (en) * 1993-01-15 1994-06-21 Motorola, Inc. Sigma-delta digital-to-analog converter with reduced noise
EP0617516A1 (en) * 1993-03-22 1994-09-28 Motorola, Inc. Sigma-delta modulator with improved tone rejection and method therefor
US5777512A (en) * 1996-06-20 1998-07-07 Tripath Technology, Inc. Method and apparatus for oversampled, noise-shaping, mixed-signal processing
US6147634A (en) * 1998-12-15 2000-11-14 Sigmatel, Inc. Method and apparatus for digital to analog conversion with reduced noise

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0369630A2 (en) * 1988-11-15 1990-05-23 Sony Corporation Signal processing apparatus
EP0399738A2 (en) * 1989-05-26 1990-11-28 Gec-Marconi Limited Analogue to digital converter
EP0543618A2 (en) * 1991-11-20 1993-05-26 Gec-Marconi Limited Analogue-to-digital converter
US5323157A (en) * 1993-01-15 1994-06-21 Motorola, Inc. Sigma-delta digital-to-analog converter with reduced noise
EP0617516A1 (en) * 1993-03-22 1994-09-28 Motorola, Inc. Sigma-delta modulator with improved tone rejection and method therefor
US5777512A (en) * 1996-06-20 1998-07-07 Tripath Technology, Inc. Method and apparatus for oversampled, noise-shaping, mixed-signal processing
US6147634A (en) * 1998-12-15 2000-11-14 Sigmatel, Inc. Method and apparatus for digital to analog conversion with reduced noise

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
COLODRO F ET AL: "New class of multibit sigma-delta modulators using multirate architecture", ELECTRONICS LETTERS, IEE STEVENAGE, GB, vol. 36, no. 9, 27 April 2000 (2000-04-27), pages 783 - 784, XP006015164, ISSN: 0013-5194 *
HARRISON, J.; WESTE, N.: "A multi-bit sigma-delta ADC with an FIR DAC loop filter", INTERNET ARTICLE, Marsfield. Australia, XP002254943, Retrieved from the Internet <URL:elec.mq.edu.au/research/microelec/sigmadelta> [retrieved on 20030930] *
HAUSER M W: "PRINCIPLES OF OVERSAMPLING A/D CONVERSION", JOURNAL OF THE AUDIO ENGINEERING SOCIETY, AUDIO ENGINEERING SOCIETY. NEW YORK, US, vol. 39, no. 1/2, January 1991 (1991-01-01), pages 3 - 26, XP000202803, ISSN: 0004-7554 *

Also Published As

Publication number Publication date
AU2002348901A8 (en) 2003-06-30
WO2003052939A2 (en) 2003-06-26
AU2002348901A1 (en) 2003-06-30

Similar Documents

Publication Publication Date Title
WO2002023733A3 (en) Sigma-delta digital-to-analog converter
WO2002001726A3 (en) Communication device with configurable sigma-delta modulator
WO2003043199A3 (en) Optically sampled delta-sigma modulator
WO2003039006A3 (en) Incremental-delta analogue-to-digital conversion
TW200709542A (en) Control circuit of DC-DC converter and its control method
WO2002013391A3 (en) Second and higher order dynamic element matching in multibit digital to analog and analog to digital data converters
WO2002063777A3 (en) Delta sigma converter incorporating a multiplier
AU2003301779A8 (en) Converter, circuit and method for compensation of non-idealities in continuous time sigma delta converters
JPH0613905A (en) A/d converter
EP1193880A3 (en) A subranging sigma delta modulator
WO1999048202A3 (en) Converter with programmable gain control
WO2003065590A3 (en) Electronic circuit with a sigma delta a/d converter
AU2001296316A1 (en) Digital to analog converter employing sigma-delta loop and feedback dac model
WO2001011787A3 (en) Sigma-delta a/d converter
WO2003017496A3 (en) Multiplexed analog to digital converter
KR970072711A (en) 1-Bit A / D Converter Reduces Noise Components
WO2003039005A3 (en) High-resolution digital-to-analog converter
WO2004030031A3 (en) Integrated digital calibration circuit and digital to analog converter (dac)
AU2003224394A1 (en) Sigma delta a/d converter with pseudo flash converter
WO2003052939A3 (en) Sigma delta a/d converter with firdac converter
EP1398880A3 (en) Analog-digital conversion circuit
US6738002B2 (en) SD-ADC with digital dither signal processing
JP3303585B2 (en) Distributed feedback ΔΣ modulator
EP0866554A3 (en) Signal processors
EP1300951A3 (en) Delta-sigma analogue/digital converter

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ OM PH PL PT RO RU SC SD SE SG SI SK SL TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR IE IT LU MC NL PT SE SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP

WWW Wipo information: withdrawn in national office

Country of ref document: JP