WO2003063168A3 - Source side sensing scheme for virtual ground read of flash eprom array with adjacent bit precharge - Google Patents

Source side sensing scheme for virtual ground read of flash eprom array with adjacent bit precharge Download PDF

Info

Publication number
WO2003063168A3
WO2003063168A3 PCT/US2002/040823 US0240823W WO03063168A3 WO 2003063168 A3 WO2003063168 A3 WO 2003063168A3 US 0240823 W US0240823 W US 0240823W WO 03063168 A3 WO03063168 A3 WO 03063168A3
Authority
WO
WIPO (PCT)
Prior art keywords
bit line
cell
sensed
memory cell
source terminal
Prior art date
Application number
PCT/US2002/040823
Other languages
French (fr)
Other versions
WO2003063168A2 (en
Inventor
Pau-Ling Chen
Michael A Vanbuskirk
Yu Sun
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Priority to AU2002367515A priority Critical patent/AU2002367515A1/en
Priority to DE10297640T priority patent/DE10297640T5/en
Priority to KR10-2004-7010943A priority patent/KR20040075081A/en
Priority to JP2003562937A priority patent/JP2005516331A/en
Priority to GB0415355A priority patent/GB2400708B/en
Publication of WO2003063168A2 publication Critical patent/WO2003063168A2/en
Publication of WO2003063168A3 publication Critical patent/WO2003063168A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0491—Virtual ground arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits

Abstract

A system (600, 800) is disclosed for producing an indication (679) of the logical state of a flash memory cell (866) for virtual ground flash memory (640) operations. The system (600, 800) comprises a bit line precharge and hold circuit (660, 855) which is operable to apply and maintain a source terminal voltage (859) (e.g., about 0 volts, ground) to a bit line (850) associated with the source terminal (857) of a cell adjacent (856) to the cell which is sensed (866) during a read operation, wherein the applied source terminal voltage is substantially the same as the bit line virtual ground voltage (869) applied to the source terminal bit line (860) of the selected memory cell (866) to be sensed. The system (600, 800) also includes a drain bit line circuit (650, 875) operable to generate a drain terminal voltage (615, 815) for a drain terminal (868) of a selected memory cell (866) to be sensed. The system (600, 800) further includes a selective bit line decode circuit (652) which is operable to select the bit lines (860, 870) of a memory cell (866) to be sensed and the bit line (850) of an adjacent cell (856), and a core cell sensing circuit (695, 890) which is operable to sense a core cell sense current (675) at a bit line associated with a source terminal (867) of the selected memory cell (866) to be sensed during memory read operations, and produce an indication (679) of the flash memory cell logical state, which is substantially independent of charge sharing leakage current to an adjacent cell.
PCT/US2002/040823 2002-01-16 2002-12-17 Source side sensing scheme for virtual ground read of flash eprom array with adjacent bit precharge WO2003063168A2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
AU2002367515A AU2002367515A1 (en) 2002-01-16 2002-12-17 Source side sensing scheme for virtual ground read of flash eprom array with adjacent bit precharge
DE10297640T DE10297640T5 (en) 2002-01-16 2002-12-17 Source Side Scheme Source Voltage Sensing on Virtueller Ground Reading in a Flash Eprom Array with Precharge of the Neighbor Bit
KR10-2004-7010943A KR20040075081A (en) 2002-01-16 2002-12-17 Source side sensing scheme for virtual ground read of flash eprom array with adjacent bit precharge
JP2003562937A JP2005516331A (en) 2002-01-16 2002-12-17 Source-side sensing method for virtual ground readout of flash EPROM arrays with proximity bit precharge
GB0415355A GB2400708B (en) 2002-01-16 2002-12-17 Source side sensing scheme for virtual ground read of flash eprom array with adjacent bit precharge

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/050,257 2002-01-16
US10/050,257 US6529412B1 (en) 2002-01-16 2002-01-16 Source side sensing scheme for virtual ground read of flash eprom array with adjacent bit precharge

Publications (2)

Publication Number Publication Date
WO2003063168A2 WO2003063168A2 (en) 2003-07-31
WO2003063168A3 true WO2003063168A3 (en) 2003-11-27

Family

ID=21964237

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/040823 WO2003063168A2 (en) 2002-01-16 2002-12-17 Source side sensing scheme for virtual ground read of flash eprom array with adjacent bit precharge

Country Status (9)

Country Link
US (1) US6529412B1 (en)
JP (1) JP2005516331A (en)
KR (1) KR20040075081A (en)
CN (1) CN1615526A (en)
AU (1) AU2002367515A1 (en)
DE (1) DE10297640T5 (en)
GB (1) GB2400708B (en)
TW (1) TWI286753B (en)
WO (1) WO2003063168A2 (en)

Families Citing this family (86)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6768165B1 (en) * 1997-08-01 2004-07-27 Saifun Semiconductors Ltd. Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
US6917544B2 (en) 2002-07-10 2005-07-12 Saifun Semiconductors Ltd. Multiple use memory chip
US7136304B2 (en) 2002-10-29 2006-11-14 Saifun Semiconductor Ltd Method, system and circuit for programming a non-volatile memory array
US6963505B2 (en) 2002-10-29 2005-11-08 Aifun Semiconductors Ltd. Method circuit and system for determining a reference voltage
US6992932B2 (en) 2002-10-29 2006-01-31 Saifun Semiconductors Ltd Method circuit and system for read error detection in a non-volatile memory array
US6731542B1 (en) * 2002-12-05 2004-05-04 Advanced Micro Devices, Inc. Circuit for accurate memory read operations
US6967896B2 (en) * 2003-01-30 2005-11-22 Saifun Semiconductors Ltd Address scramble
US7178004B2 (en) 2003-01-31 2007-02-13 Yan Polansky Memory array programming circuit and a method for using the circuit
US6768679B1 (en) * 2003-02-10 2004-07-27 Advanced Micro Devices, Inc. Selection circuit for accurate memory read operations
US7142464B2 (en) * 2003-04-29 2006-11-28 Saifun Semiconductors Ltd. Apparatus and methods for multi-level sensing in a memory array
US7177199B2 (en) * 2003-10-20 2007-02-13 Sandisk Corporation Behavior based programming of non-volatile memory
US7057931B2 (en) * 2003-11-07 2006-06-06 Sandisk Corporation Flash memory programming using gate induced junction leakage current
CN100367231C (en) * 2004-01-05 2008-02-06 定智科技股份有限公司 Method and device for detecting use state of SATA external storage unit
CN100378869C (en) * 2004-01-15 2008-04-02 旺宏电子股份有限公司 Flash memory programmed verifying method
US6888758B1 (en) * 2004-01-21 2005-05-03 Sandisk Corporation Programming non-volatile memory
US7372730B2 (en) * 2004-01-26 2008-05-13 Sandisk Corporation Method of reading NAND memory to compensate for coupling between storage elements
US7002843B2 (en) * 2004-01-27 2006-02-21 Sandisk Corporation Variable current sinking for coarse/fine programming of non-volatile memory
US7139198B2 (en) * 2004-01-27 2006-11-21 Sandisk Corporation Efficient verification for coarse/fine programming of non-volatile memory
US7068539B2 (en) * 2004-01-27 2006-06-27 Sandisk Corporation Charge packet metering for coarse/fine programming of non-volatile memory
US7652930B2 (en) * 2004-04-01 2010-01-26 Saifun Semiconductors Ltd. Method, circuit and system for erasing one or more non-volatile memory cells
US7755938B2 (en) * 2004-04-19 2010-07-13 Saifun Semiconductors Ltd. Method for reading a memory array with neighbor effect cancellation
JP2006024345A (en) * 2004-04-28 2006-01-26 Matsushita Electric Ind Co Ltd Flash memory and program verifying method for the same
US7020026B2 (en) * 2004-05-05 2006-03-28 Sandisk Corporation Bitline governed approach for program control of non-volatile memory
US7023733B2 (en) * 2004-05-05 2006-04-04 Sandisk Corporation Boosting to control programming of non-volatile memory
US7095655B2 (en) * 2004-08-12 2006-08-22 Saifun Semiconductors Ltd. Dynamic matching of signal path and reference path for sensing
US20060068551A1 (en) * 2004-09-27 2006-03-30 Saifun Semiconductors, Ltd. Method for embedding NROM
US7638850B2 (en) 2004-10-14 2009-12-29 Saifun Semiconductors Ltd. Non-volatile memory structure and method of fabrication
TWI303825B (en) * 2004-11-12 2008-12-01 Macronix Int Co Ltd Memory device having a virtual ground array and methods using program algorithm to improve read margin loss
US7173859B2 (en) * 2004-11-16 2007-02-06 Sandisk Corporation Faster programming of higher level states in multi-level cell flash memory
US7092290B2 (en) * 2004-11-16 2006-08-15 Sandisk Corporation High speed programming system with reduced over programming
US7257025B2 (en) * 2004-12-09 2007-08-14 Saifun Semiconductors Ltd Method for reading non-volatile memory cells
US7397696B1 (en) * 2004-12-28 2008-07-08 Spansion Llc Current sensing architecture for high bitline voltage, rail to rail output swing and Vcc noise cancellation
US8053812B2 (en) 2005-03-17 2011-11-08 Spansion Israel Ltd Contact in planar NROM technology
US7099204B1 (en) 2005-03-23 2006-08-29 Spansion Llc Current sensing circuit with a current-compensated drain voltage regulation
US7327186B1 (en) 2005-05-24 2008-02-05 Spansion Llc Fast wide output range CMOS voltage reference
US8400841B2 (en) * 2005-06-15 2013-03-19 Spansion Israel Ltd. Device to program adjacent storage cells of different NROM cells
US7184313B2 (en) * 2005-06-17 2007-02-27 Saifun Semiconductors Ltd. Method circuit and system for compensating for temperature induced margin loss in non-volatile memory cells
US7786512B2 (en) 2005-07-18 2010-08-31 Saifun Semiconductors Ltd. Dense non-volatile memory array and method of fabrication
US20070036007A1 (en) * 2005-08-09 2007-02-15 Saifun Semiconductors, Ltd. Sticky bit buffer
US7668017B2 (en) 2005-08-17 2010-02-23 Saifun Semiconductors Ltd. Method of erasing non-volatile memory cells
KR100673694B1 (en) * 2005-10-10 2007-01-24 주식회사 하이닉스반도체 Semiconductor memory device with column decoder for consuming low power and read operation method of the same
US7286406B2 (en) * 2005-10-14 2007-10-23 Sandisk Corporation Method for controlled programming of non-volatile memory exhibiting bit line coupling
US7206235B1 (en) 2005-10-14 2007-04-17 Sandisk Corporation Apparatus for controlled programming of non-volatile memory exhibiting bit line coupling
US7301817B2 (en) * 2005-10-27 2007-11-27 Sandisk Corporation Method for programming of multi-state non-volatile memory using smart verify
US7366022B2 (en) * 2005-10-27 2008-04-29 Sandisk Corporation Apparatus for programming of multi-state non-volatile memory using smart verify
US7289348B2 (en) * 2005-11-10 2007-10-30 Sandisk Corporation Reverse coupling effect with timing information
US7218563B1 (en) * 2005-11-18 2007-05-15 Macronix International Co., Ltd. Method and apparatus for reading data from nonvolatile memory
JP4392404B2 (en) * 2005-12-07 2010-01-06 シャープ株式会社 Virtual ground type nonvolatile semiconductor memory device
US7808818B2 (en) 2006-01-12 2010-10-05 Saifun Semiconductors Ltd. Secondary injection for NROM
US8253452B2 (en) 2006-02-21 2012-08-28 Spansion Israel Ltd Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same
US7692961B2 (en) 2006-02-21 2010-04-06 Saifun Semiconductors Ltd. Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection
US7760554B2 (en) 2006-02-21 2010-07-20 Saifun Semiconductors Ltd. NROM non-volatile memory and mode of operation
US7436708B2 (en) * 2006-03-01 2008-10-14 Micron Technology, Inc. NAND memory device column charging
US20070255889A1 (en) * 2006-03-22 2007-11-01 Yoav Yogev Non-volatile memory device and method of operating the device
US7630253B2 (en) * 2006-04-05 2009-12-08 Spansion Llc Flash memory programming and verification with reduced leakage current
US7701779B2 (en) 2006-04-27 2010-04-20 Sajfun Semiconductors Ltd. Method for programming a reference cell
US20070253255A1 (en) * 2006-04-28 2007-11-01 Girolamo Gallo Memory device, method for sensing a current output from a selected memory cell and sensing circuit
US7486561B2 (en) * 2006-06-22 2009-02-03 Sandisk Corporation Method for non-real time reprogramming of non-volatile memory to achieve tighter distribution of threshold voltages
US7489549B2 (en) * 2006-06-22 2009-02-10 Sandisk Corporation System for non-real time reprogramming of non-volatile memory to achieve tighter distribution of threshold voltages
US7755961B2 (en) * 2006-07-07 2010-07-13 Rao G R Mohan Memories with selective precharge
DE602007008729D1 (en) * 2006-07-07 2010-10-07 S Aqua Semiconductor Llc STORAGE UNITS WITH FRONT END PRE-LOAD
US7724593B2 (en) * 2006-07-07 2010-05-25 Rao G R Mohan Memories with front end precharge
US7881121B2 (en) * 2006-09-25 2011-02-01 Macronix International Co., Ltd. Decoding method in an NROM flash memory array
US7450426B2 (en) * 2006-10-10 2008-11-11 Sandisk Corporation Systems utilizing variable program voltage increment values in non-volatile memory program operations
US7474561B2 (en) * 2006-10-10 2009-01-06 Sandisk Corporation Variable program voltage increment values in non-volatile memory program operations
US7551482B2 (en) * 2006-12-27 2009-06-23 Sandisk Corporation Method for programming with initial programming voltage based on trial
US7570520B2 (en) * 2006-12-27 2009-08-04 Sandisk Corporation Non-volatile storage system with initial programming voltage based on trial
US20080239599A1 (en) * 2007-04-01 2008-10-02 Yehuda Yizraeli Clamping Voltage Events Such As ESD
US7548462B2 (en) * 2007-06-29 2009-06-16 Macronix International Co., Ltd. Double programming methods of a multi-level-cell nonvolatile memory
US7508715B2 (en) * 2007-07-03 2009-03-24 Sandisk Corporation Coarse/fine program verification in non-volatile memory using different reference levels for improved sensing
US7599224B2 (en) * 2007-07-03 2009-10-06 Sandisk Corporation Systems for coarse/fine program verification in non-volatile memory using different reference levels for improved sensing
US7995409B2 (en) * 2007-10-16 2011-08-09 S. Aqua Semiconductor, Llc Memory with independent access and precharge
US8095853B2 (en) 2007-10-19 2012-01-10 S. Aqua Semiconductor Llc Digital memory with fine grain write operation
EP2308051A1 (en) * 2008-05-07 2011-04-13 Aplus Flash Technology, Inc. A nand based nmos nor flash memory cell/array and a method of forming same
US8064263B2 (en) * 2009-10-09 2011-11-22 Macronix International Co., Ltd. Current sink system for source-side sensing
TWI451420B (en) * 2010-01-20 2014-09-01 Macronix Int Co Ltd Memory program discharge circuit and method thereof
CN102280128B (en) * 2010-06-09 2014-11-19 上海华虹宏力半导体制造有限公司 Memory
US8659963B2 (en) 2012-01-05 2014-02-25 International Business Machines Corporation Enhanced power savings for memory arrays
CN103345934B (en) * 2013-06-03 2016-12-28 上海华虹宏力半导体制造有限公司 control gate voltage decoding circuit
US10103317B2 (en) 2015-01-05 2018-10-16 Inston, Inc. Systems and methods for implementing efficient magnetoelectric junctions
US10217798B2 (en) 2015-01-13 2019-02-26 Inston, Inc. Systems and methods for implementing select devices constructed from 2D materials
US9978931B2 (en) 2015-02-13 2018-05-22 Inston Inc. Systems and methods for implementing robust magnetoelectric junctions
KR102320830B1 (en) * 2015-09-24 2021-11-03 에스케이하이닉스 주식회사 Semiconductor memory device including three-dimensional array structure
CN109690675B (en) 2016-06-28 2022-11-04 赢世通股份有限公司 Novel word line pulse writing method applicable to magnetoelectric tunnel junction
US10861527B2 (en) 2017-06-27 2020-12-08 Inston, Inc. Systems and methods for optimizing magnetic torque and pulse shaping for reducing write error rate in magnetoelectric random access memory
US10460786B2 (en) 2017-06-27 2019-10-29 Inston, Inc. Systems and methods for reducing write error rate in magnetoelectric random access memory through pulse sharpening and reverse pulse schemes

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5027321A (en) * 1989-11-21 1991-06-25 Intel Corporation Apparatus and method for improved reading/programming of virtual ground EPROM arrays
US6134156A (en) * 1999-02-04 2000-10-17 Saifun Semiconductors Ltd. Method for initiating a retrieval procedure in virtual ground arrays

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2565104B2 (en) * 1993-08-13 1996-12-18 日本電気株式会社 Virtual ground type semiconductor memory device
US5517448A (en) * 1994-09-09 1996-05-14 United Microelectronics Corp. Bias circuit for virtual ground non-volatile memory array with bank selector
IT1302433B1 (en) 1998-08-13 2000-09-05 Texas Instruments Italia Spa READING CIRCUIT FOR FLASH MEMORY DEVICES WITH IMPROVED PROGRAMMING MARGINS AND OPERATING PROCEDURE
JP3410036B2 (en) 1999-02-03 2003-05-26 シャープ株式会社 Method of writing information to nonvolatile semiconductor memory device
US6201737B1 (en) 2000-01-28 2001-03-13 Advanced Micro Devices, Inc. Apparatus and method to characterize the threshold distribution in an NROM virtual ground array

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5027321A (en) * 1989-11-21 1991-06-25 Intel Corporation Apparatus and method for improved reading/programming of virtual ground EPROM arrays
US6134156A (en) * 1999-02-04 2000-10-17 Saifun Semiconductors Ltd. Method for initiating a retrieval procedure in virtual ground arrays

Also Published As

Publication number Publication date
WO2003063168A2 (en) 2003-07-31
GB2400708A (en) 2004-10-20
DE10297640T5 (en) 2005-01-05
GB0415355D0 (en) 2004-08-11
TWI286753B (en) 2007-09-11
US6529412B1 (en) 2003-03-04
KR20040075081A (en) 2004-08-26
TW200302484A (en) 2003-08-01
GB2400708B (en) 2005-08-17
CN1615526A (en) 2005-05-11
AU2002367515A1 (en) 2003-09-02
JP2005516331A (en) 2005-06-02

Similar Documents

Publication Publication Date Title
WO2003063168A3 (en) Source side sensing scheme for virtual ground read of flash eprom array with adjacent bit precharge
WO2003036651A3 (en) Drain side sensing scheme for virtual ground flash eprom array with adjacent bit charge and hold
TW376584B (en) Low voltage single supply CMOS electrically erasable read-only memory
AU2001291145A1 (en) Non-volatile memory cell array having discontinuous source and drain diffusions contacted by continuous bit line conductors and methods of forming
EP1256959A3 (en) Programming method for non-volatile semiconductor memory device comprising twin-memory cells
AU2002364167A1 (en) A programmable conductor random access memory and a method for writing thereto
TW200502962A (en) MRAM architecture for low power consumption and high selectivity
WO2000004555A3 (en) Storage cell system in which an electric resistance of a storage element represents an information unit and can be influenced by a magnetic field, and method for producing same
WO2003001530A3 (en) Erase method for dual bit virtual ground flash
TW348316B (en) Dynamic memory
JP2002245800A (en) Semiconductor memory and its measuring method of cell current
WO2007050679A3 (en) Current driven switched magnetic storage cells having improved read and write margins and magnetic memories using such cells
WO2003036650A3 (en) Method for erasing a memory cell
WO2005029499A3 (en) Low power programming technique for a floating body memory transistor, memory cell, and memory array
WO2005057586A3 (en) Nand memory array incorporating multiple series selection devices and method for operation of same
TW200501402A (en) Memory core and accessing method thereof
TW200620298A (en) Method of improving erase voltage distribution for a flash memory array having dummy wordlines
AU3001700A (en) Dual threshold voltage sram cell with bit line leakage control
WO2007078885A3 (en) Multi-level memory cell sensing
WO2002080182A3 (en) Method, apparatus, and system to enhance negative voltage switching
EP1031993A3 (en) One-chip microcomputer and method of refreshing its data
US20110085383A1 (en) Current sink system for source side sensing
TW201011753A (en) Memory and reading method thereof
GB2457408A (en) Sensing device for floating body cell memory and method thereof
WO2007062378A3 (en) Array source line (avss) controlled high voltage regulation for programming flash or ee array

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PH PL PT RO RU SD SE SG SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR IE IT LU MC NL PT SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

ENP Entry into the national phase

Ref document number: 0415355

Country of ref document: GB

Kind code of ref document: A

Free format text: PCT FILING DATE = 20021217

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
WWE Wipo information: entry into national phase

Ref document number: 1020047010943

Country of ref document: KR

WWE Wipo information: entry into national phase

Ref document number: 2003562937

Country of ref document: JP

Ref document number: 20028272609

Country of ref document: CN

RET De translation (de og part 6b)

Ref document number: 10297640

Country of ref document: DE

Date of ref document: 20050105

Kind code of ref document: P

WWE Wipo information: entry into national phase

Ref document number: 10297640

Country of ref document: DE

122 Ep: pct application non-entry in european phase
REG Reference to national code

Ref country code: DE

Ref legal event code: 8607