WO2003065147A3 - Method and program product for creating and maintaining self-contained design environment - Google Patents

Method and program product for creating and maintaining self-contained design environment Download PDF

Info

Publication number
WO2003065147A3
WO2003065147A3 PCT/US2003/001831 US0301831W WO03065147A3 WO 2003065147 A3 WO2003065147 A3 WO 2003065147A3 US 0301831 W US0301831 W US 0301831W WO 03065147 A3 WO03065147 A3 WO 03065147A3
Authority
WO
WIPO (PCT)
Prior art keywords
design
utility
creating
program product
embedded test
Prior art date
Application number
PCT/US2003/001831
Other languages
French (fr)
Other versions
WO2003065147A2 (en
Inventor
Brian John Pajak
Paul Price
Jean-Francois Cote
Luc Romain
Original Assignee
Logicvision Inc
Brian John Pajak
Paul Price
Jean-Francois Cote
Luc Romain
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Logicvision Inc, Brian John Pajak, Paul Price, Jean-Francois Cote, Luc Romain filed Critical Logicvision Inc
Priority to AU2003205269A priority Critical patent/AU2003205269A1/en
Publication of WO2003065147A2 publication Critical patent/WO2003065147A2/en
Publication of WO2003065147A3 publication Critical patent/WO2003065147A3/en

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequences by preliminary fault modelling, e.g. analysis, simulation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31704—Design for test; Design verification
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design

Abstract

An embedded test, chip design utility is an ease-of-use utility for assisting a circuit designer in quickly implementing a circuit embedded test design flow (70). Using the utility, a designer transforms a design netlist to include embedded test structures. The utility automatically builds a workspace containing a predetermined repository structure and design environment (212), generates control files (214) for executing design automation tools that operate within the design flow, and encapsulates the data so as to be self-contained and easily transferable to other design teams.
PCT/US2003/001831 2002-01-25 2003-01-23 Method and program product for creating and maintaining self-contained design environment WO2003065147A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003205269A AU2003205269A1 (en) 2002-01-25 2003-01-23 Method and program product for creating and maintaining self-contained design environment

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US35097902P 2002-01-25 2002-01-25
US60/350,979 2002-01-25

Publications (2)

Publication Number Publication Date
WO2003065147A2 WO2003065147A2 (en) 2003-08-07
WO2003065147A3 true WO2003065147A3 (en) 2004-01-22

Family

ID=27662987

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/001831 WO2003065147A2 (en) 2002-01-25 2003-01-23 Method and program product for creating and maintaining self-contained design environment

Country Status (2)

Country Link
AU (1) AU2003205269A1 (en)
WO (1) WO2003065147A2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100361122C (en) * 2004-11-29 2008-01-09 华为技术有限公司 Automatic designing method for ICT test conversion PCB
KR102004852B1 (en) * 2012-11-15 2019-07-29 삼성전자 주식회사 System for designing semiconductor package using computing system and method for the same, device for fabricating semiconductor package comprising the system, semiconductor package designed by the method
CN107729692B (en) * 2017-11-13 2021-07-20 嘉兴倚韦电子科技有限公司 Automatic physical verification method for semi-custom back-end design of integrated circuit

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5923675A (en) * 1997-02-20 1999-07-13 Teradyne, Inc. Semiconductor tester for testing devices with embedded memory
US6063132A (en) * 1998-06-26 2000-05-16 International Business Machines Corporation Method for verifying design rule checking software
US6182020B1 (en) * 1992-10-29 2001-01-30 Altera Corporation Design verification method for programmable logic design
US20020138813A1 (en) * 2001-03-20 2002-09-26 Cheehoe Teh System & method for performing design rule check
US6516456B1 (en) * 1997-01-27 2003-02-04 Unisys Corporation Method and apparatus for selectively viewing nets within a database editor tool

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6182020B1 (en) * 1992-10-29 2001-01-30 Altera Corporation Design verification method for programmable logic design
US6516456B1 (en) * 1997-01-27 2003-02-04 Unisys Corporation Method and apparatus for selectively viewing nets within a database editor tool
US5923675A (en) * 1997-02-20 1999-07-13 Teradyne, Inc. Semiconductor tester for testing devices with embedded memory
US6063132A (en) * 1998-06-26 2000-05-16 International Business Machines Corporation Method for verifying design rule checking software
US20020138813A1 (en) * 2001-03-20 2002-09-26 Cheehoe Teh System & method for performing design rule check

Also Published As

Publication number Publication date
WO2003065147A2 (en) 2003-08-07
AU2003205269A1 (en) 2003-09-02

Similar Documents

Publication Publication Date Title
WO2006124547A3 (en) Hierarchically structured data model used in industry
WO2003102760A3 (en) Customizing computer systems
WO2004075034A3 (en) Non main cpu/os based operational environment
WO2004029785A3 (en) Customizable drag and drop for industrial software applications
WO2005106625A3 (en) Selecting input/output devices to control power consumption of a computer system
WO2001095133A3 (en) A method of modelling a maintenance system
WO2004077258A3 (en) System and method for structuring distributed applications
WO2005034185A3 (en) System and method for on-tool semiconductor simulation
EP1420308A3 (en) Industrial control and monitoring method and system
WO2002069139A3 (en) System and method for generating and maintaining software code
WO2006041554A3 (en) Document processing and management approach to editing a document in a mark up language environment using undoable commands
WO2005034180A3 (en) System and method for on-tool semiconductor simulation
WO2005008504A8 (en) An executing automatically method using semiconductor storage devices
WO2006123040A3 (en) Method and device for generating a parametric model linked to a 3d geometry
WO2005029324A3 (en) Automated source code software programmer's manual generator
WO2005048153A3 (en) Modeling an event in a spreadsheet environment
WO2004040442A3 (en) Creating software applications
EP1564629A3 (en) Always ready computing device
WO2006062542A3 (en) System and method for automatically generating a tooling specification using a logical operations utility that can be used to generate a photomask order
WO2004077268A3 (en) System and method for dynamic data binding in distributed applications
WO2003065147A3 (en) Method and program product for creating and maintaining self-contained design environment
WO2002037268A3 (en) Dialogue flow interpreter development tool
CA2435252A1 (en) System and method for creating mark-making tools
WO2004027641A3 (en) Computer-aided selection method for a portion of a volume
Ledang Automatic translation from UML specifications to B

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ OM PH PL PT RO RU SC SD SE SG SK SL TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP

WWW Wipo information: withdrawn in national office

Country of ref document: JP