WO2003073679A1

WO2003073679A1 - Circuit and method used for data rate adaptation at a variable rate ratio including adjustable buffer memory partitioning

Info

Publication number: WO2003073679A1
Application number: PCT/DE2003/000517
Authority: WO
Inventors: Burkhard Becker; Michael Speth; Werner Hein; Maria Reich
Original assignee: Infineon Technologies Ag
Priority date: 2002-02-26
Filing date: 2003-02-19
Publication date: 2003-09-04
Also published as: DE10208129A1; DE10208129B4

Abstract

The invention relates to a circuit (10) used for data rate adaptation, which comprises a memory (11) that can be variably partitioned into an input and an output memory area (I; A). The circuit (10) further comprises a rate adaptation stage (12) for deleting bits from data read-out from the input memory area and/or for repeating said data at a variable rate adaptation factor. A control circuit (CL1) is used to adjust the partitioning ratio (14) of the memory (11) in accordance with the rate adaptation factor.

Description

description

Circuit and method for data rate adaptation with variable rate ratio with adjustable buffer partitioning

The invention relates to a circuit and a method for optimizing the use of buffer memory when adapting the rate of a data stream in systems with a variable rate ratio.

In radio communication systems, various types of messages (for example voice, image information or other data) are transmitted with the aid of electromagnetic waves via the air interface. For this purpose, a number of are on the transmitter side as well as on the receiver side

Take measures to prepare the data for transmission in a suitable manner. On the one hand, the level of error protection required for the service under consideration must be achieved, on the other hand, efficient and resource-saving transmission is desirable. Furthermore, the

Data is brought into the data formats specified by the standards and, if necessary, distributed over different available channels. In addition, third-generation mobile radio systems support the simultaneous, multiplexed transmission of several services per connection. All this makes it necessary to provide variable data rate adaptation in both the transmitter and the receiver.

Data rate adaptation is achieved by puncturing or repetition of bits in a data stream. It is known for puncturing (omitting a bit) or repetitive coding (repetitive coding) of data streams to provide circuits for data rate adaptation, as are shown schematically in FIG. 2 in relation to the prior art. The data stream to be changed in its data rate is transmitted via an input 1 Circuit supplied to an input buffer memory II, and an amount of data corresponding to the size of the input buffer memory II is stored therein. A rate adjustment stage Rl cyclically accesses the input buffer memory II and punctures or repeats the data read in the cycle. The punctured or repeat-coded data are output to an output buffer AI and the cycle is then run through again. If the input buffer memory II emptied or the

Output buffer memory AI is full, the cycle is aborted and the

Output buffer memory AI via an output 2. Subsequently, the input buffer memory II is rewritten by the data stream via input 1, and the process begins again.

If a high degree of rate variability is to be ensured, a disadvantage of the storage concept shown in FIG. 2 is that it is not efficient

Space usage is possible. If, for example, strong puncturing is set, (with identical memory sizes of the input and output buffer memories II and AI) the output buffer memory AI is only partially filled when the entire memory content of the input buffer memory II has already been processed. On the other hand, in the case of strong repeat coding, the input buffer memory II only needs to be filled to a small extent, because after the output buffer memory AI has been completely filled, the rate adjustment cycle is terminated prematurely. Since it is also possible to rewrite the input buffer memory II when the output buffer memory AI is subsequently read out, a large part of the memory area of the input buffer memory II remains unused in this case. The poor with high rate variability

Memory utilization in the prior art is disadvantageous because the memory size has a significant influence on the cost of an integrated circuit (IC).

The invention has for its object to provide a circuit for data rate adaptation to be implemented cost-effectively in an IC. Furthermore, the invention aims to provide a method for data rate adaptation which can be implemented inexpensively in an IC.

The problem underlying the invention is solved by the features of the independent claims. Advantageous developments of the invention are specified in the subclaims.

According to claim 1, the circuit for data rate adaptation according to the invention comprises an input memory for temporarily storing a data stream, a rate adaptation stage for puncturing and / or repeating data read from the input memory with a variable rate adaptation factor, and an output memory for temporarily storing and outputting the rate-modified data obtained from the rate adaptation stage. An essential aspect of the invention is that the input and the output memory are designed as memory areas of a single, variably partitionable memory, and that the circuit comprises means for setting the partition ratio of this memory as a function of the rate adjustment factor.

The fact that the memory can be partitioned means that the memory content of the memory can be distributed to the input or output memory areas as desired. With this variable storage space allocation, optimal utilization of the total available storage space can always be achieved. A particularly advantageous embodiment of the invention is characterized in that the means for adjusting the partition ratio of the memory adjusts this partition ratio from the initial storage area size to the incoming storage area size essentially in accordance with the rate adjustment factor K, which is the ratio of the output data rate to the input data rate. The rate adaptation factor K indicates the ratio of output data rate to input data rate. This ensures a storage space utilization with an optimal degree of utilization.

By means of monitoring the fill level of the input storage area and / or the output storage area, an overflow of the

Output storage area and / or an underflow of the input storage area can be reliably prevented. In this case, the means for monitoring the fill level preferably monitors the fill level of the output storage area when the rate adjustment factor K <1, while it monitors a

Rate adjustment factor K> 1 expediently monitors the fill level of the input storage area. Both measures can further increase storage space efficiency.

An advantageous embodiment of the invention is characterized in that the memory is designed as a dual-port memory. This means that two of the four accesses to the memory can be used simultaneously for reading and writing processes.

A further advantageous embodiment of the invention is characterized in that the circuit contains a further memory which is assigned to the first memory in parallel and has input and output memory areas partitioned in accordance with the first memory. Unless both stores as If dual-port memories are implemented, an effective four-port memory is represented, for example, by multiplexing the two memories.

The circuit according to the invention or the method according to the invention for data rate adaptation in the UMTS (Universal Mobile Telecommunications System) standard is used with particular advantage. In this standard, a large value range of the data rate adjustment factor is required.

The invention is described below using an example with reference to the drawing; in this show:

Fig. 1 shows a schematic diagram of a circuit for

Data rate adaptation in the reception and transmission path of a radio receiver;

2 shows a circuit for data rate adaptation according to the prior art;

Fig. 3 shows an example of a circuit for

Data rate adaptation according to the invention;

FIG. 4 shows a representation to explain the use of memory space with a varying rate adjustment factor; FIG. and

Fig. 5 is a flow chart to explain the operation of a circuit according to the invention.

1 shows a simplified representation of the received signal path RX and the transmitted signal path TX of a radio station. The radio station can be a mobile station as well as a base station of a radio system. In the received signal path RX, data signals transmitted via the air interface are received by an antenna 3 and converted in a suitable manner into a digital data signal. In addition to mixing down the received high-frequency signal into an intermediate or baseband frequency, analog-to-digital conversion and adaptive data detection, this step includes the assignment of the data received into the formats used, for example in data blocks. The further data processing includes one or more deinterleaving of the data stream and a channel decoding to remove the redundancy added to the data signal by the transmitter. The signal is then subjected to source decoding and fed to a message sink 4.

In transmission mode, reference 4 represents a message source. The data generated in the message source 4 are digitized, source-coded, channel-coded, interleaved and brought into suitable data formats. The data is then modulated and an analog high-frequency signal is generated, which is emitted via a transmission antenna 5.

Depending on the system design and the requirements specified by the standard, the signals in the RX signal path or in the TX signal path are adjusted at one or more points in both signal paths by means of a data rate adaptation circuit 10.

The data rate adaptation circuit 10 has the task of generating a specific number N _RX + ΔN _RX bits at the output from a specific number N _RX bits (RX signal path), or from a specific number N _τx bits at the input in the TX signal path the data rate _adaptation circuit to generate a certain number N _τx + ΔN _TX bits. Because in the invention a distinction between the RX signal path and the TX signal path is not required, the indices RX and TX are omitted below.

For the UMTS standard, the rate adjustment is described in the technical specifications 3GPP TS 25.212 V3.5.0 (2000-12) in chapter 4.2.7. On

Rate adjustment algorithm for generating puncturing and repetition patterns is described in section 4.2.7.5. specified specification. The cited passages are added to the content of this document by reference.

The rate adjustment factor K is defined by the following relationship:

K = (N + ΔN) / N Eq. 1

The output side size N + ΔN can e.g. be specified by a data format, e.g. as the number of bits within a data packet to be sent out in a certain period of time. In this case, the corresponding rate adjustment factor K must be determined from the number N of bits on the input side, and the compression or expansion of these N bits into N + ΔN bits must then be carried out.

That is, the rate matching factor K may vary from one data packet to another data packet, wherein a lower limit and an upper limit Kmax Kmin in ^'generally are known. Kmin <Kmax applies, whereby Kmin can be << 1 and Kmax >> 1. The range of variation can be large, e.g. Kmin = 1/511 and Kmax = 511.

The average rate adjustment factor r = ΔN / N per data packet is generally known. The absolute rate adjustment factor per bit within a data packet is only known within an interval [rmax, rmin]. 3 shows an exemplary embodiment of a data rate adaptation circuit 10 according to the invention. The circuit 10 comprises a first control unit CL1, a rewritable data memory 11, a rate adaptation stage 12 and a second control unit CL2. The entrance 1 of the

Data rate adaptation circuit 10 is connected to the first control unit CL1. This transfers the received data stream to the memory 11 via a data connection 13. The memory 11 is partitioned into an input memory area I and an output memory area A. The partition boundary is represented by the division mark marked with the reference number 14. Their position can be set by the first control unit CL1 via the control line 17. The output storage area A is connected to the output 2 of the data connection 15

Data rate adaptation circuit 10 in connection and can be read out via this data connection 15.

The rate adjustment takes place by means of the rate adjustment stage 12. For this purpose, X bits are read cyclically from the input memory area I via a data connection 16, subjected to a specific puncturing and / or repeat coding and then written into the output memory area A. The number X of bits received from the input memory area I per cycle is significantly smaller than the size of the memory 11, so that the cycle is generally run through many times before the input memory area I is emptied or the output memory area A is filled.

In order to prevent the output storage area A from overflowing, the second control unit CL2 continuously monitors the fill level of either the input storage area I or the output storage area A. The mode of operation of the data rate adaptation circuit 10 shown in FIG. 3 is explained in more detail below in connection with FIGS. 4 and 5.

A certain amount of data 20 consisting of Nl bits is to be transformed into a data amount 30 consisting of Nl + ΔN1 bits by rate adaptation. The data sets 20 and 30 are shown in FIG. 4 by columns, the heights of which reflect Nl and Nl + ΔN1. Since ΔN1 <0 follows Kl <1. First, the rate adjustment factor Kl is calculated in the first control unit CLl. The first control unit CL1 then sets the memory-internal partition limit 14 via the control line 17, that is to say it is determined how large the input storage area I and the output storage area A are (the sum of these two

Memory areas is predetermined by the size of the memory 11). The determination is made according to the relationship.

WA / WI * K. Gl

WA denotes the size of the output storage area A and WI denotes the size of the input storage area I. In the example shown in FIG. 4, Kl = 1/2. The input storage area I is therefore set twice as large as the output storage area A.

A first partial data stream 20.1 is subsequently written into the input storage area I. The number ^' of bits of the partial data stream 20.1 corresponds to the previously determined memory size of the input memory area I, so that it is completely (or at least almost completely) filled.

Subsequently, the partial data stream 20.1 is read out and punctured in cycles by the rate adjustment stage 12. For example, although X = 4, a cycle can only include a single bit (X = 1). The compressed, punctured partial data stream 30.1 generated from the partial data stream 20.1 is stored in the output storage area A. Due to the previously partitioning of the memory 11 in accordance with the rate adjustment factor K1, the two memory areas I and A are used optimally.

As soon as the second control unit CL2 determines that the first partial data stream 20.1 has been completely adapted to the rate (e.g. as a result of the determination that the output storage area A is filled or the input storage area I is completely empty), the cyclical processing is terminated. There is now read access to the data connection 15

Output memory area A, by means of which the compressed partial data stream 30.1 is read out. Furthermore, the next pending partial data stream 20.2 is written into the input memory area I by means of a write access via the data connection 13. The two accesses can take place simultaneously, provided that the memory 11 is a dual-port memory.

Subsequently, the partial data streams 20.2, 20.3 and 20.4 are transformed into the partial data streams 30.2, 30.3 and 30.4 in the manner already described. Optimal memory usage is always guaranteed. After the processing of the four partial data streams 20.1 to 20.4, the Nl bits of the data set 20 are processed with the rate adjustment factor Kl.

Immediately afterwards is the processing of the data set 40 consisting of N2 bits, which is to be expanded into the data set 50 consisting of N2 + ΔN2 bits. In this example, K2 = 6. After calculating the value K2 in the first control unit CL1, the internal partition limit 14 is shifted in such a way that the memory 11 is optimized for the execution of the new rate adjustment task. Consequently, WA / WI »6 is set according to equation 2. The expansion of the partial data streams 40.1 to 40.6 into the partial data streams 50.1 to 50.6 then already takes place in the described manner by cyclically executing a repeat coding on X bits each.

5 illustrates the described method steps using a flow chart. The dashed outer loop S1 represents the processing of the partial data streams 20.1 to 20.4 or 40.1 to 40.6, the inner loop S2 shows the cycle-wise operation of the rate adjustment stage 12.

The size of the memory 11 should be selected such that an optimal memory adaptation remains possible even with Kmin and Kmax. For this, the memory size must be larger than Kex: = max {Kmax + 1, Kmin ^"1 + 1}. In practice, a value W = 2 ^X * Q bits is selected for the memory size, where 2 ^{X is} the next higher power of two Number Kex is and Q denotes the word length of the memory.

It should be noted that K * X need not be an integer for K <1 or K> 1. Unless K * X is a whole

If there is a number, different cycle-rate adjustment factors occur in the individual cycles, which must meet the condition that an average rate adjustment with the required factor K is achieved.

It is also pointed out that, for example, for K <1, monitoring the output memory area A and for K> 1, monitoring the input memory area I are more favorable than the corresponding alternative options. For K <1, the number of cycles required by the rate adaptation circuit 10 to read out all the bits of the input storage area I (for example the bits of the partial data stream 20.1) is known, and in this case the second control unit CL2 provides information about the exact fill level of the output storage area A. reached after this number of cycles. Conversely, for K> 1, the number of cycles the rate adjustment circuit 10 takes to complete the Filling output storage area A completely, known, and in this case the second control unit CL2 informs about the exact filling level of the input storage area I.

Claims

claims

1. Circuit for data rate adjustment, with

an input memory for buffering data 5 of a data stream,

- A rate adjustment stage (12) for puncturing and / or repeating data read from the input memory with a variable rate adjustment factor (K), and

- An output memory for temporarily storing the data obtained from the 0 rate adjustment stage (12) and for outputting a rate-changed data stream, that is, because of that

- The input and the output memory are designed as memory areas (I; A) of a single, variably partitionable memory 5 (11), and

- The circuit comprises means (CLl) for adjusting the partition ratio of the memory (11) as a function of the rate adjustment factor (K).

0 2. Circuit according to claim 1, d a d u r c h g e k e n n z e i c h n e t that

- The means (CLl) for setting the partition ratio of the memory (11) to the partition ratio of the initial storage area size

25 Set the input storage area size essentially according to the rate adjustment factor (K), which is the ratio of the output data rate to the input data rate.

3. Circuit according to claim 1 or 2, 30 g e k e n n z e i c h n e t d u r c h

- Means (CL2) for monitoring the fill level of the input storage area (I) and / or the output storage area (A).

35th

4. Circuit after. Claim 3, characterized in that - The means (CL2) for monitoring the fill level with a rate adjustment factor K <1 monitor the fill level of the output storage area (A).

5. Circuit according to claim 3, d a d u r c h g e k e n n z e i c h n e t that

- The means (CL2) for monitoring the fill level with a rate adjustment factor K> 1 monitor the fill level of the input storage area (I).

6. Circuit according to one of the preceding claims, d a d u r c h g e k e n n z e i c h n e t that

- The memory (11) is designed as a dual-port memory.

7. Circuit according to one of the preceding claims, d a d u r c h g e k e n n z e i c h n e t that

- The circuit (10) contains a further memory which is assigned to the first memory (11) in parallel and which has partitioned input and output memory areas corresponding to the first memory (11).

8. Circuit according to one of the preceding claims, characterized in that the memory size has the value W = 2 ^X * Q bits, where 2 ^{X is} the next higher power of two to the number Kex and Q is an integer, and wherein Kex = max {Kmax + l, Kmin ^ + l}, where Kmax is a maximum rate ratio and Kmiri is a minimum rate ratio between which the rate adjustment factor can vary.

9. A method for rate adjustment of a data stream according to a variable rate adjustment factor (K), comprising the steps:

(a) Definition of a storage area partition (14) of a data store (11) in dependence on the rate adjustment factor (K) Input storage area (I) and an output storage area (A); (b) writing data of the data stream into the input storage area (I); (c) reading data from the input storage area (I), puncturing and / or repeating the data according to the rate adjustment factor (K) and writing the rate-changed data into the output storage area (A); and (d) outputting the rate-changed data from the output storage area (A).

10. The method of claim 9, d a d u r c h g e k e n n z e i c h n e t that the partition ratio (14) of initial storage area size to

Input storage area size is set substantially in accordance with the rate adjustment factor (K), which is the ratio of output data rate to input data rate.

11. The method according to claim 9 or 10, g e k e n n z e i c h n e t d u r c h the step parallel to step (c): (cl) monitoring the fill level of the input storage area (I) and / or the output storage area (A).

12. The method according to claim 11, characterized by the step: - Aborting the rate adjustment (step (c)) and outputting the rate-changed data (step (d)) as soon as the monitoring (step (cl)) threatens to overflow the output memory area (A ) is detected.

13. The method according to any one of claims 9 to .12, characterized in that step (c) is carried out cyclically, X data being read out from the input memory area (I), punctured and / or repeated in each cycle and the rate-changed data obtained in this way being written into the output memory area (A).

14. The method according to any one of claims 9 to 13, so that the method is used to carry out the rate adjustment prescribed in the UMTS standard in the uplink and / or downlink.