WO2003077450A1

WO2003077450A1 - Hardware support for sinr calculation in mobile radio receivers

Info

Publication number: WO2003077450A1
Application number: PCT/DE2003/000369
Authority: WO
Inventors: Burkhard Becker
Original assignee: Infineon Technologies Ag
Priority date: 2002-03-08
Filing date: 2003-02-07
Publication date: 2003-09-18
Also published as: DE10210323A1

Abstract

The invention relates to a circuit arrangement for the SINR calculation for mobile radio receivers, comprising a hardware module (1) for calculating the intermediate results of said SINR calculation. The SINR calculation is carried out by a processor (2) on the basis of the intermediate results that have been calculated in the hardware.

Description

description

Hardware support for SINR calculation in radio receivers

The invention relates to a circuit arrangement for SINR calculation for radio receivers, in particular in the field of mobile radio, and a method for calculating the SINR.

For CDMA (Code Division Multiple Access) mobile radio systems of the third generation, in particular UMTS (Universal Mobile Telecommunications System), the calculation of the ratio of useful power to interference power (SINR: Signal-to-Interference-plus-Noise Ratio) ) of particular importance in the receiver, since the power control of the CDMA system is carried out based on the SINR. For the SINR calculation, different operating or propagation modes (without and with antenna diversity, without and with closed control loop operation for power control) must be taken into account. In addition, the SINR may - e.g. with soft handover (SHO) - must be calculated for several cells. The cells to be considered at the SHO can in turn use different transmission modes. A further variability in the calculation of the SINR is that the pilot symbols on which the calculation is based (i.e. symbols which are known a priori to the receiver) can originate from different channels, e.g. the DPCH (Dedicated Physical Channel) channel, the CPICH (Common Pilot Channel) channel or a combination of several channels.

In view of these conditions, it is understandable that the greatest possible flexibility must be taken into account when calculating the SINR in the radio receiver.

So far, the various SINR values have been calculated in the firmware using a DSP (Digital Signal Processor). For this, the required data (dedicated or shared Pi lotsy bole, data symbols, channel coefficients) transmitted to the DSP. The transmission is path-specific, ie for each transmission path (occurring due to the multipath propagation in mobile radio systems), the data mentioned must be made available to the DSP separately, and appropriately combined and processed by the DSP. This causes a significant computing load on the DSP, which is then no longer available for other tasks and impairs the overall system behavior (power consumption, computing speed, etc.).

This should be illustrated using an example: if an SHO has to take into account six cells (i.e. six base stations) and four propagation paths per base station with a spreading factor of SF = 4, each time slot

6 * 4 * 16 (complex value) dedicated pilot symbols are transmitted to the DSP (since there are 16 pilot symbols per time slot for the interference power measurement in the DPCH channel). When determining the SINR using the common pilot symbols of the CPICH channel, 6 * 4 * 10 (complex-valued) common pilot symbols per time slot must be transmitted to and processed by the DSP (since there are 10 pilot symbols per time slot for measuring interference power in the CPICH channel are) .

In addition to the considerable computing load on the DSP, another disadvantage of this procedure is that due to the strict time requirements for the evaluation of the symbols and the response to the base station, a not insignificant peak load occurs on the DSP data buses. These peak loads for data transmission from and to the DSP must also be taken into account by increased hardware expenditure.

The invention is based on the object of providing a circuit alignment or a method which reduces the amount of data transmission and the computing load of a DSP in a radio receiver for the SINR Calculation enables. A sufficiently high flexibility in calculating the SINR should be maintained for practical use.

The problem underlying the invention is solved by the features of the independent claims.

Accordingly, the circuit arrangement according to the invention has a hardware module for calculating intermediate results for the SINR calculation. The actual SINR calculation is then carried out by a processor on the basis of the calculated intermediate results.

By calculating intermediate results in a hardware module, the data supplied to the processor is "pre-compressed". As a result, lower data transfer rates occur at the processor interface and the processor is relieved in terms of its computing power.

According to a particularly advantageous embodiment of the circuit arrangement according to the invention, at least some, but preferably all, of the intermediate results calculated by the hardware module are path-specific, cell-level-compressed variables for the SINR calculation. This means that the processor transmits only a little or no path-specific data to the processor, but rather mostly or exclusively data calculated as an intermediate result about a complete cell. In other words, the hardware-software interface is "behind" the path integration carried out by the hardware module, so that the processor only has to process cell-specific input data.

A further advantageous embodiment of the circuit arrangement according to the invention is characterized in that the hardware module is designed to provide intermediate results for each to calculate different operating or transmission modes. This means that the flexibility requirements for calculating the SINR are already taken into account by the design of the hardware module.

In this case, the processor is expediently programmed such that it carries out a combination of the suitable intermediate results (calculated by the hardware module) depending on the selected operating mode.

The hardware module for calculating the intermediate results preferably comprises a hardware data path with a plurality of selectively evaluable and / or selectively activatable / deactivatable hardware sections. This creates a programmability of the hardware module which, depending on the operating mode, makes it possible to evaluate and / or activate only those sections which are designed for the calculation of the intermediate results relevant in this operating mode and are currently required. The power consumption of the hardware module can be reduced by deactivating the remaining hardware sections.

On the input side, the hardware module preferably has two hardware sections arranged parallel to one another in the form of complex multipliers. This means that the hardware module is designed for time-division multiplex operation of upstream RAKE fingers of a RAKE receiver.

A further advantageous embodiment of the hardware module is further characterized in that at least some of the hardware sections are provided with selectively controllable accumulators at their outputs. These accumulators can be preloaded for each integration step with a temporary integration value and can be read out after each integration step in order to store the updated integration value for further calculation. The selectivity of the control enables the integration (accumulation) can be canceled after each integration step and temporarily saved as a temporary result for the next integration step.

A further advantageous embodiment of the hardware module is characterized in that it further comprises an input memory for data symbols, which is connected to the hardware data path, and an input memory for channel coefficients, which is also connected to the hardware data path. The two internal input memories decouple the hardware module from the upstream units (usually a RAKE receiver for the detection of the data symbols and a channel estimator for the determination of the channel coefficients). This input-side decoupling of the hardware module facilitates its programmability, as well as the timing and coordination of the computing processes in the upstream units and the hardware data path.

In a comparable manner, the provision of an internal output memory for storing the intermediate results calculated in the hardware module ensures decoupling on the output side between the hardware module and the processor. The memory content of the output memory is continuously updated by the hardware data path (depending on the operating mode) and read by the processor.

Further advantageous developments of the invention are specified in the subclaims.

The invention is explained in more detail below on the basis of an exemplary embodiment with reference to the drawing. In this show:

Figure 1 is a schematic representation of the general structure of a circuit arrangement according to the invention. 2 shows a representation of the architecture of an exemplary embodiment of a hardware module according to the invention;

FIG. 3 shows a circuit diagram of the hardware data path from FIG. 2; FIG.

FIG. 4A shows the circuit diagram from FIG. 3, in which activated circuit sections are shown hatched;

FIG. 4B shows the circuit diagram from FIG. 3, in which activated circuit sections are shown hatched;

FIG. 4C shows the circuit diagram from FIG. 3, in which activated circuit sections are shown hatched;

FIG. 4D shows the circuit diagram from FIG. 3, in which activated circuit sections are shown hatched;

5A shows the memory content of the output memory of the hardware module when calculating the SINR based on dedicated pilot symbols of the DPCH channel;

5B shows a representation of the memory content of the output memory of the hardware module when calculating the SINR based on common pilot symbols of the CPICH channel; and

5C shows the memory content of the output memory of the hardware module when calculating the SINR based on the common pilot symbols of the CPICH channel for STTD mode with closed control loop operation.

1, a circuit arrangement according to the invention for the SINR calculation has a hardware module 1 and a DSP 2. Intermediate results calculated by the hardware module 1 are transferred to the DSP 2 via a data connection 3. On the input side, 4 pilot symbols and possibly also data symbols as well as 5 channel coefficients are supplied to the hardware module 1 via a data connection. The pilot or. Data symbols are supplied by the Integrate & Dump unit of a RAKE receiver (not shown), the channel coefficients transmitted via the data link 5 are calculated in a channel estimator (also not shown).

The dash-dotted line 6 indicates the course of the interface between the hardware module 1 and the DSP 2, which is also referred to as "hardware-software interface". It is characterized in that, in contrast to the DSP, the hardware module 1 has no CPU (Central Processing Unit), i.e. no machine code processed. The programmability of the hardware module 1 is limited to influencing its activity by setting parameter values (parameterizability).

The hardware-software split explained here is characterized by the type or the degree of compression of the intermediate results that are transported via the data connection 3. As explained in more detail below, these intermediate results are preferably cell-specific intermediate result values without path-related information. On the basis of these intermediate result values, the calculation and output of the SINR is carried out by the DSP 2 via a data connection 7.

2 shows the structure of the hardware module 1. This has a hardware data path 10 as a central component. Furthermore, the hardware module 1 comprises a first, second and third buffer memory P1, P2 or P3, a first and second multiplexer MUX1 or MUX2, a demultiplexer DMUX and a state generator FSM (Finite State Machine).

The first buffer memory Pl are over the data connection

4 three types of symbols, namely dedicated pilot symbols (these are pilot symbols that are transmitted in a subscriber-specific channel), common pilot symbols (these are pilot symbols that are available to all participants via a common channel) and data symbols. To store these three symbol types, the first buffer memory P1 can be partitioned into three memory sections (not shown).

The second buffer memory P2 are over the data connection

5 channel coefficients supplied. The channel coefficients can be calculated either on the basis of the dedicated pilot symbols from the DPCH channel or on the basis of the common pilot symbols from the CPICH channel. Mixed forms are also conceivable.

Both the symbols and pilot symbols in the buffer memory P1 and the channel coefficients in the buffer memory P2 are path-specific data, i.e. the corresponding values are available in the buffer memories P1, P2 for each considered propagation path in a cell (and possibly for several cells).

Further data processing takes place according to a selected operating mode. The operating modes are normal mode (mode without transmitter-side antenna diversity) and STTD (Space Time Transmit Diversity) mode (mode with transmitter-side antenna diversity). Furthermore, a power control without control loop operation (so-called open-loop control; this is used with UMTS, for example when establishing a connection) and a power control with closed Control loop operation (so-called closed-loop control; in this the SINR results calculated in the receiver are communicated to the base station for controlling the transmission power).

The first multiplexer MUX1 is controlled via a control line 11 by the state generator FSM depending on the selected operating mode. This determines which of the types of symbols and channel coefficients mentioned are forwarded from the first multiplexer MUX1 to the demultiplexer DMUX. The demultiplexer DMUX distributes the received data values (real and complex part) to the inputs of the hardware data path 10.

Hardware data path 10 has a first group of eight

Inputs 12, a second group of eight inputs 13, and two further input pairs 14 and 15.

The hardware data path 10 is composed of three complex multipliers MULI, MUL2 and MUL3 and two squaring units SQR1 and SQR2. A detailed explanation of the structure of the hardware data path 10 is given later with reference to FIG. 3.

The individual sub-units MULI, MUL2, MUL3, SQR1 and SQR2 can be separately activated or deactivated via a control line 16, which starts from the state generator FSM. Furthermore, different control values for accumulators present in the sub-units MULI, MUL2, MUL3, SQR1 and SQR2 (see FIG. 3) can be programmed via the control line 16.

On the output side, the hardware data path 10 has output pairs 17, 18, 19 and 20 and individual outputs 21 and 22. These outputs are connected to the second multiplexer MUX2. The second multiplexer MUX2 is programmable via a control line 23, which starts from the state generator FSM. Via the control line 23, the state generator FSM determines which of the outputs 17 to 22 of the hardware data path 10 the third buffer memory P3 are forwarded. The control of the second multiplexer MUX2 is also dependent on the selected operating mode.

The data selected by the second multiplexer MUX2 are thus written into the third buffer memory P3 (output memory). The DSP 3 accesses the third buffer memory P3 via the data connection 7 and obtains path-independent intermediate results for the SINR calculation.

The following mathematical notation is introduced for a more detailed explanation of the functioning of the hardware module 1.

M: number of paths within cell Z, index m

K: Number of dedicated pilot symbols of the channel DPCH in the current time slot, index k L: Number of common pilot symbols of the channel CPICH, index 1 Z: Cell number hd _m : Channel coefficient, calculated from dedicated pilot symbols, for the path m, in normal mode lid- Λn, hd ² _m : channel coefficients, calculated from dedicated pilot symbols, for path m, in STTD mode, for transmit antennas 1 and 2 hc _m : channel coefficients, calculated from common pilot symbols, for path m, im Normal mode hc ¹ _,! ,, hc ² _m : channel coefficients, calculated from common pilot symbols, for the path m, in STTD mode, for the transmit antennas 1 and 2 d _m , k: received dedicated pilot symbols or data symbols of the path mc _m , ι: received common pilot symbols of the path m

The following intermediate results are calculated by the hardware data path 10 depending on the mode selected. The different modes are in the technical specification of UMTS 3GPP TS 25.211 V4.2.0 (2001-09) in Chapter 5, in particular

5.3.1.1 (open loop transmit diversity), 5.3.1.1.1 (STTD),

5.3.1.2 (closed loop transmit diversity), 5.3.2.1 (STTD for - DPCH) and 5.3.3.1 (CPICH - open and closed loop), are described and the mentioned passages are added to the content of this document by reference.

P denotes a pilot symbol sent at time k. Thus hd _m * p is the expected pilot symbol received, which was transmitted via path m at time k.

The expected energy of the received pilot symbol is

Case 1. Interim results for the SINR calculation based on the DPCH channel:

1.1 DPCH: normal mode

In the following it is assumed that all pilot symbols have the same transmitted energy,

P P

that is, I p _k | 2 is not a function of k. So is

Then:

SD ^xp is the expected signal energy, integrated over all pilot symbols (K) and over all paths (M) within cell Z.

SDmeas m, l *

SD is the measured signal energy, integrated across all

Pilot symbols (K) and over all paths (M) within cell Z.

1.2 DPCH: STTD mode or generally 2-antenna mode

In the following it is assumed that

i.e. that the transmitted energy of a pilot symbol is not a function of k and not a function of the antenna number.

Then:

2

SDexp K fadj + d 'm = l

M K

SD ₂ ^meaS = ∑ ∑ | d _m , _k | m = lk = l

SD ™ ⁶³¹³ is the measured signal energy, integrated over all pilot symbols (K) and over all paths (M) within cell Z. Case 2. Interim results for the SINR calculation based on the CPICH channel:

2.1. CPICH: normal mode

In the following it is assumed that

I | 2 I | 2

P _k ⁼ | P | 'where Pk are the dedicated pilot symbols, ie the transmitted energy of a pilot symbol is not a function of k.

It is also believed that

= | p | , where pi are the common pilot symbols, i.e. the transmitted energy of a pilot symbol is not a function of 1.

If a channel coefficient is now available for each path m on the basis of a channel estimate based on common pilot symbols, the expected signal energy can be determined over all paths m and pilots k using the RAKE combination:

hc * hd. Pk = 1

Then:

SC ^xp is the expected signal energy, integrated over all dedicated pilot symbols (K) and over all paths (M) within cell Z. q itieas, com _ ' ¹ V " ¹ m, lm = ll = l

g ^meas , ^com ^ _st ^ _e g _{measured signal} energy of the common pilot symbols, integrated over all common pilot symbols (L) and over all paths (M) within the cell Z.

MLM _sc exp, co _{m = ∑ ∑} | _hCm | 2 | _pι f --- _{∑ L} * | _hCm | 2 _{| p | 2} m = ll = lm = l

_sc ^exp, ^com ^ _st ^ _{e expect} t _e te _S ignalenergie of the common pilot symbols, integrated over all common pilot symbols (L) and over all paths (M) within the cell Z.

Instead of the expressions sc ^eas ' ^com and SC ^{xp, com} , which are calculated on the basis of the common pilot symbols, SD ₂ ^βas or SD ^xp can also be calculated on the basis of dedicated pilot symbols. There is no difference from a hardware perspective. It is only necessary to calculate a normalization factor NC ^xp ' ^norm on the basis of the common pilot symbols, since the normalization factor is due to the RAKE combination.

The normalization factor for RAKE-Combining Nc ^xp ' ^norm is proportional to SC ^{xp, com} .

2.2 CPICH: STTD mode

In the following it is assumed that

I | p _k || 2 = t [p || 2, ie the energy transmitted by a dedicated pilot symbol is not a function of k;

PnJ = | p | , ie the transmitted energy of a common pilot symbol is not a function of 1; and that vl = p and PΪ P ² ι p, ie the sent

Energies of the dedicated or common pilot symbols are not functions of the antenna number.

We use the formula to calculate the expected signal power

^M f _*

SC ^xp (RAKE-Combining) = ∑ ∑ h ^C m * ^hd m * Pk + h ^C hd '> lk = l and assume the following simplification of this formula:

SC ^x is the expected signal energy, integrated over all dedicated pilot symbols (K) and over all paths (M) within cell Z.

_p

_sc ^ ^eas ' ^co -j_ _st 3ι _e measured signal energy of the common pilot symbols, integrated over all common pilot symbols (L) and over all paths (M) within the cell Z.

_sc ^eχp , ^com ^ _st ^ _{e expected} signal _{energy of} the common pilot symbols, integrated over all common pilot symbols (L) and over all paths (M) within the cell Z. The expected signal energy SC ^{xp of} the dedicated pilot symbols must be standardized due to the RAKE combination.

The normalization factor Nc ^χP ' ^norm results from the sum of the squares of the amounts of the channel coefficients of the common pilot symbols over all paths m and is therefore proportional to _c exp, com

Instead of the expressions sc ™ ⁶³⁸ ^'00 " ¹ and SC ^{xp, om} , which are calculated on the basis of the common pilot symbols, SD ™ ^®618 or SD ^xp can also be calculated here on the basis of dedicated pilot symbols. The same applies Statements as in case 2.1.

Case 3. Intermediate results for SINR calculation for closed control loop operation on the basis of the CPICH channel:

The procedure is analogous to case 2. Only the channel coefficients of the common pilot symbols are multiplied by the cell-specific weight factors wl and w2.

_sc ^meas , ^com ^ _s ^ ^ _e g _{e essen} signal _{energy of} the common pilot symbols, integrated over all common pilot symbols (L) and over all paths (M) within the cell Z.

_sc exp, com _{= ∑ L} * 2 hc _m + hc ² IPI ² m = l J

_sc ^{eχp, com} ^ _st ^ _{e expect} t _e th signal power of the common pilot symbols, integrated over all common pilot symbols (L) and over all paths (M) within the cell Z. Instead of the expressions sC ₂ ^eas ' ^com and SC | ^xp ' ^com , which are calculated on the basis of the common pilot symbols, can also be calculated here SD ₂ ^βas or SD ^xp on the basis of dedicated pilot symbols. The same statements apply as in case 2.1.

sc ^p = m * hc _r * hdi, + w,

SC ^xp is the expected signal energy, integrated over all paths (M) and over all dedicated pilot symbols K within cell Z. Here, wi and w denote ₂ weighting factors for the transmission power of the two transmitter-side antennas of cell Z. These are used in the receiver for the calculation of the SINR.

NCexp, norm = £ ^' + W * hc!

NC ^{<3χp, norm} ^ _s j ^. _E ^ _{he ar} ended signal energy normalization, integrated over all paths (M) within the cell Z.

When the formulas were created, the calculation of channel coefficients, which allow simplifications for different operating modes, was not dealt with. Only a general equation structure should be worked out here, on the basis of which the structure of the hardware data path can then be understood, which will be discussed in more detail below.

3 shows the structure of the hardware data path 10. The hardware data path 10 consists of interconnected ones

Standard arithmetic elements, which are designated in FIG. 3 with the following reference numerals:

Mzi: multiplier of the zth subunit with index i Azi: adder of the zth subunit with index i ACzi: accumulator of the zth subunit with index i MUXzi: multiplexer of the zth subunit with index i SQzi: squarer of the zth subunit with index i

z = 1 denotes the first complex multiplier MULI, z = 2 denotes the second complex multiplier MUL2, z = 3 denotes the third complex multiplier MUL3, z = 4 denotes the first squaring unit SQR1 and __ = 5 denotes the second squaring SQR2 unit.

Furthermore, the hardware data path 10 comprises two accumulators AC1 and AC2 and two combined adders and registers A / Rl and A / R2, which are not associated with any of the subunits mentioned.

The first and second complex multipliers MULI and MUL2 receive the first group 12 and the second group 13 of inputs, respectively. Inputs for real variables are marked with r and inputs for imaginary variables with i. The first and second input pairs 14 and 15 are fed to the third complex multiplier MUL3. The first multiplier MULI provides the output pair 17 and the second multiplier MUL2 provides the output pair 20. The further outputs 21 and 22 are provided by the squaring units SQR1 and SQR2. The connection pairs 18 and 19 represent inputs of the squaring units SQR1 and SQR2.

The multipliers Mzi and adders Azi, z = 1, 2, 3, the complex multipliers MULI, MUL2 and MUL3 each carry out a multiplication of two complex data values, which ^{, as is} known, comprises four real multiplications and two additions. The combined adders and registers A / Rl and A / R2 carry out an addition of the outputs of the adders All and A21 or AI2 and A22. Internal inputs of the third complex multiplier MUL3 are with the summed outputs of the first and second complex multipliers MULI and MUL2 (ie connected to the outputs of A / Rl and A / R2). In this way, the sum of two triple complex multiplications can be calculated.

Each complex multiplier MULI, MUL2 and MUL3 comprises two accumulators ACzl and ACz2, which integrate the multiplication results over a predetermined number of multiplications.

The first complex squaring unit SQRI is connected on the input side directly to the accumulated output of the sum of the two complex multipliers MULI and MUL2 (the accumulation is accomplished by the accumulators AC1 and AC2). The second complex squaring unit SQR2 is connected directly to the accumulated output of the third complex multiplier MUL3. Both squaring units SQR1 and SQR2 contain integrated accumulators AC41 and AC51, which add up the squared result values over a predefinable number of loops.

For the calculation of the SINR, the interference plus noise power and the expected signal power must be determined. The following two mathematical expressions indicate the interference plus noise power in the different modes based on the dedicated pilot symbols (from the DPCH channel).

MKM p tnal = α ∑ ∑ | d _{m, k} | ² - ß ∑ K * | hd _m | ² = α '* SDr ^aS - ß' * SD ^ m = lk = lm = l

(1)

M K „2 M

P ² Z, STTD = γ ∑ ∑ | d _{m | k} - δ∑ ∑ K * hdj. = γ '* SDΓ "- δ' * SD _Z m = lk = lj = lm = l

(2)

Here, p ² z, normal _denotes the interference plus noise power in normal mode and P ² Z, _STTD the interference plus noise Performance in the STTD mode with two transmit antennas or generally in the 2-antenna mode.

In the equations above, these expressions were calculated based on dedicated pilot symbols. If the calculation is to be based on the common pilot symbols (from the CPICH channel), the quantities d _m , _k , hd ¹ ,,,, hd ² _m , hd _{m are given} by the quantities d _m , ι, hc ¹ - _^ , hc ² _m , hc _m to replace.

The expected signal powers of the dedicated pilot symbols are calculated in the two modes according to the following equations:

S ² z, _nθ rmal = 8 * K∑ | hd _m | = ε '* SD§ ^Xp (3) m = l

S ² Z, STTD = η * K∑ hd + hd = η '* SD ^xp (4) m = l

S ² _Z , nor _m a _l denotes the expected signal power in normal mode and S ² _Z , _STTD denotes the expected signal power in STTD mode with two transmit antennas. The quantities mentioned are calculated in the above equations on the basis of the dedicated pilot symbols (from the DPCH channel). When calculating these quantities on the basis of the common pilot symbols (from the CPICH channel), the values hd ¹ ,! -., Hd ² _m , hd _{m are given} by the values hc ¹ !! ,, hc ² _m , hc _m to replace.

The equations for calculating the expected signal power of the dedicated pilot symbols using the CPICH channel in the two modes are given below.

S z, normal - * hd _r = μ (5)

.2

SZ, STTD = λ ∑ [h _C ; ^* * hd; + hc ² _m ^* * hd: λ '* SC ^p (6)

S ² _Z , no _rm a _l denotes the expected signal power of the dedicated pilot symbols in normal mode and S ² _Z , _S T _TD denotes the expected signal power of the dedicated pilot symbols in STTD mode (calculated in each case on the basis of channel coefficients from the DPCH channel and the CPICH channel).

Furthermore, the value χ * NC ex, norm mi | hc _m | (with an antenna) or. m = l ^with X ∑ | c + ιhcm (in 2-antenna mode) calculated. m = l

In the case of the STTD mode with control loop operation, the equation for calculating the expected signal power S ² _Z , ST _{TD of} the dedicated pilot symbols using the CPICH channel is as follows:

SZ, STTD = * hc- „* hdt +, * hc * hd = φ * sc ^xp (7)

Furthermore, the value τ * _N c _z ^exp ' ^{norm is} calculated for the normalization of the expected signal power:

Σ w-, hc + w ₂ * hc _m = τ * NC | ^xp ' ^norm (8) m = l

In the above equations, the quantities α, β, γ, δ, ε, η, μ, λ, χ, φ, τ, constants, the quantities ß ', δ', ε ', η', μ ', λ' , φ 'result from the above definitions.

The SINR is defined as the quotient of the useful power to interference power per chip, the useful power being proportional to the expected signal power and the interference power device is to be calculated from the signal plus interference power. It is sometimes referred to as SIR in the literature. If only dedicated (and not common) pilot symbols are considered, this applies to normal mode

2/2

SINR = S z, normal / p Z, normal

and for the antenna diversity mode STTD

In the following, the calculation of some of the intermediate results specified above is explained in more detail using the hardware data path 10:

FIG. 4A shows a representation of the circuit diagram from FIG. 3, the circuit sections used for calculating equation (2) being indicated by hatching. It becomes clear that only the subunits MULI and MUL2 have to be activated to calculate the individual terms. In processor 2, only the two values available at output pair 20 then have to be weighted with the relevant constants, added and subtracted from the value at the left output of output pair 17.

If the calculation is to be carried out on the basis of the common pilot symbols instead of on the basis of the dedicated pilot symbols, the input data are simply replaced by d _{m / 1} and c; , hc; replaced.

It can be seen immediately that the calculation of an integration step in the loops k = 1, ..., K, 1 = 1, ..., L and m = 1, ..., M takes only one cycle (cycle) ,

The accumulators ACH, AC21 and AC22 used here are loaded with the results of the last integration step, integrate the currently calculated value and can then integrate the same intermediate SINR value of the same cell or another intermediate SINR value of the same cell or generally another intermediate SINR value of another cell in the next cycle. The information as to which SINR intermediate values rather which cells are accumulated is given by the assignment of the virtual time-multiplexed RAKE fingers to the paths of the cells and by the operating modes of the cells. Each virtual RAKE finger supplies in time-division multiplex data or pilot symbols or channel coefficients that are required to integrate the intermediate SINR values.

The temporal assignment of the virtual time-multiplexed RAKE fingers to the paths of a cell and thus the chronological order of the calculation of the SINR intermediate values is arbitrary.

FIG. 4B shows a circuit diagram representation corresponding to FIG. 4A for the calculation of equation (6). The two complex multipliers MULI and MUL2, the combined adders and registers A / Rl and A / R2, the accumulators AC1 and AC2 and the squaring unit SQRl (but without the result-side accumulation of results by AC41) are activated. As the equation terms drawn in FIG. 4B illustrate, in the two input-side complex multipliers MULT1 and MULT2 the complex products hc; * hd; or hc 2 _m * * hd2 _m . In processor 2, only the value supplied at output 21 is multiplied by the constant λ.

4A and 4B show that the calculation of an integration step of intermediate values of the SINR calculation (equations (6) and (2)) only takes 2 cycles even in the case of STTD coding with common pilot symbols (pipelining and latency times are not taken into account ).

The calculation of an integration step of equation (2) takes place in cycle 1. In cycle 2, the calculation of an integer ration step of equation (6) started. A latency of 2 cycles through the pipelining is to be assumed.

After 2 cycles plus the latency, an integration step of all SINR intermediate values is calculated for the two cases 1 and 2 above: SD ^ ^eas , SD ^xp or _S c ^eas ' ^com , g exp, com ,,, -, exp, norm σr; ^eχ P

4C shows the circuit diagram representation for calculating equation (7). The input-side complex multipliers MULI and MUL2 are activated and calculate the products w _x * hc _m and w ₂ * hc _m in 2 cycles. In the first cycle, the first multiplier MULI calculates the value vr _x * hc _m while the second multiplier MUL2 receives the values 0 on the input side and calculates the value 0. The procedure is reversed in the second cycle, that is to say the first multiplier MULI calculates the value 0 and the second multiplier MUL2 gives the value w ₂ * hc; out . The products w ^ * hc; * hd; and vr ^* ₂ * hc * d; are then formed in successive cycles in the third complex multiplier MUL3. The result of the equation (7) is available at the output 22 of the second squaring unit SQR2 (again without result accumulation by AC51) and only has to be multiplied in the processor 2 by the constant φ.

Finally, FIG. 4D shows the activated circuit areas of the circuit diagram of FIG. 3 for the calculation of equation (8). The two complex multipliers MULI and MUL2 on the input side and the two combined adders and registers A / Rl and A / R2 carry out the same calculations as in the example shown in FIG. 4C. The further calculation path differs, however, in that it is not the third complex multiplier MULT3 that is activated, but rather that in the output-side accumulator AC41 of the first squaring unit SQR1, results are accumulated over M loops. Except for the Mul- tication with the constant τ, the normalization value to be determined is generated by the hardware data path 10.

Comparing FIGS. 4C and 4D, it can be seen that an integration step of equations (7) and (8) can be carried out in parallel with the same input values within 2 cycles (pipelining and latency times are not taken into account here).

The results of FIG. 4A result in a calculation time of 3 cycles for each integration step of all SINR components. The pending integration steps are performed as soon as a RAKE finger provides another demodulated data or pilot symbol received on a path of the same cell or a channel coefficient of a path of the same cell.

For all intermediate results output by the hardware data path 10, the integration via the M paths of the cell Z under consideration has already been carried out. The values transferred to processor 2 are therefore path-non-specific.

The memory allocation of the output-side buffer memory P3 depends on the activation of the second multiplexer MUX 2 and is shown in FIGS. 5A to 5C for different cases. 5A shows the memory allocation for a SINR calculation based on the DPCH channel (dedicated pilot symbols), see case 1. In the first three memory sections, the current cell number Z, the number of integrated pilot symbols K and the number M of the integrated ones Paths of cell Z specified. This is followed by information regarding the antenna diversity (normal / STTD) and the channel on which the calculation is based (DPCH / CPICH; the underlining indicates the selected channel). The calculated intermediate results SD ^eas _z and SD ^exp _{z are} stored in the remaining two memory areas. FIG. 5B shows a representation corresponding to FIG. 5A for case 2 of the SINR calculation based on the CPICH channel (common pilot symbols). The intermediate results sc ^meas ' ^com _z , SC ^exp ' ^com _z , SC ^exp _z and NC ^exp ' ^norm _z are now stored in the third buffer memory P3.

Finally, FIG. 5C shows the memory content of the third buffer memory P3 in a SINR calculation for the STTD mode in closed control loop mode on the basis of the CPICH channel (case 3).

Since the data path is designed in such a way that the inputs can be loaded with different values with each cycle, and the calculation of an integration step of the SINR components only takes one cycle (without latency times) and an integration step of all SINR components within two or three cycles can be calculated, this concept is ideally suited to support virtual time-multiplexed RAKE fingers.

Claims

claims

1. Circuit arrangement for SINR calculation for radio receivers, with - a hardware module (1) for calculating intermediate results for the SINR calculation, and - a processor (2), which carries out the SINR calculation on the basis of the calculated intermediate results.

2. Circuit arrangement according to claim 1, so that the calculated intermediate results are path-specific, cell-level compressed intermediate results for the SINR calculation.

3. Circuit arrangement according to claim 1 or 2, so that the hardware module (1) is designed to calculate intermediate results for different operating modes.

4. Circuit arrangement according to claim 3, so that the processor (2) is programmed to carry out a combination of suitable intermediate results depending on the selected operating mode.

5. Circuit arrangement according to one of claims 3 or 4, so that the operating modes comprise a normal mode without transmitter-side antenna diversity, a multi-antenna diversity mode without closed control loop operation and / or a multi-antenna diversity mode with closed control loop operation.

6. Circuit arrangement according to one of claims 3 to 5, characterized in that the hardware module (1) contains a hardware data path (10) with several selectively evaluable and / or selectively activatable or deactivatable hardware sections (MULT1, MULT2, MULT3, SQR1, SQR2) for calculating the intermediate results.

7. Circuit arrangement according to claim 6, so that the hardware sections (MULT1, MULT2, MULT3) comprise complex multipliers and complex squaring units (SQRl, SQR2).

8. Circuit arrangement according to claim 6 or 7, so that the hardware module has two parallel hardware sections (MULT1, MULT2) on the input side in the form of complex multipliers.

9. Circuit arrangement according to one of claims 6 to 8, characterized in that at least some of the hardware sections at their outputs selectively controllable and thus pre-chargeable and readable for each integration step accumulators (ACH, AC12, AC21, AC22, AC31, AC32, AC41, AC51 ) exhibit.

10. Circuit arrangement according to one of claims 6 to 9, d a d u r c h g e k e n n z e i c h n e t that the hardware module (1) further comprises:

- An input memory (Pl) for data symbols, which is connected to the hardware data path (10), and

- An input memory (P2) for channel coefficients, which is connected to the hardware data path (10).

11. Circuit arrangement according to claim 10, characterized in that the input memory (Pl) for data symbols and / or the input memory (P2) for channel coefficients on the input side are connected to a RAKE receiver that can be operated in particular in time division multiplex.

12. Circuit arrangement according to one of claims 6 to 11, characterized in that the hardware module (1) further an output memory (P3) for storing the intermediate results for the SINR calculation, the memory content of the hardware data path (10) continuously updated and is read by the processor (2).

13. Procedure for calculating the SINR for radio receivers, with the steps:

- Calculating intermediate results for the SINR calculation in a hardware module (1);

- Access to the intermediate results calculated in the hardware module (1) by a processor (2) for calculating the SINR.

14. The method according to claim 13, so that the intermediate results provided by the hardware module (1) are path-specific, compressed to cell level - intermediate results for the SINR calculation.