WO2003078303A2

WO2003078303A2 - Fabrication process for optical mems device for fiber alignment and variable optical attenuation

Info

Publication number: WO2003078303A2
Application number: PCT/CH2003/000159
Authority: WO
Inventors: Robert Gaisch; Sophie Birling; Jean-Philippe Thiebaud; Pierre Cusin; Marc Alan Straub
Original assignee: Colibrys S. A.
Priority date: 2002-03-15
Filing date: 2003-03-11
Publication date: 2003-09-25
Also published as: WO2003078303A3; AU2003206601A1; AU2003206601A8

Abstract

Fabrication Process for an Optical MEMS Device for Fiber Alignment and Variable Optical Attenuation. According to one embodiment of the present invention, a method is provided for fabricating a variable optical attenuator. The method comprises forming a groove on a surface of a substrate for positioning an optical microstructure at least partially in the groove. Furthermore, the method comprises forming an overlayer structure interconnected to the substrate and extending at least partially over the groove for maintaining an optical microstructure in place against the groove. The method also comprises forming a micro-electro-mechanical mechanism on the substrate wherein the microelectro-mechanical mechanism is movable for intercepting light from the optical microstructure

Description

Description FABRICATION PROCESS FOR OPTICAL MEMS DEVICE FOR FIBER

ALIGNMENT AND VARIABLE OPTICAL ATTENUATION

Technical Field

The present invention relates to micro-electro-mechanical (MEMS) fabrication technology. More particularly, the present invention relates to methods for fabricating a MEMS device for aligning an optical microstructure adjacent to an optical device for interacting with light transmitted from the optical microstructure.

Background Art

In communication networks, optical transmission systems are often used for the transmission of data signals between network terminals such as telephones or computers. Optical transmission systems transmit data signals via data-encoded light through optical fibers. Many functions in optical switching systems require physical interaction with the light output from "incoming" optical fibers. Among the functions requiring light interaction are redirecting light from one optical fiber to another, shuttering light, filtering light, converting light output to electrical form, and dividing light into certain wavelengths. Actuators are known devices for positioning elements to interact with light.

As appreciated by persons skilled in the art, many types of MEMS structures and optical microstructures can be fabricated by either bulk or surface micromachining techniques. Bulk micromachining generally involves sculpting one or more sides of a substrate to form desired three-dimensional structures and devices in the same substrate material. The substrate is composed of a material that is readily available in bulk form, and thus ordinarily is silicon or glass. Wet and/or dry etching techniques are employed in association with etch masks and etch stops to form the microstructures. Etching is typically performed through the backside of the substrate. The etching technique can generally be either isotropic or anisotropic in nature. Isotropic etching is insensitive to the crystal orientation of the planes of the material being etched (e.g., the etching of silicon by using a nitric acid as the etchant). Anisotropic etchants, such as potassium hydroxide (KOH), tetramethyl ammonium hydroxide (TMAH), and ethylenediamine pyrochatechol (EDP), selectively attack different crystallographic orientations at different rates, and thus can be used to define relatively accurate sidewalls in the etch pits being created. Etch masks and etch stops are used to prevent predetermined regions of the substrate from being etched. An alternative anisotropic etching technique is DRIE (Deep Reactive Ion Etching). In the DRIE technique, silicon is etched in plasma. This technique yields essentially vertical walls.

On the other hand, surface micromachining generally involves forming three-dimensional structures by depositing a number of different thin films on the top of a silicon wafer, but without sculpting the wafer itself. The films usually serve as either structural or sacrificial layers. Structural layers are frequently composed of polysilicon, silicon nitride, silicon dioxide, silicon carbide, or aluminum. Sacrificial layers are frequently composed of polysilicon, photoresist material, or various kinds of oxides, such as PSG (phosphosilicate glass) and LTO (low-temperature oxide). Successive deposition, etching, and patterning procedures are carried out to arrive at the desired microstructure. In a typical surface micromachining process, a silicon substrate is coated with an isolation layer, and a sacrificial layer is deposited on the coated substrate. Windows are opened in the sacrificial layer, and a structural layer is then deposited and etched. The sacrificial layer is then selectively etched to form a free-standing microstructure such as a beam or a cantilever out of the structural layer. The microstructure is ordinarily anchored to the silicon substrate, and can be designed to be movable in response to an input from an appropriate actuating mechanism. In optical transmission systems, MEMS devices and other micro- components are typically used to physically interact with transmitted light. For example, micro-components, such as lenses and wavelength dividers/multiplexors, can be used in combination with an optical MEMS device, such as an array of shutters, to filter or redirect certain wavelengths of light from "incoming" fiber optics. These devices are manufactured with lithographic mass fabrication techniques of the kind that are used by the semiconductor industry in the manufacture of silicon integrated circuits. Generally, the technology involves shaping a multilayer structure by sequentially depositing and shaping layers of a multilayer wafer that typically includes a plurality of polysilicon layers that are separated by layers of silicon oxide and silicon nitride. Typically, individual layers are shaped by a process known as etching. The etching process is generally controlled by masks that are patterned by photolithographic techniques. MEMS technology can also involve the etching of intermediate sacrificial layers of the wafer to release overlying layers for use as thin elements that can be easily deformed or moved to function as an actuator. One existing problem is the accurate coupling of fiber optics with one another or to other components such as shutters. For example, in order to achieve good coupling efficiency between two fiber optics, or between a fiber optic and another element, the actual coupling has to be performed with sub- micron accuracy and in a reliable and stable manner.

Therefore, it is desired to improve the fabrication of devices for positioning of micro-components with respect to one another. It is also desired to increase the efficiency of the fabrication of these micro-components, such as eliminating or minimizing the need for adaptive alignment techniques. Brief Description of the Drawings

Exemplary embodiments of the invention will now be explained with reference to the accompanying drawings, of which:

Figures 1 -23 are perspective and cross-sectional views illustrating various stages of a method for fabricating a variable optical attenuator in accordance with one method of the present invention.

Detailed Description of the Invention

For purposes of the present disclosure, it will be understood that when a given component such as a layer, region, or substrate is referred to herein as being disposed or formed "on" another component, that given component can be directly on the other component or, alternatively, intervening components (for example, one or more buffer or transition layers, interlayers, electrodes or contacts) can also be present. It will be further understood that the terms

"disposed on" and "formed on" are used interchangeably to describe how a given component is positioned or situated in relation to another component. Hence, the terms "disposed on" and "formed on" are not intended to introduce any limitations relating to particular methods of material transport, deposition, or fabrication.

Various metals can be formed by sputtering, CVD, or evaporation. If gold, nickel or Permalloy™ (Ni_xFe_y) is employed as the metal element, an electroplating process can be carried out to transport the material to a desired surface. The chemical solutions used in the electroplating of various metals are generally known. Some metals, such as gold, might require an appropriate intermediate adhesion layer to prevent peeling. Examples of adhesion material often used include chromium, titanium, or an alloy such as titanium-tungsten (TiW).

Conventional lithographic techniques can be employed in accordance with the micromachining steps of the invention described below. Accordingly, basic lithographic process steps such as photoresist application, optical exposure, and the use of developers are not described in detail herein. Similarly, generally known etching processes can be employed to selectively remove material or regions of material. An imaged photoresist layer is ordinarily used as a masking template. A pattern can be etched directly into the bulk of a substrate, or into a thin film or layer that is then used as a mask for subsequent etching steps. The type of etching process employed in a particular process step (e.g., wet, dry, isotropic, anisotropic, anisotropic-orientation dependent), the etch rate, and the type of etchant used will depend on the composition of material to be removed, the composition of any masking or etch-stop layer to be used, and the profile of the etched region to be formed. As examples, poly-etch (HF:HN0₃:CH₃COOH) can generally be used for isotropic wet etching. Hydroxides of alkali metals (e.g., KOH), simple ammonium hydroxide (NH₄OH), quaternary (tetramethyl) ammonium hydroxide ((CH₃) NOH, also known commercially as TMAH), and ethylenediamine mixed with pyrochatechol in water (EDP) can be used for anisotropic wet etching to fabricate V-shaped or tapered grooves, trenches or cavities. Silicon nitride is typically used as the masking material against etching by KOH, and thus can used in conjunction with the selective etching of silicon. Silicon dioxide is slowly etched by KOH, and thus can be used as a masking layer if the etch time is short. While KOH will etch undoped silicon, heavily doped (p++) silicon can be used as an etch-stop against KOH as well as the alkaline etchants and EDP. Silicon oxide and silicon nitride can be used as masks against TMAH and EDP. The preferred metal used to form electrical components in accordance with the invention is gold, which is resistant to EDP. The adhesion layer applied in connection with forming a gold component (e.g., chromium) is also resistant to EDP. It will be appreciated that electrochemical etching in hydroxide solution can be performed instead of timed wet etching. For example, if a p-type silicon wafer is used as a substrate, an etch-stop can be created by epitaxially growing an n-type silicon end layer to form a p-n junction diode. A voltage is applied between the n-type layer and an electrode disposed in the solution to reverse- bias the p-n junction. As a result, the bulk p-type silicon is etched through a mask down to the p-n junction, stopping at the n-type layer. Furthermore, photovoltaic and galvanic etch-stop techniques are also suitable.

Dry etching techniques such as plasma-phase etching and reactive ion etching (RIE) can also be used to remove silicon and its oxides and nitrides, as well as various metals. Deep reactive ion etching (DRIE) can be used to anisotropically etch deep, vertical trenches in bulk layers. Silicon dioxide is typically used as an etch-stop against DRIE, and thus structures containing a buried silicon dioxide layer, such as silicon-on-insulator (SOI) wafers, can be used according to the methods of the invention as starting substrates for the fabrication of microstructures.

As used herein, the term "device" is interpreted to have a meaning interchangeable with the term "component."

Examples of the methods of the present invention will now be described with reference to the accompanying drawings. A method for fabricating a Variable Optical Attenuator (VOA) according to the present invention consists primarily of three processes: (1) fabrication of a bottom wafer; (2) fabrication of a top wafer; and (3) assembly and processing of the top and bottom wafers into a wafer stack. Referring to FIGs. 1-23 of the drawings, a method for fabricating a VOA according to a two-wafer bulk micromachining process of the present invention will now be described. Referring specifically to FIG. 1 , a perspective view of the top side of a starting wafer or substrate 100 is illustrated. Substrate 100 is provided for fabrication of the bottom wafer. Substrate 100 is preferably a double-side polished, 380 micrometers, silicon wafer. Non-limiting examples of materials for use as substrate 100 include silicon (in single-crystal, polycrystalline, or amorphous forms), silicon oxinitride, glass, quartz, sapphire, zinc oxide, alumina, silica, or one of the various Group III - V compounds in either binary, ternary or quaternary forms (e.g., GaAs, InP, GaN, AIN, AIGaN, InGaAs, and so on). A thin thermal oxide is grown on the top side of substrate 100. Preferably, the oxide is 2 micrometers in thickness. Preferably, a 1600 A nitride is deposited on the top side of substrate 100. The bottom side of substrate 100 is protected with a photoresist material. Photoresist is a photosensitive polymer material commonly used in microelectronic processes as a masking material patterned by photolithographic means. In this step, the photoresist functions as a non-structured protective layer.

Next, a mask, referred to herein as a CAVITY mask, is patterned on the top side surface for forming cavity and actuator areas. The nitride layer is plasma etched away in these areas according to the CAVITY mask. The CAVITY mask defines the etched away areas shown in FIG. 1. The oxide is exposed using a

Buffered Oxide Etch (BOE). BOE is a wet etch product used in wafer processing

^■ for etching oxide in the presence of photoresist materials. V-shaped grooves

102, 104, and 106 are formed on the top side of substrate 100. Optical fibers can be accurately positioned with respect to the top side of substrate 100 by accurately etching v-shaped grooves 102, 104, and 106 with a KOH solution. The positioning of the center of the optical fiber with respect to the top side of substrate 100 is determined by the following: the radius of the optical fiber, the angle the v-shaped groove is etched with respect to the top side of substrate 100; and the width of the groove at the top side of substrate 100. Referring to FIG.2, a cross-sectional front view of an optical fiber 200 in a groove 202 of substrate 100 is illustrated. The front cross-section of optical fiber 200 is shaped circularly having a radius 204 and a center 206. Center 206 is positioned a distance a 208 above substrate 102 by the manufacture of groove 202 in the top side of substrate 100. In this embodiment, the radius of the optical fiber is between the range of 62.25 and 62.75 micrometers. Alternatively, the radius can be another dimension depending on the type of optical fiber selected for use.

Groove 202 is etched into the top side of substrate 100 having a cross- sectional width of distance b 210 at the top side of substrate 100. A KOH etch produces a groove wall 212 haying an angle c 214 with respect to the top side of substrate 100. Angle c 214 is 54.74° in this embodiment. Alternatively, another suitable solution and substrate combination can be used to produce a different angle with respect to the top side of substrate 100. Groove 202 is etched into substrate 100 a depth equal to distance d 216.

The KOH etching process will leave small steps on the walls of grooves 102, 104, and 106. These small steps can be removed by finishing the etching process with an isotropic polishing chemical etch or by adding an oxidation step. The distance between center 206 and the bottom of groove 202 is a distance e 218. Distance e 218 is determined by the following equation, wherein H is the distance between the center of the optical fiber and the bottom of the groove, R is the radius of the optical fiber, and Θ is the angle of the groove wall with respect to the substrate surface:

R

H = - cos θ

As stated above the radius of the optical fiber is between 62.25 and 62.75 micrometers. As stated above, the angle Θ is 54.74°. Thus, the distance H is between 107.83 and 108.70 micrometers in this embodiment. As stated above, center 206 is separated from the top side of substrate 100 by distance a 208. Distance a 208 is determined by the following equation, wherein Δ is the distance separating the top side of substrate 100 and the center of the optical fiber, H is the distance between the center of the optical fiber and the bottom of the groove, and D is the distance from the bottom of the groove to the substrate surface:

Δ = H - D As stated above, distance His between 107.83 and 108.70 micrometers in this embodiment. I n order to determine Δ, distance D must be determined using the following equation, wherein I/Vis the half of the cross-sectional width distance of the groove at the substrate surface, and Θ is the angle of the groove wall with respect to the substrate surface:

cotø In this embodiment, the cross-sectional width distance of groove 202 at the top side of substrate 100 is 128.25 micrometers. Therefore, l/Vis one half of 128.25 micrometers, or 64.125 micrometers. Thus, distance D is 90.70 micrometers. Using the above equation, Δ is approximately 18.0 micrometers. Therefore, grooves 102, 104, and 106 are etched to a depth of approximately 90.1 micrometers. Referring again to FIG. 1 , cavities 108, 110, and 112 are etched for

MEMS devices for interacting with light transmitted through the optical fibers placed in grooves 102, 104, and 106, respectively. This provides a gap for release of the MEMS device. Cavity 114 is etched for placement of a 3-fiber ribbon for optical fiber input. Cavity 116 is etched for placement of another 3- fiber ribbon for optical fiber output. Cavities 118, 120, and 122 are etched for tapering grooves 102, 104, and 106, respectively, for easy insertion of the input optical fibers. Cavities 118, 120, and 122 are etched for tapering grooves 102, 104, and 106, respectively, for easy insertion of the output optical fibers. Referring to FIG. 3, another perspective view of the top side of substrate

100 is illustrated. The KOH etch is continued for over-etching the tapered ends of grooves 102, 104, and 106 for smoothing. Cavities 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, and 128 are etched further to produce deeper cavities. Grooves 102, 104, and 106 remain approximately 91.0 micrometers deep. Next, the nitride and oxide is stripped.

Referring to FIG. 4, a perspective view of the back side surface 400 of substrate 100 is illustrated. A thin oxide is regrown and 1600 A nitride, preferably Si₃N₄ employing a Low Pressure Chemical Vapor Deposition (LPCVD), is

deposited on surface 400. LPCVD is a technique used for depositing materials such as silicon dioxide, silicon nitride, and polisilicon materials on silicon wafers. A mask, referred to herein as a WINDOW mask, is patterned on surface 400. Nitride is plasma etched away according to the WINDOW mask. The WINDOW mask defines an cavity on back side surface 400. As described below, the cavity will be etched further to form an aperture extending through substrate 100. The oxide is exposed using BOE on surface 400. A cavity 402 is etched into surface 400. Cavity 402 is etched to a depth that is approximately 50 micrometers from the cavities on the other side of substrate 100. Alternatively, this etching step can be combined with the etches on the other side of substrate 100.

Referring to FIG. 5, another perspective view of the top side of substrate 100 is illustrated. The nitride and oxide remaining on the top side of substrate 100 is stripped. Next, an oxide layer, preferably 1 - 2 micrometers thick, is grown on all surfaces to protect during subsequent DRIE steps after bonding, as described below.

Referring to FIG.6, another perspective view of the back side of substrate 100 is illustrated. The nitride and oxide on surface 400 is stripped. Next, an oxide layer, preferably 1-2 micrometers thick, is grown on all surfaces.

Referring to FIG. 7, a perspective view of a SOI handle wafer 700 for fabricating the top wafer is illustrated. Wafer 700 is comprised of a Si layer 702, a SiO₂ layer 704, and another Si layer 706. Si layer 702 is preferably 200

micrometers thick. SiO ₂ layer 704 is preferably 2 micrometers thick. Si layer 706

is preferably 85 micrometers thick. A thermal oxide, preferably 0.5 micrometers thick, is grown on a surface 708 of Si layer 706. Si layer 706 is patterned using a mask, referred to herein as a CHANNEL mask, and BOE. The CHANNEL mask defines cavities, described hereinafter, for allowing the optical fibers placed in grooves 102, 104, and 106 to extend partially into wafer 700. Apertures will be formed at patterned areas 710, 712, and 714.

Referring to FIG. 8, another perspective view of a SOI handle wafer 700 for fabricating the top wafer is illustrated. A nitride layer, preferably 0.16 micrometers thick, is deposited 'on surface 708 and patterned using the mask, referred to herein as a SHUTTER mask, for forming shutter openings 800, 802, and 804. Next, the nitride layer is plasma etched to expose Si layer 706. Shutter openings 800, 802, and 804 will align with openings formed at patterned areas 714, 712, and 710, respectively (as shown in FIG.7). Patterned areas 714, 712, and 710 are slightly smaller than openings 800, 802, and 804. Referring to FIG. 9, a closer view of shutter openings 800, 802, and 804 is illustrated. Referring to FIG. 10, another view of shutter openings 800, 802, and 804 is illustrated. A KOH solution is used to etch the exposed silicon at openings 800, 802, and 804. V-grooves approximately 35 micrometers deep are formed. These v-shaped grooves will eventually form the sloped edge of each shutter as described in more detail below. Next, approximately 5000 A thermal oxide is grown on the exposed silicon in the v-shaped grooves etched at 800, 802, and 804. The thermal oxide does not grow on the nitride surface.

Referring to FIG. 11 , the nitride mask is stripped. This stripping exposes the oxide mask shown in FIG. 7. The v-shaped grooves 800, 802, and 804 are protected by oxide.

Referring to FIG. 12, a perspective view of the top wafer after stripping nitride is illustrated.

Referring to FIG. 13, channels 1300, 1302, 1304, 1306, 1308, and 1310 are DRIE etched preferably 35 micrometers deep in wafer 700. The channels are formed using in-situ inferometer measurement to control the depth. This measurement control is not critical. The remaining 20 micrometers is used to form overlayer structures for retaining optical fibers, as described in more detail below. Cavities 1312 and 1314 are etched preferably 65 micrometers deep in wafer 700. Referring to FIG. 14, a closer view of channels 1300, 1302, 1304, 1306,

1308, and 1310 and grooves 800, 802, and 804 is illustrated. The silicon remaining between the separate section of channels 1300, 1302, 1304, 1306, 1308, and 1310 will be used to form the shutter, described in detail below.

Referring to FIG. 15, the top wafer is aligned and fusion bonded to bottom wafer to form the wafer stack. Si layer 706 is bonded directly to the top side surface of substrate 100. Channels 1300, 1302, and 1304 are aligned with cavities 122, 120, and 118, respectively. Likewise, channels 1306, 1308, and 1310 are aligned with cavities 128, 126, and 124, respectively. This assembly process is preferably completed under vacuum to avoid excessive pressure differences in any subsequent DRIE etching steps. The bonded wafer is approximately between 747 and 847 micrometers in thickness.

Referring to FIG. 16, the bottom side of substrate 100 is illustrated. A thin layer of nitride, preferably 1600 A (0.16 micrometers) of LPVCD Si₃ N₄ , is

deposited on all surfaces. Referring to FIG. 17, a surface 1700 of SiO ₂ layer 704 is exposed. The

thin nitride layer is stripped from surface 1700 and preferably 0.2 micrometers of SiO₂ layer 704, using plasma etch. KOH etch is used to completely remove Si

layer 702 to reveal surface 1700 of silicon layer 706. Nitride is removed from the bottom side of substrate 100. The wafer is now approximately 365 micrometers in thickness. SiO ₂ layer 704 is patterned and etched using a mask, referred to

herein as a DEVICE mask, and BOE. The DEVICE mask etch of SiO ₂ layer 704

defines a pattern for etching through Si layer 706 to grooves 102, 104, and 106, and cavities 114, 116, 118, 120, 122, 124, 126, and 128. Additionally, the DEVICE mask etch of SiO ₂ layer 704 defines a pattern for fabricating actuators

1802, and 1804. The pattern for actuators 1802, and 1804 are aligned over cavities 108, 110, and 112, respectively, so that the actuators are movable.

Referring to FIG. 18, a closer view of actuators 1802 and 1804 is illustrated. Actuators 1802 and 1804 include shutters 1900 and 1902, respectively, as well as a shutter (not shown) for actuator 1800. Stoppers 1904 and 1906 are positioned adjacent shutters 1802 and 1804, respectively, for stopping the insertion of optical fiber ends at the appropriate position adjacent the shutters.

During the etch of SiO₂ layer 704, the exposed oxide of substrate 100

was also removed from surface 400. A short DRIE etch of cavity 402, partially etched in the step associated with FIG.4, will complete an aperture through the bottom wafer. The oxide layer covering the grooves will protect them during any over-etch.

Referring to FIG. 19, a photoresist is deposited on the top side of the wafer stack. The photoresist is patterned using a mask, referred to herein as an OS mask, for patterning and forming overlayer structures 2104, 2106, 2108, 2110, 2112, 2114, 2116, 2118, 2120 and 2122. Overlayer structures 2104, 2106, 2108, 2110, 2112, 2114, 2116, 2118, 2120, and 2122 function to capture the optical fibers in grooves 102, 104, and 106, shown in FIG. 1. Alternatively, the overlayer structures can be comprised of another suitable material known to those of skill in the art. As described herein, dual overlayer structures are employed for holding an optical fiber in a groove. Alternatively, a single overlayer structure can be employed to hold the optical fiber in the groove. Additionally, the overlayer structure can be a continuous material layer extending over the groove. The overlayer structure can also be one or more strip materials or patterned material extending over the groove to hold the optical fiber in the groove.

A portion of the OS mask overlaps the DEVICE mask for attachment of overlayer structures 2104, 2106, 2108, 2110, 2112, 2114, 2116, 2118, 2120, and 2122 to the stack wafer. The remaining portion extends over grooves 102, 104, and 106 once the grooves are exposed.

The surface area of Si layer 706 exposed after the patterning of the DEVICE and OS masks is DRIE etched to reveal grooves 102, 104, and 106 and cavities 114, 116, 118, 120, 122, 124, 126, and 128. Furthermore, actuators 1802, and 1804 and attached shutters 1900 and 1902 are further formed by the DRIE etching. The oxide layer grown in the step associated with FIG. 5 protects grooves 102, 104, and 106 and cavities 114, 116, 118, 120, 122, 124, 126, and 128 during the etching process. Referring to FIG. 20, a closer view of shutter 1900 and 1902 is illustrated. The actuators, shutter, and overlayer structures are now completely released. The overlayer structures remain approximately 20 micrometers.

Referring to FIG. 21 , the remaining photoresist material on overlayer structures 2104, 2106, 2108, 2110, 2112, 2114, 2116, 2118, 2120, and 2122 is stripped. This stripping exposes the top silicon surface of the overlayer structures. Actuators 1802 and 1804 and shutters 1900 and 1902 are shown in this FIG. 21. Next, a thin thermal oxide is grown on all exposed silicon surface, including sidewalls and the underside of overlayer structures 2100, 2102, 2104, 2106, 2108, 2110, 2112, 2114, 2116, 2118, 2120, and 2122. The thin oxide from the unmasked horizontal surfaces is removed via a short DRIE etch. The thick oxide mask and the thin oxide on the sidewalls and undersides will remain. Referring to FIG. 22, overlayer structures 2100, 2102, 2104, 2106, 2108, 2110, 2112, 2114, 2116, 2118, 2120, and 2122 are etched, preferably using an isotropic SF6 plasma, until the overlayer structures are the desired thickness, preferably between 2 and 3 micrometers. The thickness of overlayer structures 2100, 2102, 2104, 2106, 2108, 2110, 2112, 2114, 2116, 2118, 2120, and 2122 is monitored using in-situ interferometer measurement. All oxidized surfaces are protected during this etching process. Next, all the oxide is stripped using BOE.

Referring to FIG. 23, a perspective top view of wafer stack, generally designated 2800, is illustrated after the oxide strip.

A metal layer is deposited on back side surface 400. This deposition of metal through aperture 402 provides electrical contact to the bottom of actuators 1800, 1802, and 1804. Additionally, the deposition provides a metal surface on the sloped surface of shutters 1900, 1902, and 2300. The metal deposition on the sloped surfaces of shutters 1900, 1902, and 2300 is to transform them into a mirror. The purpose of the mirrors is to redirect the light transmitted from the optical fibers out of the bottom side of stack wafer 2800.

Alternative to the steps described above with respect to FIGs. 13 and 17- 22, a second embodiment is provided in accordance with the present invention. In the second embodiment to the steps described with regard to FIG. 13, channels 1300, 1302, 1304, 1308, 1310, and 1312 can be etched through Si layer 706. In this alternative process, the overlayer structures are not formed from wafer 700. Rather, the overlayer structures are formed of a polysilicon layer. The polysilicon layer, preferably 3 microns in thickness, is deposited on wafer 700. Next, a polishing step is conducted for SFB. Additional steps for the second embodiment is described in more detail below.

In the alternative to the steps associated with FIGs. 17-22, the top side of the wafer stack is removed by grinding polishing to a depth whereby, preferably, 20 microns remaining of Si layer 702. A photoresist layer is deposited on the surface. Next, a pattern is defined on the photoresist layer corresponding to a combination of the above-described DEVICE and OS masks. The patterning of the DEVICE and OS mask combination is DRIE etched to Si0₂ layer 704. The

photoresist layer is stripped. SiO₂ layer 704 is plasma etched according to Si

layer 706, wherein Si layer 706 functions as a mask. Si layer 702 and SiO ₂ layer

704 are DRIE etched preferably 20 micrometers. This step creates the overlayer structures. Next, DRIE etching is continued, preferably 40 micrometers, to stop on Si layer 706. A short DRIE etch is applied to the back side of the stack wafer to remove polysilicon from the shutter. It will be understood that various details of the invention may be changed without departing from the scope of the invention. The switch embodiments described above can be applied to cantilever beams, doubly supported beams, plates or other known type switch geometries known to those of skill in the art. Furthermore, the foregoing description is for the purpose of illustration only, and not for the purpose of limitation — the invention being defined by the claims.

Claims

CLAIMS What is claimed is:

1. A method for fabricating a variable optical attenuator, comprising:

(a) forming a groove on a surface of a substrate for positioning an optical microstructure at least partially in the groove;

(b) forming an overlayer structure interconnected to the substrate and extending at least partially over the groove for maintaining an optical microstructure in place against the groove; and

(c) forming a micro-electro-mechanical mechanism on the substrate wherein the micro-electro-mechanical mechanism is movable for intercepting light from the optical microstructure.

2. The method of claim 1 wherein the substrate comprises a material selected from the group consisting of silicon, silica, glass, quartz, sapphire, zinc oxide, alumina, Group lll-V compounds, and alloys thereof.

3. The method of claim 1 wherein forming the overlayer structure comprises attaching a silicon-on-insulator wafer to the substrate and etching the silicon-on-insulator wafer to form the overlayer structure.

4. The method of claim 1 wherein forming the micro-electro-mechanical mechanism comprises attaching a silicon-on-insulator wafer to the substrate and etching the silicon-on-insulator wafer to form the micro- electro-mechanical mechanism.

5. The method of claim 1 wherein the micro-electro-mechanical mechanism is a shutter having an angled portion for at least partially redirecting intercepted light.

6. The method of claim 5 further comprising forming an aperture through the substrate to provide a pathway for the redirected light.

7. A method for fabricating a variable optical attenuator, comprising:

(a) forming a groove on a surface of a first substrate for positioning an optical microstructure at least partially in the groove; (b) attaching a second substrate to the first substrate;

(c) forming a micro-electro-mechanical mechanism in the second substrate wherein the micro-electro-mechanical mechanism is movable for intercepting light from the optical microstructure; and

(d) forming an overlayer structure in the second substrate extending at least partially over the groove for maintaining an optical microstructure in place against the groove.

8. A method for fabricating a variable optical attenuator, comprising:

(a) forming a groove on a surface of a first substrate for positioning an optical microstructure at least partially in the groove; (b) forming an aperture through the first substrate;

(c) attaching a second substrate to the first substrate;

(d) etching a micro-electro-mechanical mechanism in the second substrate, the micro-electro-mechanical mechanism having a shutter having an angled portion for at least partially redirecting light from the optical microstructure through the aperture; and

(e) forming an overlayer structure in the second substrate wherein the overlayer structure extends at least partially over the groove for maintaining an optical microstructure in place against the groove.

9. A method for fabricating a variable optical attenuator, comprising: (a) forming a groove on a surface of a first substrate for positioning an fl ¬

optical microstructure at least partially in the groove;

(b) forming an aperture through the first substrate for providing a light pathway;

(c) attaching a second substrate to the first substrate; (d) forming a micro-electro-mechanical shutter in the second substrate wherein the micro-electro-mechanical shutter is movable for intercepting light from the optical microstructure, the shutter having an angled portion for at least partially redirecting intercepted light along the light pathway; and (e) forming an overlayer structure in the second substrate extending at least partially over the groove for maintaining an optical microstructure in place against the groove.