WO2003083623A3 - Apparatus and method for aggregation and transportation for plesiosynchronous framing oriented data formats - Google Patents

Apparatus and method for aggregation and transportation for plesiosynchronous framing oriented data formats Download PDF

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Publication number
WO2003083623A3
WO2003083623A3 PCT/US2003/009645 US0309645W WO03083623A3 WO 2003083623 A3 WO2003083623 A3 WO 2003083623A3 US 0309645 W US0309645 W US 0309645W WO 03083623 A3 WO03083623 A3 WO 03083623A3
Authority
WO
WIPO (PCT)
Prior art keywords
timing
plesiosynchronous
data
signal
framing
Prior art date
Application number
PCT/US2003/009645
Other languages
French (fr)
Other versions
WO2003083623A9 (en
WO2003083623A2 (en
Inventor
John R Carrel
Samir Satish
Steve Judge
Brian Royal
Original Assignee
Celion Networks Inc
John R Carrel
Samir Satish
Steve Judge
Brian Royal
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Celion Networks Inc, John R Carrel, Samir Satish, Steve Judge, Brian Royal filed Critical Celion Networks Inc
Priority to AU2003222112A priority Critical patent/AU2003222112A1/en
Publication of WO2003083623A2 publication Critical patent/WO2003083623A2/en
Publication of WO2003083623A3 publication Critical patent/WO2003083623A3/en
Publication of WO2003083623A9 publication Critical patent/WO2003083623A9/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/07—Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates
    • H04J3/073—Bit stuffing, e.g. PDH
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/07—Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
    • H04J3/1605—Fixed allocated frame structures
    • H04J3/1611—Synchronous digital hierarchy [SDH] or SONET
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
    • H04J3/1605—Fixed allocated frame structures
    • H04J3/1623—Plesiochronous digital hierarchy [PDH]

Abstract

The invention provides an apparatus and method for transparently transporting four pleisiosynchronous OC-48 signals (105, 110, 115, 120) over a network (100). Multiple plesiosynchronous data streams are aggregated onto an independent clock source at an ingress circuit (145) through the use of 'stuffing' bits. The independent clock is selected such that the output data rate is greater than the composite input data rate of all the plesiosynchronous data streams. The signal is encapsulated with forward error correction at the transport interface, serialized, and modulated across the transport system (125). An egress circuit (140) at the receiving end recovers the modulated signal and extracts the data stream and the timing extraction resulting in a return of the original data frames with the same timing as the originals. In this manner, the timing is reproduced identical to the timing of the incident signal at the ingress path, ensuring the data is identical in content and timing.
PCT/US2003/009645 2002-03-28 2003-03-28 Apparatus and method for aggregation and transportation for plesiosynchronous framing oriented data formats WO2003083623A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003222112A AU2003222112A1 (en) 2002-03-28 2003-03-28 Apparatus and method for aggregation and transportation for plesiosynchronous framing oriented data formats

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US36821402P 2002-03-28 2002-03-28
US60/368,214 2002-03-28

Publications (3)

Publication Number Publication Date
WO2003083623A2 WO2003083623A2 (en) 2003-10-09
WO2003083623A3 true WO2003083623A3 (en) 2004-04-08
WO2003083623A9 WO2003083623A9 (en) 2004-06-24

Family

ID=28675461

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/009645 WO2003083623A2 (en) 2002-03-28 2003-03-28 Apparatus and method for aggregation and transportation for plesiosynchronous framing oriented data formats

Country Status (3)

Country Link
US (1) US20030235215A1 (en)
AU (1) AU2003222112A1 (en)
WO (1) WO2003083623A2 (en)

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Also Published As

Publication number Publication date
AU2003222112A1 (en) 2003-10-13
WO2003083623A9 (en) 2004-06-24
WO2003083623A2 (en) 2003-10-09
AU2003222112A8 (en) 2003-10-13
US20030235215A1 (en) 2003-12-25

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