WO2003088250A2 - Method of manufacture of programmable conductor memory - Google Patents
Method of manufacture of programmable conductor memory Download PDFInfo
- Publication number
- WO2003088250A2 WO2003088250A2 PCT/US2003/010952 US0310952W WO03088250A2 WO 2003088250 A2 WO2003088250 A2 WO 2003088250A2 US 0310952 W US0310952 W US 0310952W WO 03088250 A2 WO03088250 A2 WO 03088250A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- array
- forming
- glass
- top electrode
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0009—RRAM elements whose operation depends upon chemical change
- G11C13/0011—RRAM elements whose operation depends upon chemical change comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/041—Modification of the switching material, e.g. post-treatment, doping
- H10N70/046—Modification of the switching material, e.g. post-treatment, doping by diffusion, e.g. photo-dissolution
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/061—Patterning of the switching material
- H10N70/063—Patterning of the switching material by etching of pre-deposited switching material layers, e.g. lithography
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
- H10N70/245—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies the species being metal cations, e.g. programmable metallization cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
- H10N70/8825—Selenides, e.g. GeSe
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
- Y10T428/24917—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer
Definitions
- This invention relates generally to a method of manufacture of memory devices for integrated circuits and more particularly to programmable conductor memory arrays comprising glass electrolyte elements.
- DRAM dynamic random access memory
- Non-volatile memories do not need f equent ref esh cycles to preserve their stored information, so they consume less power than volatile memories. The information stays in the memory even when the power is turned off.
- Non-volatile memories include magnetic random access memories (MRAMs), erasable programmable read only memories (EPROMs) and variations thereof.
- Non-volatile memory is the programmable conductor or programmable metallization memory cell, which is described by Kozicki et al. in (U.S. Patent No. 5,761,115; No. 5,914,893; and No. 6,084,796), which are incorporated herein by reference.
- the programmable conductor cell of Kozicki et al. (also referred to by Kozicki et al. as a "metal dendrite memory”) comprises a glass ion conductor, such as a chalcogenide- metal ion glass and a plurality of electrodes disposed at the surface of the fast ion conductor and spaced a distance apart from on another.
- the glass/ion element shall be referred to herein as a "glass electrolyte,” or, more generally, “cell body.”
- a non-volatile conductive pathway (considered a sidewall "dendrite” by Kozicki et al.) grows from the cathode through or along the cell body towards the anode.
- the growth of the dendrite depends upon applied voltage and time; the higher the voltage, the faster the growth rate; and the longer the time, the longer the dendrite.
- the dendrite stops growing when the voltage is removed.
- the dendrite shrinks, re-dissolving metal ions into the cell body, when the voltage polarity is reversed.
- programmable capacitance between electrodes are programmed by the extent of dendrite growth.
- programmable resistances are also programmed in accordance with the extent of dendrite growth. The resistance, or capacitance of the cell thus changes with changing dendrite length. By completely shorting the glass electrolyte, the metal dendrite can cause a radical change in current flow through the cell, defining a different memory state.
- a memory storage element e.g., capacitor
- Programmable memory cells have been fabricated also using a container configuration, wherein the electrodes and body layers are deposited into a via etched into an insulating layer. The dendrites were believed by Kozicki et al. to grow along the interface between the cell and the via wall.
- the memory cell is formed in an array having a conventional DRAM-type circuit design. For example, in a conventional cross-point circuit design, memory elements are formed between upper and lower conductive lines at intersections.
- a via is formed in an insulating layer and filled with the memory element, such as a glass electrolyte or glass fast ion diffusion (GFID) element.
- GFID glass electrolyte or glass fast ion diffusion
- a method for fabricating programmable conductor memory cells on a substrate using blanket deposition of layers.
- the fabrication method comprises forming a bottom electrode in contact with a conductive region in a semiconductor base material, providing a glass electrolyte layer having metal ions diffused therein and being capable of growing conductive pathway(s) therethrough under the influence of an applied voltage and forming a top electrode layer.
- the top electrode layer, the glass electrolyte layer and the bottom electrode are patterned and etched to define separate pillars or cells of stacked materials.
- a liner layer of an insulating material that conforms to the cells and the semiconductor base material is deposited over the cells.
- This liner layer acts as a barrier to prevent diffusion of the metal away from the cell. Remaining regions between the cells are filled with an insulating layer. At least some of the insulating layer and some of the liner layer are removed to make contact to the top electrode layer of the cell and to the substrate.
- each programmable conductor memory cell or pillar comprises a bottom electrode, a cell body formed of a glass electrolyte layer having metal ions diffused therein and a top electrode.
- Figure 1 is a schematic cross-section of a partially fabricated integrated circuit, showing blanket layers deposited on a semiconductor substrate according to a preferred embodiment of the present invention.
- Figure 2 is a schematic cross-section of the structure of Figure 1 after patterning to define a programmable memory cell in a stud configuration.
- Figure 3 is a schematic cross-section of the programmable memory cell of Figure 2 after deposition of a thin, conformal sealing layer.
- Figure 4A is a schematic cross-section of two cells in an array of programmable memory cells, similar to that of Figure 3, after deposition of a layer of insulating material to fill the spaces around them.
- Figure 4B is a schematic cross-section of the cells of Figure 4 A after electrical contacts to the electrodes of the cells have been made.
- the preferred embodiment discloses a method of fabricating a programmable memory cell in a stud configuration. Blanket layers of electrode and body materials are deposited and subsequently patterned and etched, leaving pillars or studs as individual devices. The blanket deposition of the layers avoids problems associated with via filling and allows more flexibility in cell configuration.
- a semiconductor base material 100 containing a heavily doped (e.g., n + ) conductive region 102 comprises the substrate 101 upon which the memory cells are fabricated.
- the substrate comprises the lowest layer of semiconductor material from which devices are formed in the integrated circuit.
- the substrate comprises a single-crystal silicon wafer.
- an epitaxial silicon layer or another semiconductor, such as a IH-N material, can be used.
- a bottom electrode 103 makes contact with the substrate.
- the bottom electrode 103 can include more than one layer.
- the bottom electrode 103 comprises a layer of polysilicon 104, a layer of tungsten nitride 106 and a layer of tungsten 108.
- the polysilicon layer 104 is between about 25 nm and 75 nm thick
- the tungsten nitride layer 106 is between about 5 nm and 40 nm thick
- the tungsten layer 108 is between about 50 nm and 100 nm thick.
- the body 110 of the programmable memory cell is deposited over the electrode 103.
- the memory cell body 110 comprises a glass material, preferably a chalcogenide glass selected from the group consisting of sulfur, germanium, selenium and tellurium, more preferably a glass comprising germanium (Ge) and selenium (Se), in which the ratio of Ge:Se can vary (e.g., Ge 4 Se 6 , Ge 3 Se 7 or Ge 2 Se 8 ) but is preferably targeted for about Ge 25 Se 75 ).
- the thickness of the germanium selenide layer is preferably between about 25 nm and 75 nm, with a target thickness of about 50 nm in the illustrated embodiment.
- Preferred methods of depositing the Ge-Se material include sputtering and evaporation. More complicated structures for the cell body are also contemplated, as discussed below.
- a metal film (not shown) is deposited over the memory cell body 110 as a source of metal ions for diffusion into the memory cell body.
- the metal film includes a metal from Group IB or Group IIB (e.g., silver, copper or zinc), and more preferably the metal is silver.
- the metal film may be co-sputtered tungsten- silver.
- Energy is provided to diffuse metal from the film into the memory cell body 110, preferably by photodissolution, a self-limiting reaction. Take, for example, a silver layer of 30 nm over a Ge-Se layer 110 of 50 nm, exposed to ultraviolet radiation, particularly ultraviolet radiation with a wavelength of less than 500 nm at about 4 mW/cm 2 for about 15 min.
- Sufficient silver dissolves into the glass layer 110 to saturate the glass by forming a glass electrolyte ternary compound with about 30 atomic percent silver. It is preferred that there be some silver film left over the cell body 110 after the diffusion occurs.
- the 50-nm layer of Ge-Se consumes about 15 nm of silver, leaving a film 112 of about 15 nm over the memory cell body after the photodissolution reaction.
- metal for the programmable conductor memory cell body is supplied by other means.
- the metal and glass material can be co- sputtered or deposited from a source that contains all species, so no metal deposition and drive-in steps are needed.
- This fast ion conducting element with metal ions diffused therein will be referred to herein as the memory cell body 110.
- the cell body 110 can include multiple layers.
- the cell body 110 in one embodiment includes a first Ge-Se layer (e.g., Ge 4 Se 6 ), a metal selenide layer (e.g., Ag 2 Se) thereover, and a second Ge-Se layer (e.g., Ge 4 Se 6 ) over the metal selenide layer.
- a first Ge-Se layer e.g., Ge 4 Se 6
- a metal selenide layer e.g., Ag 2 Se
- Ge 4 Se 6 Ge 4 Se 6
- the intermediate metal selenide layer provides metal to the cell body 110 for formation of conductive pathways under the influence of applied electrical fields.
- an additional silver layer 112 may be deposited particularly if the original silver layer was fully consumed in the dissolution process.
- the top electrode further comprises a tungsten layer 114 with a thickness between about 5 nm and 25 nm and is formed over any remaining or added metal film 112.
- the stack of blanket layers is patterned using a mask that forms pillars, preferably less than about 250 nm in width and preferably separated from one another by at least about 300 nm, using standard photolithographic techniques as are known in the art.
- the layers from the bottom electrode 103 to the top electrode 114 are then etched down to the substrate 101, preferably including a physical etch component, more preferably using Ar/Cl sputtering or reactive ion etching.
- each pillar 120 is an individual programmable memory cell.
- the width of each cell 120 is less than about 250 nm, and the spaces between the cells are at least about 300 nm in width.
- the skilled artisan will readily appreciate that such spacing issues will depend upon the critical dimension for any particular generation of integrated circuit processing. Currently, state-of- the-art fabrication techniques employ 0.13 ⁇ m line widths, although this critical dimension is expected to continue to shrink with each new generation of integrated circuit technology.
- Figure 3 shows an exemplary memory cell 120, covered by a blanket liner layer 200 of insulating material, preferably between about 5 nm and 50 nm in thickness, and also preferably comprising a material that can serve as a diffusion barrier.
- the liner layer 200 is selected to prevent diffusion of metal from metal film 112 away from the cell 120 and into other areas of the integrated circuit, where it could cause severe problems.
- the liner layer 200 comprises silicon nitride that conforms over the cells and the semiconductor base material.
- Fabrication of the memory cell array of the illustrated embodiment comprises deposition of a blanket layer of silver to a thickness of about 30 nm. Much of the blanket layer is removed during etching to form individual memory cell stacks 120. The silver that remains in the individual cells is encapsulated by the liner layer 200 to prevent it from diffusing away from the cell 120.
- Figure 4 A shows two memory cells 120 in a memory array after blanket deposition of an insulating layer 210 to fill the spaces between the separate cells 120.
- the insulating material 210 is silicon oxide deposited using TEOS, although the skilled artisan will readily appreciate that other insulating materials (e.g., low k materials) known in the art can be used readily with good result.
- Electrodes are made to the electrodes of the memory cells 120 as shown in Figure 4B. At least some of the insulating material 210 and/or liner layer 200 are removed from the upper surface of electrode layer 114. These materials can be removed by chemical mechanical polishing (CMP), arranged to stop on and expose the top surface of electrode layer 114, or alternatively by patterning and etching, preferably dry etching, as shown in Figure 4B, or any other method known in the art. Note that the drawings are not to scale and that the openings for making contact can be comparable to the dimensions of the cell 120 top surface. In addition, vias are etched through the insulating layer 210 between cells down to the conducting region 102 of the semiconductor substrate 101. A conducting material is used to make contact to both the electrode layers 114 (contacts 220) and the conducting region 102 of the substrate (contacts 230). Contact 230 makes electrical connection to the lower electrode 103 through conducting region 102.
- CMP chemical mechanical polishing
- a conducting material is used to make contact to both the electrode layers 114 (
- each cell comprises stacked materials on a semiconductor substrate.
- the regions between the cells comprise insulating material, preferably including a thin barrier layer 200 (preferably silicon nitride) conforming to the cells 120 and to the substrate 100 and a thick layer of insulation 210 (preferably a form of silicon oxide) that fills in the remaining space between the cells.
- the barrier layer 200 is between about 5 nm and 50 nm thick.
- the silicon oxide 210 is deposited from tetraethylorthosilicate (TEOS).
- TEOS tetraethylorthosilicate
- Each programmable conductor memory cell 120 comprises the layers discussed above in reference to Figures 1-4. These include a bottom electrode 103 comprising one or more layers, a cell body 110 that includes glass electrolyte layer having metal ions diffused therein and a top electrode 112, 114.
- the bottom electrode 103 preferably comprises a polysilicon layer 104, a tungsten nitride layer 106 and a tungsten layer 108.
- the polysilicon layer 104 is between about 25 nm and 75 nm thick
- the tungsten nitride layer 106 is between about 5 nm and 40 nm thick
- the tungsten layer 108 is between about 50 nm and 100 nm thick.
- the glass electrolyte material 110 comprises a chalcogenide glass with metal ions diffused therein, more preferably silver germanium selenide, typically of the form Ag/Ge 25 Se 75 .
- the thickness of the silver germanium selenide layer is preferably between about 25 nm and 75 nm. There is some silver film 112 remaining over the glass after silver ions have been driven into the Ge-Se, whether left over from photodissolution or deposited after forming the electrolyte 110.
- the top electrode also comprises a tungsten layer 114 over the silver film 112 with a thickness between about 5 nm and 25 nm.
- the memory cell body 110 i.e., the glass electrolyte material having metal ions therein, forms conductive pathways that grow from the negative electrode to the positive electrode when a first voltage is applied to the electrodes 103, 114.
- the growth of the conductive pathways depends upon applied voltage and time. Low voltages cause slow growth, whereas higher voltages result in faster growth of conductive path(s) from the negative electrode to the positive electrode. Without being limited by theory, it is believed that the conductive pathways grow by precipitation of cations (e.g., silver cations) from the memory cell body 110. Changes in the extent of the conductive pathways affect the resistance of the devices. The conductive pathway remains intact when the voltage is removed.
- the memory has two basic states: 0 and 1. When there is no conductive pathway, the memory cell has high electrical resistance and reads as 0. When the conductive pathway shorts the memory cell body, from the cathode to the anode, the resistance is low and the memory cell reads as 1.
- the change in resistance of the memory cell with and without a conductive pathway can be as much as two orders of magnitude, i.e., a change from Megaohms to milliohms. Reversing the polarity of the voltage preferably reverses the conductive pathway.
- the memory cell can be programmed into as many as 3 or 4 states by setting the extent of the conductive pathway. These changes can be detected easily by passing current through the bit lines and word lines (not shown) connected to the contacts 220, 230 in the memory array, such that changing the extent of the pathways can serve to change the state of the memory bit.
Abstract
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/121,792 US6858482B2 (en) | 2002-04-10 | 2002-04-10 | Method of manufacture of programmable switching circuits and memory cells employing a glass layer |
US10/121,792 | 2002-04-10 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2003088250A2 true WO2003088250A2 (en) | 2003-10-23 |
Family
ID=28790404
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2003/010952 WO2003088250A2 (en) | 2002-04-10 | 2003-04-10 | Method of manufacture of programmable conductor memory |
Country Status (3)
Country | Link |
---|---|
US (2) | US6858482B2 (en) |
AU (1) | AU2003231998A1 (en) |
WO (1) | WO2003088250A2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102004061548A1 (en) * | 2004-12-21 | 2006-06-29 | Infineon Technologies Ag | Memory cell matrix for integration of solid electrolyte memory cells has word line and plate line that are controlled by means of selection transistor and exhibits common plate electrode which is connected to common plate circuit |
Families Citing this family (87)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040052117A1 (en) * | 2002-07-05 | 2004-03-18 | Hai Jiang | Fabrication of ultra-small memory elements |
US6784069B1 (en) * | 2003-08-29 | 2004-08-31 | Micron Technology, Inc. | Permeable capacitor electrode |
US7411208B2 (en) * | 2004-05-27 | 2008-08-12 | Samsung Electronics Co., Ltd. | Phase-change memory device having a barrier layer and manufacturing method |
US7482616B2 (en) * | 2004-05-27 | 2009-01-27 | Samsung Electronics Co., Ltd. | Semiconductor devices having phase change memory cells, electronic systems employing the same and methods of fabricating the same |
DE102004041894B3 (en) * | 2004-08-30 | 2006-03-09 | Infineon Technologies Ag | A memory device (CBRAM) having memory cells based on a resistance variable active solid electrolyte material and method of manufacturing the same |
TW200620473A (en) * | 2004-09-08 | 2006-06-16 | Renesas Tech Corp | Nonvolatile memory device |
US7634337B2 (en) * | 2004-12-29 | 2009-12-15 | Snap-On Incorporated | Vehicle or engine diagnostic systems with advanced non-volatile memory |
US7937198B2 (en) * | 2004-12-29 | 2011-05-03 | Snap-On Incorporated | Vehicle or engine diagnostic systems supporting fast boot and reprogramming |
US7348590B2 (en) * | 2005-02-10 | 2008-03-25 | Infineon Technologies Ag | Phase change memory cell with high read margin at low power operation |
US7361925B2 (en) * | 2005-02-10 | 2008-04-22 | Infineon Technologies Ag | Integrated circuit having a memory including a low-k dielectric material for thermal isolation |
US7214958B2 (en) | 2005-02-10 | 2007-05-08 | Infineon Technologies Ag | Phase change memory cell with high read margin at low power operation |
JPWO2006129367A1 (en) * | 2005-06-02 | 2008-12-25 | 有限会社 みすゞR&D | Non-volatile memory |
US20070215987A1 (en) * | 2006-03-15 | 2007-09-20 | Schwerin Ulrike G | Method for forming a memory device and memory device |
US20080314738A1 (en) * | 2007-06-19 | 2008-12-25 | International Business Machines Corporation | Electrolytic Device Based on a Solution-Processed Electrolyte |
JP5175525B2 (en) * | 2007-11-14 | 2013-04-03 | 株式会社東芝 | Nonvolatile semiconductor memory device |
KR100912822B1 (en) | 2007-11-22 | 2009-08-18 | 한국전자통신연구원 | Solid electrolyte memory device and fabricating method thereof |
US7825479B2 (en) | 2008-08-06 | 2010-11-02 | International Business Machines Corporation | Electrical antifuse having a multi-thickness dielectric layer |
JP5531296B2 (en) * | 2008-09-02 | 2014-06-25 | 株式会社東芝 | Nonvolatile semiconductor memory device |
US8058646B2 (en) | 2008-10-29 | 2011-11-15 | Seagate Technology Llc | Programmable resistive memory cell with oxide layer |
US9812638B2 (en) * | 2010-03-19 | 2017-11-07 | Globalfoundries Inc. | Backend of line (BEOL) compatible high current density access device for high density arrays of electronic components |
US9012307B2 (en) * | 2010-07-13 | 2015-04-21 | Crossbar, Inc. | Two terminal resistive switching device structure and method of fabricating |
US9601692B1 (en) | 2010-07-13 | 2017-03-21 | Crossbar, Inc. | Hetero-switching layer in a RRAM device and method |
US8946046B1 (en) | 2012-05-02 | 2015-02-03 | Crossbar, Inc. | Guided path for forming a conductive filament in RRAM |
US9570678B1 (en) | 2010-06-08 | 2017-02-14 | Crossbar, Inc. | Resistive RAM with preferental filament formation region and methods |
CN103081093B (en) * | 2010-06-11 | 2015-06-03 | 科洛斯巴股份有限公司 | Pillar structure for memory device and method |
US8441835B2 (en) | 2010-06-11 | 2013-05-14 | Crossbar, Inc. | Interface control for improved switching in RRAM |
US8374018B2 (en) | 2010-07-09 | 2013-02-12 | Crossbar, Inc. | Resistive memory using SiGe material |
US8884261B2 (en) | 2010-08-23 | 2014-11-11 | Crossbar, Inc. | Device switching using layered device structure |
US8467227B1 (en) | 2010-11-04 | 2013-06-18 | Crossbar, Inc. | Hetero resistive switching material layer in RRAM device and method |
US8168506B2 (en) | 2010-07-13 | 2012-05-01 | Crossbar, Inc. | On/off ratio for non-volatile memory device and method |
US8569172B1 (en) | 2012-08-14 | 2013-10-29 | Crossbar, Inc. | Noble metal/non-noble metal electrode for RRAM applications |
US8947908B2 (en) | 2010-11-04 | 2015-02-03 | Crossbar, Inc. | Hetero-switching layer in a RRAM device and method |
US9401475B1 (en) | 2010-08-23 | 2016-07-26 | Crossbar, Inc. | Method for silver deposition for a non-volatile memory device |
US8404553B2 (en) | 2010-08-23 | 2013-03-26 | Crossbar, Inc. | Disturb-resistant non-volatile memory device and method |
US8889521B1 (en) | 2012-09-14 | 2014-11-18 | Crossbar, Inc. | Method for silver deposition for a non-volatile memory device |
US8492195B2 (en) | 2010-08-23 | 2013-07-23 | Crossbar, Inc. | Method for forming stackable non-volatile resistive switching memory devices |
US8558212B2 (en) | 2010-09-29 | 2013-10-15 | Crossbar, Inc. | Conductive path in switching material in a resistive random access memory device and control |
US8391049B2 (en) | 2010-09-29 | 2013-03-05 | Crossbar, Inc. | Resistor structure for a non-volatile memory device and method |
USRE46335E1 (en) | 2010-11-04 | 2017-03-07 | Crossbar, Inc. | Switching device having a non-linear element |
US8502185B2 (en) | 2011-05-31 | 2013-08-06 | Crossbar, Inc. | Switching device having a non-linear element |
US8088688B1 (en) | 2010-11-05 | 2012-01-03 | Crossbar, Inc. | p+ polysilicon material on aluminum for non-volatile memory device and method |
US8930174B2 (en) | 2010-12-28 | 2015-01-06 | Crossbar, Inc. | Modeling technique for resistive random access memory (RRAM) cells |
FR2970115B1 (en) | 2010-12-29 | 2013-01-18 | Altis Semiconductor Snc | METHOD FOR ETCHING A PROGRAMMABLE MEMORY MICROELECTRONIC DEVICE |
US8487293B2 (en) * | 2010-12-30 | 2013-07-16 | Micron Technology, Inc. | Bipolar switching memory cell with built-in “on ”state rectifying current-voltage characteristics |
US9153623B1 (en) | 2010-12-31 | 2015-10-06 | Crossbar, Inc. | Thin film transistor steering element for a non-volatile memory device |
US8815696B1 (en) | 2010-12-31 | 2014-08-26 | Crossbar, Inc. | Disturb-resistant non-volatile memory device using via-fill and etchback technique |
US8791010B1 (en) | 2010-12-31 | 2014-07-29 | Crossbar, Inc. | Silver interconnects for stacked non-volatile memory device and method |
US8450710B2 (en) | 2011-05-27 | 2013-05-28 | Crossbar, Inc. | Low temperature p+ silicon junction material for a non-volatile memory device |
US9620206B2 (en) | 2011-05-31 | 2017-04-11 | Crossbar, Inc. | Memory array architecture with two-terminal memory cells |
US8394670B2 (en) | 2011-05-31 | 2013-03-12 | Crossbar, Inc. | Vertical diodes for non-volatile memory device |
US8619459B1 (en) | 2011-06-23 | 2013-12-31 | Crossbar, Inc. | High operating speed resistive random access memory |
US8659929B2 (en) | 2011-06-30 | 2014-02-25 | Crossbar, Inc. | Amorphous silicon RRAM with non-linear device and operation |
US9564587B1 (en) | 2011-06-30 | 2017-02-07 | Crossbar, Inc. | Three-dimensional two-terminal memory with enhanced electric field and segmented interconnects |
US9627443B2 (en) | 2011-06-30 | 2017-04-18 | Crossbar, Inc. | Three-dimensional oblique two-terminal memory with enhanced electric field |
US8946669B1 (en) | 2012-04-05 | 2015-02-03 | Crossbar, Inc. | Resistive memory device and fabrication methods |
US9166163B2 (en) | 2011-06-30 | 2015-10-20 | Crossbar, Inc. | Sub-oxide interface layer for two-terminal memory |
CN103828047A (en) | 2011-07-22 | 2014-05-28 | 科洛斯巴股份有限公司 | Seed layer for a p + silicon germanium material for non-volatile memory device and method |
US8674724B2 (en) | 2011-07-29 | 2014-03-18 | Crossbar, Inc. | Field programmable gate array utilizing two-terminal non-volatile memory |
US9729155B2 (en) | 2011-07-29 | 2017-08-08 | Crossbar, Inc. | Field programmable gate array utilizing two-terminal non-volatile memory |
US10056907B1 (en) | 2011-07-29 | 2018-08-21 | Crossbar, Inc. | Field programmable gate array utilizing two-terminal non-volatile memory |
US9006075B2 (en) | 2011-11-17 | 2015-04-14 | Micron Technology, Inc. | Memory cells, semiconductor devices including such cells, and methods of fabrication |
US9048415B2 (en) | 2012-01-11 | 2015-06-02 | Micron Technology, Inc. | Memory cells including top electrodes comprising metal silicide, apparatuses including such cells, and related methods |
US8716098B1 (en) | 2012-03-09 | 2014-05-06 | Crossbar, Inc. | Selective removal method and structure of silver in resistive switching device for a non-volatile memory device |
US9087576B1 (en) | 2012-03-29 | 2015-07-21 | Crossbar, Inc. | Low temperature fabrication method for a three-dimensional memory device and structure |
US9685608B2 (en) | 2012-04-13 | 2017-06-20 | Crossbar, Inc. | Reduced diffusion in metal electrode for two-terminal memory |
US8658476B1 (en) | 2012-04-20 | 2014-02-25 | Crossbar, Inc. | Low temperature P+ polycrystalline silicon material for non-volatile memory device |
US8796658B1 (en) | 2012-05-07 | 2014-08-05 | Crossbar, Inc. | Filamentary based non-volatile resistive memory device and method |
US8765566B2 (en) | 2012-05-10 | 2014-07-01 | Crossbar, Inc. | Line and space architecture for a non-volatile memory device |
US10096653B2 (en) | 2012-08-14 | 2018-10-09 | Crossbar, Inc. | Monolithically integrated resistive memory using integrated-circuit foundry compatible processes |
US9583701B1 (en) | 2012-08-14 | 2017-02-28 | Crossbar, Inc. | Methods for fabricating resistive memory device switching material using ion implantation |
US8946673B1 (en) | 2012-08-24 | 2015-02-03 | Crossbar, Inc. | Resistive switching device structure with improved data retention for non-volatile memory device and method |
US9312483B2 (en) | 2012-09-24 | 2016-04-12 | Crossbar, Inc. | Electrode structure for a non-volatile memory device and method |
US9576616B2 (en) | 2012-10-10 | 2017-02-21 | Crossbar, Inc. | Non-volatile memory with overwrite capability and low write amplification |
US11068620B2 (en) | 2012-11-09 | 2021-07-20 | Crossbar, Inc. | Secure circuit integrated with memory layer |
US8982647B2 (en) | 2012-11-14 | 2015-03-17 | Crossbar, Inc. | Resistive random access memory equalization and sensing |
US9412790B1 (en) | 2012-12-04 | 2016-08-09 | Crossbar, Inc. | Scalable RRAM device architecture for a non-volatile memory device and method |
US9406379B2 (en) | 2013-01-03 | 2016-08-02 | Crossbar, Inc. | Resistive random access memory with non-linear current-voltage relationship |
US9112145B1 (en) | 2013-01-31 | 2015-08-18 | Crossbar, Inc. | Rectified switching of two-terminal memory via real time filament formation |
US9324942B1 (en) | 2013-01-31 | 2016-04-26 | Crossbar, Inc. | Resistive memory cell with solid state diode |
US8934280B1 (en) | 2013-02-06 | 2015-01-13 | Crossbar, Inc. | Capacitive discharge programming for two-terminal memory cells |
US8956939B2 (en) | 2013-04-29 | 2015-02-17 | Asm Ip Holding B.V. | Method of making a resistive random access memory device |
JP2014216647A (en) | 2013-04-29 | 2014-11-17 | エーエスエムアイピー ホールディング ビー.ブイ. | Method for manufacturing resistive random access memory having metal-doped resistive switching layer |
US9520562B2 (en) | 2013-07-19 | 2016-12-13 | Asm Ip Holding B.V. | Method of making a resistive random access memory |
US9472757B2 (en) | 2013-07-19 | 2016-10-18 | Asm Ip Holding B.V. | Method of making a resistive random access memory device |
US10290801B2 (en) | 2014-02-07 | 2019-05-14 | Crossbar, Inc. | Scalable silicon based resistive memory device |
US10483462B1 (en) * | 2015-06-17 | 2019-11-19 | Crossbar, Inc. | Formation of structurally robust nanoscale Ag-based conductive structure |
TWI625874B (en) * | 2015-11-05 | 2018-06-01 | 華邦電子股份有限公司 | Conductive-bridging random access memory |
Family Cites Families (160)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3271591A (en) | 1963-09-20 | 1966-09-06 | Energy Conversion Devices Inc | Symmetrical current controlling device |
US3622319A (en) | 1966-10-20 | 1971-11-23 | Western Electric Co | Nonreflecting photomasks and methods of making same |
US3868651A (en) | 1970-08-13 | 1975-02-25 | Energy Conversion Devices Inc | Method and apparatus for storing and reading data in a memory having catalytic material to initiate amorphous to crystalline change in memory structure |
US3743847A (en) | 1971-06-01 | 1973-07-03 | Motorola Inc | Amorphous silicon film as a uv filter |
US4267261A (en) | 1971-07-15 | 1981-05-12 | Energy Conversion Devices, Inc. | Method for full format imaging |
US3961314A (en) | 1974-03-05 | 1976-06-01 | Energy Conversion Devices, Inc. | Structure and method for producing an image |
US3966317A (en) | 1974-04-08 | 1976-06-29 | Energy Conversion Devices, Inc. | Dry process production of archival microform records from hard copy |
US4177474A (en) | 1977-05-18 | 1979-12-04 | Energy Conversion Devices, Inc. | High temperature amorphous semiconductor member and method of making the same |
JPS5565365A (en) | 1978-11-07 | 1980-05-16 | Nippon Telegr & Teleph Corp <Ntt> | Pattern forming method |
DE2901303C2 (en) | 1979-01-15 | 1984-04-19 | Max Planck Gesellschaft Zur Foerderung Der Wissenschaften E.V., 3400 Goettingen | Solid ionic conductor material, its use and process for its manufacture |
US4312938A (en) | 1979-07-06 | 1982-01-26 | Drexler Technology Corporation | Method for making a broadband reflective laser recording and data storage medium with absorptive underlayer |
US4269935A (en) | 1979-07-13 | 1981-05-26 | Ionomet Company, Inc. | Process of doping silver image in chalcogenide layer |
US4316946A (en) | 1979-12-03 | 1982-02-23 | Ionomet Company, Inc. | Surface sensitized chalcogenide product and process for making and using the same |
US4499557A (en) | 1980-10-28 | 1985-02-12 | Energy Conversion Devices, Inc. | Programmable cell for use in programmable electronic arrays |
US4405710A (en) | 1981-06-22 | 1983-09-20 | Cornell Research Foundation, Inc. | Ion beam exposure of (g-Gex -Se1-x) inorganic resists |
US4737379A (en) | 1982-09-24 | 1988-04-12 | Energy Conversion Devices, Inc. | Plasma deposited coatings, and low temperature plasma method of making same |
US4545111A (en) | 1983-01-18 | 1985-10-08 | Energy Conversion Devices, Inc. | Method for making, parallel preprogramming or field programming of electronic matrix arrays |
US4608296A (en) | 1983-12-06 | 1986-08-26 | Energy Conversion Devices, Inc. | Superconducting films and devices exhibiting AC to DC conversion |
US4795657A (en) | 1984-04-13 | 1989-01-03 | Energy Conversion Devices, Inc. | Method of fabricating a programmable array |
US4843443A (en) | 1984-05-14 | 1989-06-27 | Energy Conversion Devices, Inc. | Thin film field effect transistor and method of making same |
US4769338A (en) | 1984-05-14 | 1988-09-06 | Energy Conversion Devices, Inc. | Thin film field effect transistor and method of making same |
US4673957A (en) | 1984-05-14 | 1987-06-16 | Energy Conversion Devices, Inc. | Integrated circuit compatible thin film field effect transistor and method of making same |
US4668968A (en) | 1984-05-14 | 1987-05-26 | Energy Conversion Devices, Inc. | Integrated circuit compatible thin film field effect transistor and method of making same |
US4670763A (en) | 1984-05-14 | 1987-06-02 | Energy Conversion Devices, Inc. | Thin film field effect transistor |
US4678679A (en) | 1984-06-25 | 1987-07-07 | Energy Conversion Devices, Inc. | Continuous deposition of activated process gases |
US4646266A (en) | 1984-09-28 | 1987-02-24 | Energy Conversion Devices, Inc. | Programmable semiconductor structures and methods for using the same |
US4664939A (en) | 1985-04-01 | 1987-05-12 | Energy Conversion Devices, Inc. | Vertical semiconductor processor |
US4637895A (en) | 1985-04-01 | 1987-01-20 | Energy Conversion Devices, Inc. | Gas mixtures for the vapor deposition of semiconductor material |
US4710899A (en) | 1985-06-10 | 1987-12-01 | Energy Conversion Devices, Inc. | Data storage medium incorporating a transition metal for increased switching speed |
US4671618A (en) | 1986-05-22 | 1987-06-09 | Wu Bao Gang | Liquid crystalline-plastic material having submillisecond switch times and extended memory |
US4766471A (en) | 1986-01-23 | 1988-08-23 | Energy Conversion Devices, Inc. | Thin film electro-optical devices |
US4818717A (en) | 1986-06-27 | 1989-04-04 | Energy Conversion Devices, Inc. | Method for making electronic matrix arrays |
US4728406A (en) | 1986-08-18 | 1988-03-01 | Energy Conversion Devices, Inc. | Method for plasma - coating a semiconductor body |
US4809044A (en) | 1986-08-22 | 1989-02-28 | Energy Conversion Devices, Inc. | Thin film overvoltage protection devices |
US4845533A (en) | 1986-08-22 | 1989-07-04 | Energy Conversion Devices, Inc. | Thin film electrical devices with amorphous carbon electrodes and method of making same |
US4853785A (en) | 1986-10-15 | 1989-08-01 | Energy Conversion Devices, Inc. | Electronic camera including electronic signal storage cartridge |
US4788594A (en) | 1986-10-15 | 1988-11-29 | Energy Conversion Devices, Inc. | Solid state electronic camera including thin film matrix of photosensors |
US4847674A (en) | 1987-03-10 | 1989-07-11 | Advanced Micro Devices, Inc. | High speed interconnect system with refractory non-dogbone contacts and an active electromigration suppression mechanism |
US4800526A (en) | 1987-05-08 | 1989-01-24 | Gaf Corporation | Memory element for information storage and retrieval system and associated process |
US4891330A (en) | 1987-07-27 | 1990-01-02 | Energy Conversion Devices, Inc. | Method of fabricating n-type and p-type microcrystalline semiconductor alloy material including band gap widening elements |
US4775425A (en) | 1987-07-27 | 1988-10-04 | Energy Conversion Devices, Inc. | P and n-type microcrystalline semiconductor alloy material including band gap widening elements, devices utilizing same |
US4804490A (en) | 1987-10-13 | 1989-02-14 | Energy Conversion Devices, Inc. | Method of fabricating stabilized threshold switching material |
US5272359A (en) | 1988-04-07 | 1993-12-21 | California Institute Of Technology | Reversible non-volatile switch based on a TCNQ charge transfer complex |
GB8910854D0 (en) | 1989-05-11 | 1989-06-28 | British Petroleum Co Plc | Semiconductor device |
US4920078A (en) | 1989-06-02 | 1990-04-24 | Bell Communications Research, Inc. | Arsenic sulfide surface passivation of III-V semiconductors |
US5159661A (en) | 1990-10-05 | 1992-10-27 | Energy Conversion Devices, Inc. | Vertically interconnected parallel distributed processor |
US5314772A (en) | 1990-10-09 | 1994-05-24 | Arizona Board Of Regents | High resolution, multi-layer resist for microlithography and method therefor |
JPH0770731B2 (en) | 1990-11-22 | 1995-07-31 | 松下電器産業株式会社 | Electroplastic element |
US5330630A (en) | 1991-01-02 | 1994-07-19 | Energy Conversion Devices, Inc. | Switch with improved threshold voltage |
US5406509A (en) | 1991-01-18 | 1995-04-11 | Energy Conversion Devices, Inc. | Electrically erasable, directly overwritable, multibit single cell memory elements and arrays fabricated therefrom |
US5166758A (en) | 1991-01-18 | 1992-11-24 | Energy Conversion Devices, Inc. | Electrically erasable phase change memory |
US5335219A (en) | 1991-01-18 | 1994-08-02 | Ovshinsky Stanford R | Homogeneous composition of microcrystalline semiconductor material, semiconductor devices and directly overwritable memory elements fabricated therefrom, and arrays fabricated from the memory elements |
US5596522A (en) | 1991-01-18 | 1997-01-21 | Energy Conversion Devices, Inc. | Homogeneous compositions of microcrystalline semiconductor material, semiconductor devices and directly overwritable memory elements fabricated therefrom, and arrays fabricated from the memory elements |
US5536947A (en) | 1991-01-18 | 1996-07-16 | Energy Conversion Devices, Inc. | Electrically erasable, directly overwritable, multibit single cell memory element and arrays fabricated therefrom |
US5534711A (en) | 1991-01-18 | 1996-07-09 | Energy Conversion Devices, Inc. | Electrically erasable, directly overwritable, multibit single cell memory elements and arrays fabricated therefrom |
US5341328A (en) | 1991-01-18 | 1994-08-23 | Energy Conversion Devices, Inc. | Electrically erasable memory elements having reduced switching current requirements and increased write/erase cycle life |
US5296716A (en) | 1991-01-18 | 1994-03-22 | Energy Conversion Devices, Inc. | Electrically erasable, directly overwritable, multibit single cell memory elements and arrays fabricated therefrom |
US5534712A (en) | 1991-01-18 | 1996-07-09 | Energy Conversion Devices, Inc. | Electrically erasable memory elements characterized by reduced current and improved thermal stability |
US5414271A (en) | 1991-01-18 | 1995-05-09 | Energy Conversion Devices, Inc. | Electrically erasable memory elements having improved set resistance stability |
US5128099A (en) | 1991-02-15 | 1992-07-07 | Energy Conversion Devices, Inc. | Congruent state changeable optical memory material and device |
US5219788A (en) | 1991-02-25 | 1993-06-15 | Ibm Corporation | Bilayer metallization cap for photolithography |
US5177567A (en) | 1991-07-19 | 1993-01-05 | Energy Conversion Devices, Inc. | Thin-film structure for chalcogenide electrical switching devices and process therefor |
US5359205A (en) | 1991-11-07 | 1994-10-25 | Energy Conversion Devices, Inc. | Electrically erasable memory elements characterized by reduced current and improved thermal stability |
US5238862A (en) | 1992-03-18 | 1993-08-24 | Micron Technology, Inc. | Method of forming a stacked capacitor with striated electrode |
US5341271A (en) * | 1992-06-22 | 1994-08-23 | Minnesota Mining And Manufacturing Company | Surge arrester fault indicator |
US5512328A (en) | 1992-08-07 | 1996-04-30 | Hitachi, Ltd. | Method for forming a pattern and forming a thin film used in pattern formation |
US5350484A (en) | 1992-09-08 | 1994-09-27 | Intel Corporation | Method for the anisotropic etching of metal films in the fabrication of interconnects |
US5818749A (en) | 1993-08-20 | 1998-10-06 | Micron Technology, Inc. | Integrated circuit memory device |
US5363329A (en) * | 1993-11-10 | 1994-11-08 | Eugeniy Troyan | Semiconductor memory device for use in an electrically alterable read-only memory |
BE1007902A3 (en) | 1993-12-23 | 1995-11-14 | Philips Electronics Nv | Switching element with memory with schottky barrier tunnel. |
US5500532A (en) | 1994-08-18 | 1996-03-19 | Arizona Board Of Regents | Personal electronic dosimeter |
JP2643870B2 (en) | 1994-11-29 | 1997-08-20 | 日本電気株式会社 | Method for manufacturing semiconductor memory device |
US5543737A (en) | 1995-02-10 | 1996-08-06 | Energy Conversion Devices, Inc. | Logical operation circuit employing two-terminal chalcogenide switches |
US5869843A (en) | 1995-06-07 | 1999-02-09 | Micron Technology, Inc. | Memory array having a multi-state element and method for forming such array or cells thereof |
WO1996041381A1 (en) | 1995-06-07 | 1996-12-19 | Micron Technology, Inc. | A stack/trench diode for use with a multi-state material in a non-volatile memory cell |
US5879955A (en) * | 1995-06-07 | 1999-03-09 | Micron Technology, Inc. | Method for fabricating an array of ultra-small pores for chalcogenide memory cells |
US5789758A (en) | 1995-06-07 | 1998-08-04 | Micron Technology, Inc. | Chalcogenide memory cell with a plurality of chalcogenide electrodes |
US6420725B1 (en) * | 1995-06-07 | 2002-07-16 | Micron Technology, Inc. | Method and apparatus for forming an integrated circuit electrode having a reduced contact area |
US5751012A (en) | 1995-06-07 | 1998-05-12 | Micron Technology, Inc. | Polysilicon pillar diode for use in a non-volatile memory cell |
US5714768A (en) | 1995-10-24 | 1998-02-03 | Energy Conversion Devices, Inc. | Second-layer phase change memory array on top of a logic device |
US5837564A (en) | 1995-11-01 | 1998-11-17 | Micron Technology, Inc. | Method for optimal crystallization to obtain high electrical performance from chalcogenides |
US5694054A (en) | 1995-11-28 | 1997-12-02 | Energy Conversion Devices, Inc. | Integrated drivers for flat panel displays employing chalcogenide logic elements |
US5591501A (en) | 1995-12-20 | 1997-01-07 | Energy Conversion Devices, Inc. | Optical recording medium having a plurality of discrete phase change data recording points |
US5687112A (en) | 1996-04-19 | 1997-11-11 | Energy Conversion Devices, Inc. | Multibit single cell memory element having tapered contact |
US5851882A (en) | 1996-05-06 | 1998-12-22 | Micron Technology, Inc. | ZPROM manufacture and design and methods for forming thin structures using spacers as an etching mask |
US5761115A (en) | 1996-05-30 | 1998-06-02 | Axon Technologies Corporation | Programmable metallization cell structure and method of making same |
US5814527A (en) | 1996-07-22 | 1998-09-29 | Micron Technology, Inc. | Method of making small pores defined by a disposable internal spacer for use in chalcogenide memories |
US5789277A (en) | 1996-07-22 | 1998-08-04 | Micron Technology, Inc. | Method of making chalogenide memory device |
US5998244A (en) * | 1996-08-22 | 1999-12-07 | Micron Technology, Inc. | Memory cell incorporating a chalcogenide element and method of making same |
US6087674A (en) * | 1996-10-28 | 2000-07-11 | Energy Conversion Devices, Inc. | Memory element with memory material comprising phase-change material and dielectric material |
US5825046A (en) | 1996-10-28 | 1998-10-20 | Energy Conversion Devices, Inc. | Composite memory material comprising a mixture of phase-change memory material and dielectric material |
US5846889A (en) | 1997-03-14 | 1998-12-08 | The United States Of America As Represented By The Secretary Of The Navy | Infrared transparent selenide glasses |
US5998066A (en) | 1997-05-16 | 1999-12-07 | Aerial Imaging Corporation | Gray scale mask and depth pattern transfer technique using inorganic chalcogenide glass |
US6031287A (en) | 1997-06-18 | 2000-02-29 | Micron Technology, Inc. | Contact structure and memory element incorporating the same |
US5933365A (en) | 1997-06-19 | 1999-08-03 | Energy Conversion Devices, Inc. | Memory element with energy control mechanism |
US5976928A (en) * | 1997-11-20 | 1999-11-02 | Advanced Technology Materials, Inc. | Chemical mechanical polishing of FeRAM capacitors |
US6011757A (en) | 1998-01-27 | 2000-01-04 | Ovshinsky; Stanford R. | Optical recording media having increased erasability |
US5912839A (en) | 1998-06-23 | 1999-06-15 | Energy Conversion Devices, Inc. | Universal memory element and method of programming same |
US6388324B2 (en) * | 1998-08-31 | 2002-05-14 | Arizona Board Of Regents | Self-repairing interconnections for electrical circuits |
US6515343B1 (en) * | 1998-11-19 | 2003-02-04 | Quicklogic Corporation | Metal-to-metal antifuse with non-conductive diffusion barrier |
US6487106B1 (en) * | 1999-01-12 | 2002-11-26 | Arizona Board Of Regents | Programmable microelectronic devices and method of forming and programming same |
US6985378B2 (en) * | 1998-12-04 | 2006-01-10 | Axon Technologies Corporation | Programmable microelectronic device, structure, and system and method of forming the same |
US6825489B2 (en) * | 2001-04-06 | 2004-11-30 | Axon Technologies Corporation | Microelectronic device, structure, and system, including a memory structure having a variable programmable property and method of forming the same |
US6177338B1 (en) * | 1999-02-08 | 2001-01-23 | Taiwan Semiconductor Manufacturing Company | Two step barrier process |
US6072716A (en) | 1999-04-14 | 2000-06-06 | Massachusetts Institute Of Technology | Memory structures and methods of making same |
JP2000328989A (en) * | 1999-05-18 | 2000-11-28 | Aisan Ind Co Ltd | Fuel injection control unit for engine |
US6350679B1 (en) * | 1999-08-03 | 2002-02-26 | Micron Technology, Inc. | Methods of providing an interlevel dielectric layer intermediate different elevation conductive metal layers in the fabrication of integrated circuitry |
US20030107105A1 (en) * | 1999-08-31 | 2003-06-12 | Kozicki Michael N. | Programmable chip-to-substrate interconnect structure and device and method of forming same |
JP2001167595A (en) * | 1999-12-08 | 2001-06-22 | Mitsubishi Electric Corp | Semiconductor memory |
JP3406265B2 (en) * | 2000-01-20 | 2003-05-12 | 松下電器産業株式会社 | Semiconductor device and manufacturing method thereof |
US6914802B2 (en) * | 2000-02-11 | 2005-07-05 | Axon Technologies Corporation | Microelectronic photonic structure and device and method of forming the same |
JP3901432B2 (en) * | 2000-08-22 | 2007-04-04 | セイコーエプソン株式会社 | Memory cell array having ferroelectric capacitor and manufacturing method thereof |
US6429064B1 (en) * | 2000-09-29 | 2002-08-06 | Intel Corporation | Reduced contact area of sidewall conductor |
US6555860B2 (en) * | 2000-09-29 | 2003-04-29 | Intel Corporation | Compositionally modified resistive electrode |
US6567293B1 (en) * | 2000-09-29 | 2003-05-20 | Ovonyx, Inc. | Single level metal memory cell using chalcogenide cladding |
US6339544B1 (en) * | 2000-09-29 | 2002-01-15 | Intel Corporation | Method to enhance performance of thermal resistor device |
US6404665B1 (en) * | 2000-09-29 | 2002-06-11 | Intel Corporation | Compositionally modified resistive electrode |
US6563164B2 (en) * | 2000-09-29 | 2003-05-13 | Ovonyx, Inc. | Compositionally modified resistive electrode |
US6653193B2 (en) * | 2000-12-08 | 2003-11-25 | Micron Technology, Inc. | Resistance variable device |
US6696355B2 (en) * | 2000-12-14 | 2004-02-24 | Ovonyx, Inc. | Method to selectively increase the top resistance of the lower programming electrode in a phase-change memory |
US6569705B2 (en) * | 2000-12-21 | 2003-05-27 | Intel Corporation | Metal structure for a phase-change memory device |
US6534781B2 (en) * | 2000-12-26 | 2003-03-18 | Ovonyx, Inc. | Phase-change memory bipolar array utilizing a single shallow trench isolation for creating an individual active area region for two memory array elements and one bipolar base contact |
US6531373B2 (en) * | 2000-12-27 | 2003-03-11 | Ovonyx, Inc. | Method of forming a phase-change memory cell using silicon on insulator low electrode in charcogenide elements |
US6687427B2 (en) * | 2000-12-29 | 2004-02-03 | Intel Corporation | Optic switch |
US6727192B2 (en) * | 2001-03-01 | 2004-04-27 | Micron Technology, Inc. | Methods of metal doping a chalcogenide material |
US6348365B1 (en) * | 2001-03-02 | 2002-02-19 | Micron Technology, Inc. | PCRAM cell manufacturing |
US6734455B2 (en) * | 2001-03-15 | 2004-05-11 | Micron Technology, Inc. | Agglomeration elimination for metal sputter deposition of chalcogenides |
US6589714B2 (en) * | 2001-06-26 | 2003-07-08 | Ovonyx, Inc. | Method for making programmable resistance memory element using silylated photoresist |
US6570784B2 (en) * | 2001-06-29 | 2003-05-27 | Ovonyx, Inc. | Programming a phase-change material memory |
US6511867B2 (en) * | 2001-06-30 | 2003-01-28 | Ovonyx, Inc. | Utilizing atomic layer deposition for programmable device |
US6514805B2 (en) * | 2001-06-30 | 2003-02-04 | Intel Corporation | Trench sidewall profile for device isolation |
US6511862B2 (en) * | 2001-06-30 | 2003-01-28 | Ovonyx, Inc. | Modified contact for programmable devices |
US6673700B2 (en) * | 2001-06-30 | 2004-01-06 | Ovonyx, Inc. | Reduced area intersection between electrode and programming element |
US6951805B2 (en) * | 2001-08-01 | 2005-10-04 | Micron Technology, Inc. | Method of forming integrated circuitry, method of forming memory circuitry, and method of forming random access memory circuitry |
US6590807B2 (en) * | 2001-08-02 | 2003-07-08 | Intel Corporation | Method for reading a structural phase-change memory |
US6737312B2 (en) * | 2001-08-27 | 2004-05-18 | Micron Technology, Inc. | Method of fabricating dual PCRAM cells sharing a common electrode |
US6881623B2 (en) * | 2001-08-29 | 2005-04-19 | Micron Technology, Inc. | Method of forming chalcogenide comprising devices, method of forming a programmable memory cell of memory circuitry, and a chalcogenide comprising device |
US6955940B2 (en) * | 2001-08-29 | 2005-10-18 | Micron Technology, Inc. | Method of forming chalcogenide comprising devices |
US6784018B2 (en) * | 2001-08-29 | 2004-08-31 | Micron Technology, Inc. | Method of forming chalcogenide comprising devices and method of forming a programmable memory cell of memory circuitry |
US6646902B2 (en) * | 2001-08-30 | 2003-11-11 | Micron Technology, Inc. | Method of retaining memory state in a programmable conductor RAM |
US20030047765A1 (en) * | 2001-08-30 | 2003-03-13 | Campbell Kristy A. | Stoichiometry for chalcogenide glasses useful for memory devices and method of formation |
US6709958B2 (en) * | 2001-08-30 | 2004-03-23 | Micron Technology, Inc. | Integrated circuit device and fabrication using metal-doped chalcogenide materials |
US6507061B1 (en) * | 2001-08-31 | 2003-01-14 | Intel Corporation | Multiple layer phase-change memory |
EP2112659A1 (en) * | 2001-09-01 | 2009-10-28 | Energy Convertion Devices, Inc. | Increased data storage in optical data storage and retrieval systems using blue lasers and/or plasmon lenses |
US6586761B2 (en) * | 2001-09-07 | 2003-07-01 | Intel Corporation | Phase change material memory device |
US6545287B2 (en) * | 2001-09-07 | 2003-04-08 | Intel Corporation | Using selective deposition to form phase-change memory cells |
US7109056B2 (en) * | 2001-09-20 | 2006-09-19 | Micron Technology, Inc. | Electro-and electroless plating of metal in the manufacture of PCRAM devices |
US6690026B2 (en) * | 2001-09-28 | 2004-02-10 | Intel Corporation | Method of fabricating a three-dimensional array of active media |
US6566700B2 (en) * | 2001-10-11 | 2003-05-20 | Ovonyx, Inc. | Carbon-containing interfacial layer for phase-change memory |
US6545907B1 (en) * | 2001-10-30 | 2003-04-08 | Ovonyx, Inc. | Technique and apparatus for performing write operations to a phase change material memory device |
US6576921B2 (en) * | 2001-11-08 | 2003-06-10 | Intel Corporation | Isolating phase change material memory cells |
US6815818B2 (en) * | 2001-11-19 | 2004-11-09 | Micron Technology, Inc. | Electrode structure for use in an integrated circuit |
US6791859B2 (en) * | 2001-11-20 | 2004-09-14 | Micron Technology, Inc. | Complementary bit PCRAM sense amplifier and method of operation |
US6873538B2 (en) * | 2001-12-20 | 2005-03-29 | Micron Technology, Inc. | Programmable conductor random access memory and a method for writing thereto |
US6512241B1 (en) * | 2001-12-31 | 2003-01-28 | Intel Corporation | Phase change material memory device |
US6909656B2 (en) * | 2002-01-04 | 2005-06-21 | Micron Technology, Inc. | PCRAM rewrite prevention |
US20030143782A1 (en) * | 2002-01-31 | 2003-07-31 | Gilton Terry L. | Methods of forming germanium selenide comprising devices and methods of forming silver selenide comprising structures |
US6867064B2 (en) * | 2002-02-15 | 2005-03-15 | Micron Technology, Inc. | Method to alter chalcogenide glass for improved switching characteristics |
US6671710B2 (en) * | 2002-05-10 | 2003-12-30 | Energy Conversion Devices, Inc. | Methods of computing with digital multistate phase change materials |
US6918382B2 (en) * | 2002-08-26 | 2005-07-19 | Energy Conversion Devices, Inc. | Hydrogen powered scooter |
-
2002
- 2002-04-10 US US10/121,792 patent/US6858482B2/en not_active Expired - Lifetime
-
2003
- 2003-04-10 AU AU2003231998A patent/AU2003231998A1/en not_active Withdrawn
- 2003-04-10 WO PCT/US2003/010952 patent/WO2003088250A2/en not_active Application Discontinuation
-
2004
- 2004-03-03 US US10/790,816 patent/US7479650B2/en not_active Expired - Lifetime
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102004061548A1 (en) * | 2004-12-21 | 2006-06-29 | Infineon Technologies Ag | Memory cell matrix for integration of solid electrolyte memory cells has word line and plate line that are controlled by means of selection transistor and exhibits common plate electrode which is connected to common plate circuit |
Also Published As
Publication number | Publication date |
---|---|
US6858482B2 (en) | 2005-02-22 |
AU2003231998A1 (en) | 2003-10-27 |
US20030194865A1 (en) | 2003-10-16 |
US7479650B2 (en) | 2009-01-20 |
US20040171208A1 (en) | 2004-09-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6858482B2 (en) | Method of manufacture of programmable switching circuits and memory cells employing a glass layer | |
US6838307B2 (en) | Programmable conductor memory cell structure and method therefor | |
TWI449171B (en) | Methods of self-aligned growth of chalcogenide memory access device | |
US8288254B2 (en) | Programmable metallization memory cell with planarized silver electrode | |
US7423281B2 (en) | Microelectronic device with a plurality of storage elements in serial connection and method of producing the same | |
US7294527B2 (en) | Method of forming a memory cell | |
US20060071244A1 (en) | Switching or amplifier device, in particular transistor | |
US8501621B2 (en) | Method of fabrication of the memristive device | |
CN111052376B (en) | Three-dimensional memory array | |
US10978511B1 (en) | Semiconductor device and memory cell | |
US6858465B2 (en) | Elimination of dendrite formation during metal/chalcogenide glass deposition | |
US20140042382A1 (en) | Sidewall diode driving device and memory using same | |
CN113346011A (en) | Memory device, integrated chip and forming method thereof | |
US20220254833A1 (en) | Semiconductor memory devices |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A2 Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NI NO NZ OM PH PL PT RO RU SC SD SE SG SK SL TJ TM TN TR TT TZ UA UG UZ VC VN YU ZA ZM ZW |
|
AL | Designated countries for regional patents |
Kind code of ref document: A2 Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG |
|
WA | Withdrawal of international application | ||
NENP | Non-entry into the national phase |
Ref country code: JP |