WO2003090230A3 - Variable delay compensation for data-dependent mismatch in characteristic of opposing devices of a sense amplifier - Google Patents

Variable delay compensation for data-dependent mismatch in characteristic of opposing devices of a sense amplifier Download PDF

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Publication number
WO2003090230A3
WO2003090230A3 PCT/US2003/008303 US0308303W WO03090230A3 WO 2003090230 A3 WO2003090230 A3 WO 2003090230A3 US 0308303 W US0308303 W US 0308303W WO 03090230 A3 WO03090230 A3 WO 03090230A3
Authority
WO
WIPO (PCT)
Prior art keywords
devices
opposing
nbti
data
sense amp
Prior art date
Application number
PCT/US2003/008303
Other languages
French (fr)
Other versions
WO2003090230A2 (en
Inventor
Nadeem N Eleyan
Howard L Levy
Jeffrey Y Su
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Priority to AU2003214221A priority Critical patent/AU2003214221A1/en
Publication of WO2003090230A2 publication Critical patent/WO2003090230A2/en
Publication of WO2003090230A3 publication Critical patent/WO2003090230A3/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065—Differential amplifiers of latching type

Abstract

Post-manufacture variation of timing may be employed to address data-dependent degradation or creep in device characteristics affecting a differential circuit. One particular example of such data-dependent degradation or creep involves Negative Bias Temperature Instability (NBTI). In certain memory circuit configurations, NBTI can cause threshold voltage (Vt) of PMOS devices to increase by an amount that depends on the historical amount of voltage bias that has been applied across gate and source/drain nodes. In the case of many sense amplifier designs, a predominant value read out using the sense amp may tend to disparately affect one device (or set of devices) as compared with an opposing device (or set of devices). In other words, if the same data value is read over and over again, then one of two opposing PMOS devices of a typical sense amp will accumulate an NBTI-related Vt shift, while the opposing PMOS device will accumulate little or no shift. The accumulated mismatch tends to cause an increase in the sense amp fail-point.
PCT/US2003/008303 2002-04-16 2003-03-17 Variable delay compensation for data-dependent mismatch in characteristic of opposing devices of a sense amplifier WO2003090230A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003214221A AU2003214221A1 (en) 2002-04-16 2003-03-17 Variable delay compensation for data-dependent mismatch in characteristic of opposing devices of a sense amplifier

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/123,480 2002-04-16
US10/123,480 US6762961B2 (en) 2002-04-16 2002-04-16 Variable delay compensation for data-dependent mismatch in characteristic of opposing devices of a sense amplifier

Publications (2)

Publication Number Publication Date
WO2003090230A2 WO2003090230A2 (en) 2003-10-30
WO2003090230A3 true WO2003090230A3 (en) 2004-02-05

Family

ID=29214493

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/008303 WO2003090230A2 (en) 2002-04-16 2003-03-17 Variable delay compensation for data-dependent mismatch in characteristic of opposing devices of a sense amplifier

Country Status (3)

Country Link
US (1) US6762961B2 (en)
AU (1) AU2003214221A1 (en)
WO (1) WO2003090230A2 (en)

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US7177201B1 (en) * 2003-09-17 2007-02-13 Sun Microsystems, Inc. Negative bias temperature instability (NBTI) preconditioning of matched devices
US7164612B1 (en) 2003-10-10 2007-01-16 Sun Microsystems, Inc. Test circuit for measuring sense amplifier and memory mismatches
US7020035B1 (en) 2003-10-10 2006-03-28 Sun Microsystems, Inc. Measuring and correcting sense amplifier and memory mismatches using NBTI
US7088630B2 (en) * 2004-04-23 2006-08-08 Macronix International Co., Ltd. Circuit and method for high speed sensing
US7616513B1 (en) 2004-10-29 2009-11-10 Cypress Semiconductor Corporation Memory device, current sense amplifier, and method of operating the same
US7956641B1 (en) 2005-04-28 2011-06-07 Cypress Semiconductor Corporation Low voltage interface circuit
US8063655B2 (en) * 2005-07-19 2011-11-22 Cypress Semiconductor Corporation Method and circuit for reducing degradation in a regulated circuit
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US7437620B2 (en) * 2005-11-30 2008-10-14 International Business Machines Corporation Method and system for extending the useful life of another system
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US8578137B2 (en) * 2006-11-03 2013-11-05 Intel Corporation Reducing aging effect on registers
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US7826288B2 (en) * 2007-03-09 2010-11-02 International Business Machines Corporation Device threshold calibration through state dependent burn-in
US20090099828A1 (en) * 2007-10-12 2009-04-16 Igor Arsovski Device Threshold Calibration Through State Dependent Burnin
US7849426B2 (en) * 2007-10-31 2010-12-07 International Business Machines Corporation Mechanism for detection and compensation of NBTI induced threshold degradation
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JP2011198406A (en) * 2010-03-18 2011-10-06 Toshiba Corp Semiconductor memory device and method for testing semiconductor memory device
US8456247B2 (en) 2011-01-19 2013-06-04 International Business Machines Corporation Monitoring negative bias temperature instability (NBTI) and/or positive bias temperature instability (PBTI)
US8659322B2 (en) * 2011-01-28 2014-02-25 Freescale Semiconductor, Inc. Memory having a latching sense amplifier resistant to negative bias temperature instability and method therefor
CN103424684B (en) * 2012-05-24 2015-12-09 中芯国际集成电路制造(上海)有限公司 The instable testing circuit of Bias Temperature and detection method
KR20140064270A (en) * 2012-11-20 2014-05-28 에스케이하이닉스 주식회사 Semiconductor memory apparatus
CN106531210B (en) * 2016-10-11 2019-11-05 苏州宽温电子科技有限公司 A kind of differential architecture storage unit improving p-type NVM memory NBTI effect
TWI738615B (en) 2021-02-04 2021-09-01 華邦電子股份有限公司 Semiconductor memory device
JP7012175B1 (en) * 2021-02-04 2022-01-27 華邦電子股▲ふん▼有限公司 Semiconductor storage device

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US6185712B1 (en) * 1998-07-02 2001-02-06 International Business Machines Corporation Chip performance optimization with self programmed built in self test
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FR2792760A1 (en) * 1999-04-23 2000-10-27 St Microelectronics Sa Memory circuit with optimized reading cycle, comprising means for providing internal signal for precharging bit line

Also Published As

Publication number Publication date
US6762961B2 (en) 2004-07-13
AU2003214221A1 (en) 2003-11-03
WO2003090230A2 (en) 2003-10-30
AU2003214221A8 (en) 2003-11-03
US20030198112A1 (en) 2003-10-23

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