WO2003100632A3 - Dual-processor based system and method of waking up components therein - Google Patents

Dual-processor based system and method of waking up components therein Download PDF

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Publication number
WO2003100632A3
WO2003100632A3 PCT/GB2003/002274 GB0302274W WO03100632A3 WO 2003100632 A3 WO2003100632 A3 WO 2003100632A3 GB 0302274 W GB0302274 W GB 0302274W WO 03100632 A3 WO03100632 A3 WO 03100632A3
Authority
WO
WIPO (PCT)
Prior art keywords
components
processor system
waking
dual
processor
Prior art date
Application number
PCT/GB2003/002274
Other languages
French (fr)
Other versions
WO2003100632A2 (en
Inventor
Paul Dale
Original Assignee
Sendo Int Ltd
Paul Dale
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GBGB0212260.4A external-priority patent/GB0212260D0/en
Application filed by Sendo Int Ltd, Paul Dale filed Critical Sendo Int Ltd
Priority to AU2003236890A priority Critical patent/AU2003236890A1/en
Publication of WO2003100632A2 publication Critical patent/WO2003100632A2/en
Publication of WO2003100632A3 publication Critical patent/WO2003100632A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W52/00—Power management, e.g. TPC [Transmission Power Control], power saving or power classes
    • H04W52/02—Power saving arrangements
    • H04W52/0209—Power saving arrangements in terminal devices
    • H04W52/0261—Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level
    • H04W52/0287—Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level changing the clock frequency of a controller in the equipment
    • H04W52/0293—Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level changing the clock frequency of a controller in the equipment having a sub-controller with a low clock frequency switching on and off a main controller with a high clock frequency
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Abstract

A method of waking up components in a dual-processor based system comprising a first processor system (310) to be activated. Upon activation, components in a second processor system (320) need to be activated. The method comprises initiating a wake-up process (405) and waking-up first processor system components, and generating an interrupt signal (420). The interrupt signal is used to wake-up second processor system components that are required to be woken for the wake-up process of the first processor system (310). The second processor system components are activated at, or before, a time when the first processor system requires the components to be activated. A dual processor based system is also described. In this manner, components used in a second processor system are awoken in a timely manner when they are needed in the awakening process of the first processor system. This prevents delay and reduces power consumption in a device.
PCT/GB2003/002274 2002-05-28 2003-05-27 Dual-processor based system and method of waking up components therein WO2003100632A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003236890A AU2003236890A1 (en) 2002-05-28 2003-05-27 Dual-processor based system and method of waking up components therein

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
GBGB0212260.4A GB0212260D0 (en) 2002-05-28 2002-05-28 System wakeup
GB0212260.4 2002-05-28
GB0214098A GB2382180B (en) 2002-05-28 2002-06-19 Processor system wake-up
GB0214098.6 2002-06-19

Publications (2)

Publication Number Publication Date
WO2003100632A2 WO2003100632A2 (en) 2003-12-04
WO2003100632A3 true WO2003100632A3 (en) 2004-05-13

Family

ID=29585826

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB2003/002274 WO2003100632A2 (en) 2002-05-28 2003-05-27 Dual-processor based system and method of waking up components therein

Country Status (2)

Country Link
AU (1) AU2003236890A1 (en)
WO (1) WO2003100632A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20090032415A (en) 2007-09-28 2009-04-01 삼성전자주식회사 Multi processor system having multiport semiconductor memory with processor wake-up function and therefore method

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4870570A (en) * 1983-01-24 1989-09-26 Sharp Kabushiki Kaisha Control system for multi-processor
WO1993025955A1 (en) * 1992-06-12 1993-12-23 Norand Corporation Portable data processor which selectively activates and deactivates internal modular units and application processor to conserve power
EP0677974A2 (en) * 1994-04-12 1995-10-18 Nokia Mobile Phones Ltd. Data buffering device between communicating processors in a cellular mobile telephone terminal
US5487181A (en) * 1992-10-28 1996-01-23 Ericsson Ge Mobile Communications Inc. Low power architecture for portable and mobile two-way radios
EP0757466A2 (en) * 1988-05-21 1997-02-05 Fujitsu Limited Mobile telephone terminal with power saving means
EP0895394A2 (en) * 1997-08-02 1999-02-03 Philips Patentverwaltung GmbH Radiotelephone
US6356538B1 (en) * 1998-03-30 2002-03-12 Oki Telecom, Inc. Partial sleep system for power savings in CDMA wireless telephone devices

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4870570A (en) * 1983-01-24 1989-09-26 Sharp Kabushiki Kaisha Control system for multi-processor
EP0757466A2 (en) * 1988-05-21 1997-02-05 Fujitsu Limited Mobile telephone terminal with power saving means
WO1993025955A1 (en) * 1992-06-12 1993-12-23 Norand Corporation Portable data processor which selectively activates and deactivates internal modular units and application processor to conserve power
US5487181A (en) * 1992-10-28 1996-01-23 Ericsson Ge Mobile Communications Inc. Low power architecture for portable and mobile two-way radios
EP0677974A2 (en) * 1994-04-12 1995-10-18 Nokia Mobile Phones Ltd. Data buffering device between communicating processors in a cellular mobile telephone terminal
EP0895394A2 (en) * 1997-08-02 1999-02-03 Philips Patentverwaltung GmbH Radiotelephone
US6356538B1 (en) * 1998-03-30 2002-03-12 Oki Telecom, Inc. Partial sleep system for power savings in CDMA wireless telephone devices

Also Published As

Publication number Publication date
AU2003236890A8 (en) 2003-12-12
AU2003236890A1 (en) 2003-12-12
WO2003100632A2 (en) 2003-12-04

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