WO2004001803A3 - Logic array devices having complex macro-cell architecture and methods facilitating use of same - Google Patents

Logic array devices having complex macro-cell architecture and methods facilitating use of same Download PDF

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Publication number
WO2004001803A3
WO2004001803A3 PCT/US2003/019478 US0319478W WO2004001803A3 WO 2004001803 A3 WO2004001803 A3 WO 2004001803A3 US 0319478 W US0319478 W US 0319478W WO 2004001803 A3 WO2004001803 A3 WO 2004001803A3
Authority
WO
WIPO (PCT)
Prior art keywords
logic
cells
line
clock
inverters
Prior art date
Application number
PCT/US2003/019478
Other languages
French (fr)
Other versions
WO2004001803A2 (en
Inventor
William D Cox
Original Assignee
Viasic Inc
William D Cox
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Viasic Inc, William D Cox filed Critical Viasic Inc
Priority to AU2003243683A priority Critical patent/AU2003243683A1/en
Publication of WO2004001803A2 publication Critical patent/WO2004001803A2/en
Publication of WO2004001803A3 publication Critical patent/WO2004001803A3/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1735—Controllable logic circuits by wiring, e.g. uncommitted logic arrays
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H03K19/17796—Structural details for adapting physical parameters for physical disposition of blocks

Abstract

Logic array devices having complex macro-cell architecture and methods facilitating use of same. A semiconductor device comprising an array of logic cells and programmable metal includes gate structures that are pre-wired, where, inputs and/or outputs are available for routing in programmable metal, possibly as part of a hybrid process. The device can also include selectable, in-line inverters, which can share the input/output tracks with logic inputs. A bubble-pushing algorithm can take ad-vantage of the selectable in-line inverters to reduce the number of inverters in a de-sign. In some embodiments, an embedded clock line is common to a plurality of logic cells. The clock line is terminated in a clock cell, which can include test logic, so that a clock group is formed. Flexibility to power down cells, or groups of cells can be provided by power traces with programmable connections.
PCT/US2003/019478 2002-06-19 2003-06-19 Logic array devices having complex macro-cell architecture and methods facilitating use of same WO2004001803A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003243683A AU2003243683A1 (en) 2002-06-19 2003-06-19 Logic array devices having complex macro-cell architecture and methods facilitating use of same

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US38984302P 2002-06-19 2002-06-19
US60/389,843 2002-06-19
US10/234,926 2002-09-04
US10/234,926 US6873185B2 (en) 2002-06-19 2002-09-04 Logic array devices having complex macro-cell architecture and methods facilitating use of same

Publications (2)

Publication Number Publication Date
WO2004001803A2 WO2004001803A2 (en) 2003-12-31
WO2004001803A3 true WO2004001803A3 (en) 2005-02-17

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Family Applications (1)

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PCT/US2003/019478 WO2004001803A2 (en) 2002-06-19 2003-06-19 Logic array devices having complex macro-cell architecture and methods facilitating use of same

Country Status (3)

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US (4) US6873185B2 (en)
AU (1) AU2003243683A1 (en)
WO (1) WO2004001803A2 (en)

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Also Published As

Publication number Publication date
AU2003243683A1 (en) 2004-01-06
US20070262789A1 (en) 2007-11-15
WO2004001803A2 (en) 2003-12-31
US20090210848A1 (en) 2009-08-20
US20050117436A1 (en) 2005-06-02
US6873185B2 (en) 2005-03-29
AU2003243683A8 (en) 2004-01-06
US7538580B2 (en) 2009-05-26
US7930670B2 (en) 2011-04-19
US7248071B2 (en) 2007-07-24
US20030234666A1 (en) 2003-12-25

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