WO2004001837A3 - Methods of forming electronic structures including conductive shunt layers and related structures - Google Patents

Methods of forming electronic structures including conductive shunt layers and related structures Download PDF

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Publication number
WO2004001837A3
WO2004001837A3 PCT/US2003/020790 US0320790W WO2004001837A3 WO 2004001837 A3 WO2004001837 A3 WO 2004001837A3 US 0320790 W US0320790 W US 0320790W WO 2004001837 A3 WO2004001837 A3 WO 2004001837A3
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WO
WIPO (PCT)
Prior art keywords
layer
conductive shunt
methods
including conductive
structures
Prior art date
Application number
PCT/US2003/020790
Other languages
French (fr)
Other versions
WO2004001837A2 (en
Inventor
Krishna K Nair
Glenn A Rinne
William E Batchelor
Original Assignee
Unitive Int Ltd
Krishna K Nair
Glenn A Rinne
William E Batchelor
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Unitive Int Ltd, Krishna K Nair, Glenn A Rinne, William E Batchelor filed Critical Unitive Int Ltd
Priority to AU2003256360A priority Critical patent/AU2003256360A1/en
Publication of WO2004001837A2 publication Critical patent/WO2004001837A2/en
Publication of WO2004001837A3 publication Critical patent/WO2004001837A3/en

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    • HELECTRICITY
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    • H01L23/00Details of semiconductor or other solid state devices
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    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528Geometry or layout of the interconnection structure
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
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    • H01L21/2885Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
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Abstract

Methods of forming an electronic structure may include forming a seed layer on an electronic substrate, and forming a conductive shunt layer on portions of the seed layer wherein portions of the seed layer are free of the conductive shunt layer. A conductive barrier layer may be formed on the conductive shunt layer opposite the seed layer wherein the conductive shunt layer comprises a first material and wherein the barrier layer comprises a second material different than the first material. Moreover, a solder layer may be formed on the barrier layer opposite the conductive shunt layer wherein the solder layer comprises a third material different than the first and second materials. Related structures are also discussed.
PCT/US2003/020790 2002-06-25 2003-06-23 Methods of forming electronic structures including conductive shunt layers and related structures WO2004001837A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003256360A AU2003256360A1 (en) 2002-06-25 2003-06-23 Methods of forming electronic structures including conductive shunt layers and related structures

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US39151102P 2002-06-25 2002-06-25
US60/391,511 2002-06-25

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WO2004001837A2 WO2004001837A2 (en) 2003-12-31
WO2004001837A3 true WO2004001837A3 (en) 2004-07-08

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US (4) US6960828B2 (en)
AU (1) AU2003256360A1 (en)
TW (1) TWI306654B (en)
WO (1) WO2004001837A2 (en)

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Publication number Priority date Publication date Assignee Title
AU2002228926A1 (en) * 2000-11-10 2002-05-21 Unitive Electronics, Inc. Methods of positioning components using liquid prime movers and related structures
WO2004001837A2 (en) * 2002-06-25 2003-12-31 Unitive International Limited Methods of forming electronic structures including conductive shunt layers and related structures
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US20080026560A1 (en) 2008-01-31
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US6960828B2 (en) 2005-11-01

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