WO2004006426A9 - Flexible method and apparatus for performing digital modulation and demodulation - Google Patents
Flexible method and apparatus for performing digital modulation and demodulationInfo
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- WO2004006426A9 WO2004006426A9 PCT/US2003/021055 US0321055W WO2004006426A9 WO 2004006426 A9 WO2004006426 A9 WO 2004006426A9 US 0321055 W US0321055 W US 0321055W WO 2004006426 A9 WO2004006426 A9 WO 2004006426A9
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
- H04B1/7097—Interference-related aspects
- H04B1/711—Interference-related aspects the interference being multi-path interference
- H04B1/7115—Constructive combining of multi-path signals, i.e. RAKE receivers
- H04B1/712—Weighting of fingers for combining, e.g. amplitude control or phase rotation using an inner loop
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
- H04B1/7097—Interference-related aspects
- H04B1/711—Interference-related aspects the interference being multi-path interference
- H04B1/7115—Constructive combining of multi-path signals, i.e. RAKE receivers
- H04B1/7117—Selection, re-selection, allocation or re-allocation of paths to fingers, e.g. timing offset control of allocated fingers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B2201/00—Indexing scheme relating to details of transmission systems not covered by a single group of H04B3/00 - H04B13/00
- H04B2201/69—Orthogonal indexing scheme relating to spread spectrum techniques in general
- H04B2201/707—Orthogonal indexing scheme relating to spread spectrum techniques in general relating to direct sequence modulation
- H04B2201/70701—Orthogonal indexing scheme relating to spread spectrum techniques in general relating to direct sequence modulation featuring pilot assisted reception
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B2201/00—Indexing scheme relating to details of transmission systems not covered by a single group of H04B3/00 - H04B13/00
- H04B2201/69—Orthogonal indexing scheme relating to spread spectrum techniques in general
- H04B2201/707—Orthogonal indexing scheme relating to spread spectrum techniques in general relating to direct sequence modulation
- H04B2201/70707—Efficiency-related aspects
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B2201/00—Indexing scheme relating to details of transmission systems not covered by a single group of H04B3/00 - H04B13/00
- H04B2201/69—Orthogonal indexing scheme relating to spread spectrum techniques in general
- H04B2201/707—Orthogonal indexing scheme relating to spread spectrum techniques in general relating to direct sequence modulation
- H04B2201/70707—Efficiency-related aspects
- H04B2201/7071—Efficiency-related aspects with dynamic control of receiver resources
Definitions
- the present invention is related to communication systems capable of communicating signals. More particularly, the present invention relates to a flexible method and apparatus for performing digital modulation and demodulation.
- conventional digital communication systems include a baseband subsystem in which received signals are demodulated and transmitted signals are modulated.
- Demodulators in baseband subsystems have been implemented using an application specific integrated circuit (ASIC) or a digital signal processor (DSP) or combination thereof.
- ASIC application specific integrated circuit
- DSP digital signal processor
- known demodulator implementations suffer from significant drawbacks.
- FIGURE 1 illustrates a conventional implementation of a spread-spectrum demodulator 1 0.
- the demodulator 1 0 includes a combiner 1 2 that combines symbols received from Fingers 1 , 2, through Finger N (hereinafter referred collectively as fingers 14). Fingers 14 are instantiations of hardware logic for each multi-path processing entity, or "path.”
- the combiner 1 2 de-skews or aligns in time the symbols from the fingers 1 4 and adds the symbols together to form an estimate of the transmitted symbol value. Once steady-state is reached, an output of the combiner 1 2 occurs synchronously with the symbol reception at the antenna.
- Demodulator 10 has several disadvantages.
- the demodulator 1 0 uses multiple, static instantiations of the fingers 14.
- the number of fingers 14 is selected based on the worst-case channel condition possible, representing the largest possible number of gates needed.
- MIMO multiple input multiple output antennas
- current conventional architectures have been instantiating more and more fingers. More fingers require more power.
- Another disadvantage of the demodulator 1 0 is a slow assignment or de-assignment of fingers 14, thereby wasting power. Turning on and off fingers 1 4 via assignment and de-assighment is a relatively slow process. As a result, there is a significant lag between a path dying and a finger shutting off. This results in higher power consumption with no corresponding gain in performance.
- An exemplary embodiment relates to a method of processing data based on programmed instructions.
- the method includes referencing a number of locations in memory by forming addresses and correct buffer mappings corresponding to separate buffers in the plurality of buffers, and communicating data from the referenced locations in memory to a processing unit.
- the processing unit concurrently receives inputs from the separate buffers in the plurality of buffers and outputs to another buffer in the plurality of buffers.
- Another exemplary embodiment relates to an apparatus operable to process communication signals.
- the apparatus includes a plurality of buffers, a controller including programmed instructions configured to reference a number of locations in memory by forming addresses and correct buffer mappings corresponding to separate buffers in the plurality of buffers, and a processing unit that concurrently receives inputs from the separate buffers in the plurality of buffers and outputs to another buffer in the plurality of buffers.
- Another exemplary embodiment relates to a system for processing communication signals.
- the system includes means for referencing a number of locations in memory by forming addresses and correct buffer mappings corresponding to separate buffers in the plurality of buffers, and means for communicating data from the referenced locations in memory to a processing unit, wherein the processing unit concurrently receives inputs from the separate buffers in the plurality of buffers and outputs to another buffer in the plurality of buffers.
- FIGURE 1 is a diagrammatic representation of a conventional spread spectrum demodulator
- FIGURE 2 is a diagrammatic representation of a multi- path processing system in accordance with an exemplary embodiment
- FIGURE 3 is a diagrammatic representation comparing the operation of a conventional demodulator with the demodulator of the system of FIGURE 2;
- FIGURE 4 is a diagrammatic representation of a minimal buffer operation in accordance with an exemplary embodiment
- FIGURE 5 is a diagrammatic representation of another exemplary buffer operation
- FIGURE 6 is a diagrammatic representation of an Accumulated Maximal Ratio Combining (A-MRC) processing operation in accordance with an exemplary embodiment
- FIGURE 7 is a diagrammatic representation of an Accumulated Maximal Ratio Combining (A-MRC) algorithm processing units in accordance with an exemplary embodiment
- FIGURE 8 is a diagrammatic representation of the Accumulated Maximal Ratio Combining (A-MRC) despreader of FIGURE 7;
- FIGURE 9 is a diagrammatic representation of the Accumulated Maximal Ratio Combining (A-MRC) algorithm of FIGURE 6 in greater detail;
- FIGURE 10 is a diagrammatic representation of the Accumulated Maximal Ratio Combining (A-MRC) algorithm processing units of FIGURE 7 in greater detail;
- FIGURE 1 1 is a diagrammatic representation of a conventional finger for Multiple Inputs (Ml);
- FIGURE 1 2 is a diagrammatic representation of a conventional Multiple Outputs (MO) Receiver;
- FIGURE 1 3 is a diagrammatic representation of a processor for Accumulated Maximal Ratio Combining (A-MRC) with MIMO in accordance with an exemplary embodiment;
- FIGURE 14 is a diagrammatic representation of a first phase of an exemplary windowed search process
- FIGURE 1 5 is a diagrammatic representation of a second phase of an exemplary windowed search process
- FIGURE 1 6 is a diagrammatic representation of a windowed searcher implementation in accordance with an exemplary embodiment
- FIGURE 1 7 is a diagrammatic representation comparing a frequency search feature of an exemplary embodiment to conventional processing
- FIGURE 1 8 is a diagrammatic representation of a convergent searcher operation in accordance with an exemplary embodiment
- FIGURE 1 9 is a diagrammatic representation of a soft combiner operation included in the convergent searcher operation of FIGURE 1 8;
- FIGURE 20 is a diagrammatic representation of a convergent searcher implementation in accordance with an exemplary embodiment
- FIGURE 21 is a state diagram depicting operations in the convergent searcher implementation of FIGURE 1 8;
- FIGURE 22 is a diagrammatic representation of a communication system in accordance with an exemplary embodiment
- FIGURE 23 is a diagrammatic representation of the processor of the communication system of FIGURE 22;
- FIGURE 24 is a diagrammatic representation of the processor of the communication system of FIGURE 22;
- FIGURE 25 is a state diagram depicting operation states of the control state machine of the communication system of FIGURE 23;
- FIGURE 26 is a diagrammatic representation of a buffer operation in accordance with an exemplary embodiment
- FIGURE 27 is a diagrammatic representation of the address generators of FIGURE 24;
- FIGURE 28 is a diagrammatic representation of Unit A of the processor of FIGURE 23;
- FIGURE 29 is a diagrammatic representation of the input shifter of the processor of FIGURE 23;
- FIGURE 30 is a diagrammatic representation of the output shifter of the processor of FIGURE 23;
- FIGURE 31 is a diagrammatic representation of Unit B of the processor of FIGURE 23;
- FIGURE 32 is a diagrammatic representation of Unit C of the processor of FIGURE 23;
- FIGURE 33 is a diagrammatic representation of a timing diagram
- FIGURE 34 is a state diagram depicting operation states for the instruction set of the processor of FIGURE 23;
- FIGURE 35 is a state machine diagram for an 802.1 1 a/b/g multi-mode program in accordance with an exemplary embodiment;
- FIGURE 36 is a state diagram for OFDM only transmit processing in accordance with an exemplary embodiment.
- FIGURE 2 illustrates a multi-path communication processing system including a processor 20 that receives signals in the form of sub-chip samples from sample buffers 22.
- Sample buffers 22 receive timing input from a master timer 24 and chip samples (modulated signals in a spread spectrum system) from a receiver 26.
- the receiver 26 can be a radio frequency (RF) or an intermediate frequency (IF) type receiver.
- the chip samples provided to sample buffers 22 can be decimated or interpolated.
- a control 28 provides feedback to the receiver 26.
- Sample buffers 22 can store an amount of data referred to as a "Symbol Group.”
- sample buffers 22 make it possible for the processor 20 to not be synchronously clocked by the sample rate because the processor 20 can obtain data from sample buffers 22 as needed. In this way, the processor 20 operates as more like a processor than an application specific integrated circuit (ASIC), working at the fastest clock rate that the silicon technology will support.
- ASIC application specific integrated circuit
- FIGURE 3 illustrates operation of the processor 20 compared to operation of a conventional synchronous implementation.
- the processor 20 does the required amount of processing at the fastest clock rate available in a serial fashion. This speed enables the processor 20 to finish its processing before the time needed for the next buffer to fill and require servicing (i.e., a Symbol Group Duration).
- the processor 20 can be shut down (i.e., the clock is gated off) until the completion of the Symbol Group Duration.
- the given amount of processing may vary from Symbol Group to Symbol Group.
- the processor 20 is configured to provide dynamic path processing.
- This dynamic path processing can be referred to as a "virtual finger" feature because the multi-path communication paths, or fingers, are not actual hardwired circuits but rather paths defined using various algorithms.
- the clock is disabled. This can be seen in FIGURE 3 in the shaded "Shut Down" region.
- FIGURE 3 shows the shaded "Shut Down" region.
- Another example of the dynamic processing ability of the processor 20 is the dynamic setting of bit-widths. Dynamically processing the bits is particularly beneficial since less bits are usually needed to produce a decodable output than the instantaneous worst case. By processing less bits on average, less power is consumed.
- Bits can be treated like paths, in that they can be separately processed, because of the linearity in most demodulation processing (e.g., de-spreading, accumulation, MRC) such that many bits can be divided into sub-units of bits. If the processor 20 were designed in this fashion, it would be composed of small bit-width circuitry. In the presence of a fade, where more bits are necessary on a given path, the same path would be processed several times, each on a different sub-unit of bits (i.e. first the LSB sub-unit and last the MSB sub-unit). Each time a sub-unit is processed, the de- spreaded output is appropriately shifted and accumulated into a symbol buffer. Such processing is simply another kind of Accumulated Maximal Ratio Combining (A-MRC) algorithm with the paths being replaced by sub-units of bits in the algorithm.
- A-MRC Accumulated Maximal Ratio Combining
- processor 20 can dynamically set bit-widths is by using a programmable ASIC. If only a few bits are needed, the data is shifted to the right such that the number of toggling bits in the demodulator are reduced.
- the processor 20 can offload some of the low processing intensive operations that are typically forced into ASIC.
- the buffering nature of the processor 20 operation can be exploited to eliminate the stringent real-time DSP deadlines that typically force these operations into ASIC. Because samples are buffered, stringent real-time processor deadlines are no longer in force.
- the processor can offload many relatively non- computationally intensive tasks including Multipath Finger Assignment, Equalization/lnterpolation/MRC Tap Weight Calculation, NCO Stride Selection, and Time Tracking. Offloading this functionality into the processor 20 represents a saving in silicon area, yielding lower cost in addition to reduced development risks. Incorporating a processor into the demodulation algorithm reduces power consumption, too.
- FIGURE 4 illustrates the operation of an exemplary buffering scheme.
- a "buffer” is a memory element including two sets of data / address ports - one for read and one for write.
- the buffer does not have to support simultaneous read / write access. Any given cycle is either read or write or both.
- the selection criteria of this exemplary buffer scheme is to use a small amount of RAM for the chip memory, yet have very simple operation of the processor. At any given time, the processor is processing on two of the buffers that are logically functioning as one.
- a state 40 in FIGURE 4 shows that during iteration N, Buffer 1 and Buffer 2 are serving as a single logical data source. With this scheme, all symbols whose earliest path begins in Buffer 1 are processed to completion (all multi-paths are combined), which entails using the chips in Buffer 2 for the later paths of these symbols. Those symbols whose earliest paths occur in Buffer 2 are not processed until iteration N + 1 in a state 42 as shown in FIGURE 4.
- Buffer 3 is receiving the samples occurring during the processing of the logical combination of Buffer 1 and Buffer 2.
- the processor processes those symbols whose earliest path are in Buffer 2 while using the contents of Buffer 3 as the necessary later arriving paths which also must be present to complete the symbol processing.
- these operations allow for complete symbol processing during any iteration which eliminates the requirement of many state variables to keep track of the partial processing between iterations, and more complicated control logic to allow "fast-forwarding" through states to reach partial symbols.
- the larger sample buffer size is used when other requirements drive the necessity of a larger buffer size.
- the driving requirement of sample buffer size is the multi-path delay spread such that all data for symbol processing is accessible to the processor simultaneously.
- burst-pilot wireless technologies such as 1 xEV-DO
- the burst spacing is the more stringent requirement for determining buffer size.
- the processor must have simultaneous access to all the data stored between pilot bursts, in addition to the later pilot burst for linear interpolation of the channel estimate to be performed which is vital for demodulation performance for the automatic frequency control (AFC) drift that is ever-present.
- AFC automatic frequency control
- FIGURE 5 illustrates an exemplary buffering scheme for wireless technologies that use burst-pilot.
- Buffers 1 , 2, and 3 serve as a single logical data source to the processor 20 (FIGURE 2).
- Buffers 4 and 5 serve as a single logical memory element that captures the synchronously arriving samples from the ADC. All symbols whose earliest arriving multi-path components are contained in Buffers 1 and 2 are completely processed during iteration N. .
- This operation uses the samples in Buffer 3 in order to process the later arriving multi-path components.
- the processing of the symbols whose earliest arriving multi-path components are contained in Buffer 3 is deferred until iteration N + 1 . Therefore, during iteration N + 1 , Buffers 3, 4, and 5 serve as the single logical entity for processing.
- FIGURE 6 illustrates operations in an Accumulated Maximal Ratio Combining (A-MRC) procedure of the processor 20 described with reference to FIGURE 2.
- A-MRC Accumulated Maximal Ratio Combining
- operations are performed serially.
- the number of paths, N is set to zero.
- a pilot channel for path N is processed, yielding a channel estimate.
- Operation 62 continues until all known multi-paths are estimated.
- the number of paths, N can vary over time.
- channel estimates for a set of M relevant multi-paths are used in data de-spreading of an operation 64.
- multi-paths can refer to communication signals from the one base station, other base stations, one antenna, or other antennas.
- data for path M is processed while multiplying by the channel estimate.
- Operation 64 continues until all relevant multi-paths for all channels are demodulated.
- the processor sleeps until the next symbol group is available.
- FIGURE 7 shows exemplary processing blocks of the processor 20 that are specific to the A-MRC algorithm.
- the Master Timer 24 is used to determine the beginning of the Processing Interval.
- the processor 20 begins processing of sub-chip samples.
- An address generator 52 decimates the samples to the correct rate and phase by initializing to the buffer address corresponding to the desired sub-ship phase. To keep proper sub-chip phase alignment, the address generator 52 is advanced the number of sub-chips per chip.
- a despreader 56 and a channel estimator 58 serially despread and accumulate the paths into a Symbol Buffer 54.
- FIGURE 8 illustrates the despreader 56 for the A-MRC algorithm.
- the despreader 56 operates by multiplying by the known pilot sequence, and inserting the correlation value into a channel estimator 58.
- the despreader 56 multiplies the on-phase sub-chip samples by the correct PN and channelization code (e.g., Walsh, OVSF, etc.) and outputs the value at symbol rate.
- the complex symbols are then multiplied by the channel estimate from the path and accumulated into the symbol buffer 54. In other words, the complex symbols are read, added to the current value, and written back into the symbol buffer 54.
- the MRC estimates are valid at the end of processing the relevant multi-paths and are ready for symbol processing (e.g., deinterleaving, depuncturing, and decoding).
- FIGURE 9 illustrates in more detail operations performed in the Accumulated Maximal Ratio Combining (A-MRC) procedure described with reference to FIGURE 6.
- A-MRC Accumulated Maximal Ratio Combining
- a state 65 the channel estimate for path N is multiplied by the despread data of path N, the accumulator is bypassed, and the output is sent to intermediate buffers.
- symbols from the path N are accumulated over multi-paths and base stations.
- the current MRC accumulation of the group of symbols (which are initialized to zero for processing of the first path) from the intermediate buffer are added to the despread and channel estimated symbols from the intermediate buffer, the accumulator is bypassed, and output is sent to intermediate buffers.
- States 63-66 are repeated until all N relevant multi-paths and base stations are processed at which point, the current MRC accumulation is the final accumulation and this value is output to the symbol processor.
- this process may be repeated in the case where a receiver is demodulating several channels After that, in a state 67, the processor 20 sleeps until the next processing interval.
- FIGURE 10 illustrates in more detail the processing blocks specific to the A-MRC algorithm described with reference to FIGURE 7.
- the processor 20 includes a state machine control 80 configured to change states as described with reference to FIGURE 8.
- the processor 20 also includes multiplexers (MUX) 82, 83, and 85 directing input from the sample buffers 22, intermediate buffers 86, and despreader sequence generator 88.
- MUX multiplexers
- a bypassable accumulator 84 directs symbols to a decoder and intermediate buffers 86.
- the bypassable accumulator 84 can output channel estimates, current and incomplete accumulated symbols, despread data symbols, despread pilot symbols, or channel estimated data symbols for a particular path.
- the sample buffer 22 inputs pilot symbols to MUX 82 and the despread sequence generator 88 inputs despread data to MUX 83. These inputs are multiplied and sent to bypassable accumulator 84 via MUX 85.
- the bypassable accumulator 84 outputs accumulated symbols to intermediate buffers 86. The control of where results are output is dependent upon the state diagram described with reference to FIGURE 9.
- the A-MRC algorithm serially accumulates to the correct MRC value.
- Each iteration of the processor 20 in the situation extracts a single multi-path component:
- n is the extracted symbol estimate of the ⁇ h symbol for the rrth multi-path
- c(.) is the contents of the chip sample buffer
- J is the spreading factor
- s(i) is the beginning of the correlation for the th symbol
- Wn is the multi-path delay
- d is the decimation rate
- pj is the pseudo-nose sequence multiplied by the orthogonal channelization code.
- This value is weighted and accumulated in the symbol buffer 54 of the processor 20 according to the following recursion relation
- n is the channel estimate of multipath n during the I th symbol.
- the resultant MRC symbol attains its final value after the number of useful multipath iterations N as
- criteria can include not to process paths that have an instantaneous power in excess of Ti dB below the strongest instantaneous multi-path component. Paths that are substantially below a strongest path contribute little to the SNR of the resultant (especially in an interference dominated scenario) .
- Another criteria can be to rank paths in order of strongest to weakest instantaneous powers and not process paths once a threshold of T 2 has been reached. This represents a condition where de-codability has been reached and there is no need for processing any more multi-path components.
- Ml Multiple Inputs
- MO Multiple Outputs
- TX Multiple transmit
- RX Multiple receive
- MISO Multiple Inputs Single Output
- SIMO Single Input Multiple Outputs
- FIGURE 1 1 illustrates a conventional finger supporting multiple input antenna (Ml). As can be seen, such a finger is forced to contain two multipliers 70 and 72 plus some transformation logic to properly take advantage of the diversity. This results in at least two disadvantages. First, this results in increased cost of an additional multiplier and transform logic per finger. Second, the conventional finger, when enabled, is forced to always process all the incoming antenna path streams. This results in inefficiency in terms of power consumption.
- FIGURE 1 2 illustrates a conventional receiver supporting multiple output antenna (MO).
- MO multiple output antenna
- FIGURE 1 3 illustrates a receiver 75 supporting full- fedged MIMO.
- the receiver 75 treats paths emanating from different BS antennas as well as paths coming from different RX antennas almost the same as another multi-path.
- Ml the only addition to the receiver 75 compared to the processing system of FIGURE 7 is the necessity of a transformer 77 to handle such operations as STTD in WCDMA.
- the A- MRC algorithm can be almost exactly applied for Ml with the difference that twice the number of paths could potentially be processed.
- MO the only addition to the receiver 75 compared to the processing system of FIGURE 7 is that the sample buffer 22 is doubled to support data coming in from both RF chains. As a result, there is substantial cost savings.
- processor 20 is configured for operation with a "burst-pilot" signal where the information sent from the communication base-station used to estimate the cellular channel is time-division multiplexed so that it is present and not present in the forward- link signal at different times.
- processor 20 is configured for operation with a "continuous-pilot" where the information sent from the communication base-station used to estimate the cellular channel is always present in the forward link signal transmitted by the base-station.
- Finding the multi-path components in a timely manner so that they may contribute to the demodulation of the signal is one of the design challenges in a CDMA receiver implementation.
- Searching refers to the process of finding multi-path components in a rapidly changing environment.
- the processor 20 allows for enhanced searcher operation.
- the convergent searcher function described below with reference to FIGURES 18-19 is a distinct algorithm that allows for fast acquisition of multi-path components and enhances the performance of the CDMA receiver in a rapidly changing multi- path environment.
- the processor 20 includes a scheme that does not require separate buffering for the windowed searching operation.
- conventional implementations generally consist of instantiations of "fingers" operating synchronously upon the samples in parallel.
- the processor 20 serially processes each multi-path one at a time where each iteration through the data is termed a "virtual finger.”
- channel estimates performed by conventional ASIC hardware are performed by dedicated hardware in addition to the demodulation specific circuitry.
- the processor 20 does not have this limitation. The same circuitry can be used both for demodulation and channel estimation.
- the way that the samples are buffered helps in the operation of the processor 20.
- a three buffer scheme is used which gives access to the entire delay spread of the sub-chip samples to be demodulated by the processor 20. This minimal buffering scheme avoids the time delay of a two buffer scheme where the two physical buffers switch roles once the buffer receiving chips is full. Further, the buffering scheme has an entire multi-path spread worth of digital samples available during each processing iteration.
- a single dual-port memory is used to implement the buffering scheme.
- FIGURE 14 illustrates a first phase of an exemplary windowed search process.
- the process takes a set of digital complex samples 92, 94, 96, 98, and 1 00 and determines the correlation of these samples with various hypothesis.
- all combinations of 4 adjacent chips are computed for a number of adjacent sets of 4 chips.
- FIGURE 1 5 illustrates a second phase of the exemplary windowed search process.
- the computed combinations from phase one are used to find correlations over multiples of 4 chips.
- the correlations can be coherent and non-coherent. In the example shown, 128 correlations are found.
- a PN sequence 1 04 is received by shift registers 1 06.
- Shift registers 1 06 direct processed chips from the PN sequence 1 04 to a number of RAM devices (e.g., RAM 1 -32) .
- RAM device 1 08 includes, for example, partial sums of chips 1 -4.
- RAM device 1 1 0 includes partial sums of chips 5-8.
- RAM device 1 1 2 includes partial sums of chips 1 25-1 28. Correlations from the RAM devices are combined using a combining apparatus 1 24.
- the number of computations becomes close to a factor of 4 reduction relative to conventional algorithms, given a sufficiently large set of
- the processor 20 described with reference to FIGURE 2 can perform a windowed search.
- An additional search functionality referred to as a convergent searcher is described below with reference to FIGURES 20-21 .
- the processor 20 receives samples from sample buffers 82 and 84.
- the sample buffer 82 provides even phase samples and the sample buffer 84 provides odd phase samples.
- a 2x2 permute block 86 supplies a demodulator 88 with on-time samples such that the signal energy is maximized.
- the other set of sample buffers is for use with a searcher 89.
- the searcher 89 gets either the odd phase or the even phase samples, whichever is not used by the demodulator 88, whenever the searcher 89 and the demodulator 88 contend for the same memory block.
- the searcher 89 After acquisition, the searcher 89 operates on samples that are either 1 /8 th chip early or 1 /8 th chip late, but this slight degradation in energy impacts operation of the searcher 89 only minimally.
- the windowed searcher function performs a sufficient number of correlations, then shuts down until a new block of data is available. As such, hardware idle cycles are avoided.
- a buffer 87 is used to store digital samples obtained at a different frequency than an original frequency. Using an additional buffer has the advantage of storing samples for possible use later. Alternatively, the digital samples obtained at a different frequency can be placed in sample buffers 82 and 84 for a receive iteration and a processing iteration.
- FIGURE 1 7 illustrates a frequency search feature of an exemplary embodiment compared with frequency search accomplished by conventional processing.
- the processor 20 allows for baseband processing of signals while the RF is either shut-off or tuned to a different frequency.
- One benefit of this technique is a more effective inter-frequency search.
- FIGURE 1 7 shows that a search for base stations at other frequencies can be performed "off-line" after an initial buffer fill.
- One benefit is that the time-consuming process of testing various PN offsets via coherent and non-coherent combinations of correlations can be performed while tuned to the demodulation frequency. This potentially enhances system performance by either: reducing the amount of time necessary for making other frequency measurements, or allowing for less data loss from the current frequency assignment during other frequency measurements.
- the frequency search feature utilizes the same sample buffers used with the original frequency.
- the sample buffers receive the digital samples from the new frequency in one iteration and process them in a next iteration. After the original frequency is returned to, the sample buffers continue in use.
- a separate buffer is used for new frequency, such as buffer 87 described with reference to FIGURE 1 7. Use of a separate buffer has the advantage of maintaining the digital samples received at the new frequency even after returning to the original frequency.
- FIGURE 1 8 illustrates a convergent searcher operation.
- a received chip, r n is multiplied by channel reliability, R, to obtain a channel measurement, Schann ⁇ i.
- Channel reliability can be computed from the equation:
- the convergent searcher operation converges to the correct PN state using noisy chip measurements of the pilot.
- Channel measurements are used as a soft input and added to a soft output feedback from a soft combiner 91 .
- This soft input is used to compute log-likelihoods.
- the soft combiner 91 performs a mod 2 addition to a group of channel measurements, Sn-i though Sn-15.
- the soft combiner 91 can be implemented by a series of soft XOR operations as described with reference to FIGURE 1 9.
- a soft XOR operation is a combining operation where the output ST from inputs Si and S 2 is defined by the following mathematical relationship:
- the soft XOR operation is implemented via a look-up-table.
- the convergent searcher operation of FIGURE 1 8 acquires PN synchronization without a priori knowledge of a last known PN like conventional searchers.
- the convergent searcher operation is capable of finding dominant multi-paths in fewer operations than a windowed searcher operation.
- Other advantages possible by the convergent searcher operation include the following. First, the operation provides for rapid acquisition of strong pilots that may be missed by a conventional windowed searcher when the path comes in rapidly. Second, the operation enables neighbor set maintenance during idle mode to be performed much more rapidly, which results in a 2 x increase in stand-by time for a mobile device. Third, the operation provides for rapid acquisition.
- FIGURE 1 9 illustrates a detailed implementation of the soft combiner 91 of FIGURE 1 8.
- the convergent searcher operation of FIGURE 1 8 is specific to the PN I (In-Phase) sequence for and defined by the recursion:
- the Ec/No for quick convergence (around 0 dB) of this technique is higher than the power at which the pilot currently operates.
- the base station dedicates slots of time at which the pilot signal is transmitted at 1 00% of the operating power.
- FIGURE 20 illustrates an exemplary implementation of the convergent searcher operation by the processor 20.
- the convergent searcher 90 receives samples including a phase rotation from a subtraction of samples from the sample buffers 22 and known paths from a FIR block 98.
- FIR (finite impulse response) block 98 is a pulse shaping filter.
- Known paths 94 are re-modulated by a re-modulator 96 and provided to the FIR block 98 along with channel estimates.
- FIGURE 21 illustrates a state diagram depicting convergent searcher operations performed by the processor 20.
- operations 1 00 and 102 the current set of known paths (which is empty during acquisition) is re-modulated and subtracted out. This separation aids in finding the weaker multi-paths once the stronger ones have been detected. In addition, the instantaneous fading of strong multi-paths aids in this process.
- phase rotation is introduced before the convergent searcher block because phase rotation of the multi-path is not known.
- phase rotation hypothesis is iterated upon. Once the phase rotation aligns with the phase of the strongest unknown pilot, convergence is indicated. Hard decisions are made on the soft-decision states, and this state is mapped to a PN phase in an operation 1 06 which is sent to the windowed searcher for verification and accurate measurement.
- the processor 20 described with reference to FIGURE 2 can be adapted for use with 802.1 1 specifications.
- the adapted processor is referred to as processor 1 20 and is described with reference to FIGURE 22.
- 802.1 1 refers to a family of specifications developed for wireless LAN technology.
- 802.1 1 specifies an over-the-air interface between a wireless client and a base station or between two wireless clients.
- 802.1 1 applies to wireless LANs and provides 1 or 2 Mbps transmission in the 2.4 GHz band using either frequency hopping spread spectrum (FHSS) or direct sequence spread spectrum. (DSSS) .
- FHSS frequency hopping spread spectrum
- DSSS direct sequence spread spectrum
- the 802.1 1 a specification is an extension to 802.1 1 that applies to wireless LANs and provides up to 54 Mbps in the 5GHz band.
- 802.1 1 a uses an orthogonal frequency division multiplexing encoding scheme rather than FHSS or DSSS.
- the 802.1 1 b specification (also referred to as 802.1 1 High Rate or Wi-Fi) is an extension to 802.1 1 that applies to wireless LANS and provides 1 1 Mbps transmission (with a fallback to 5.5, 2 and 1 Mbps) in the 2.4 GHz band.
- 802.1 1 b uses only DSSS.
- the 802.1 1 g specification applies to wireless LANs and provides 20 + Mbps in the 2.4 GHz band.
- the processor 1 20 includes features, such as branch support, indirect addressing via dynamic initialization of address generators, instruction pointers, vector-oriented instructions, configurable data path, and customized processing units.
- Vector-oriented instructions refers to execution of multi-element operations, thereby avoiding frequent access of program memory.
- the processor 1 20 can include processing units that are customized for the common vector processes inherent to demodulation.
- a Unit A is optimized for a convolution operation where a convolution output is calculated each clock.
- a Unit B is optimized for FFT functionality where a Radix-4 butterfly is performed each clock.
- a Unit C is optimized for other vector operations including: de-spreading, vector addition, vector subtraction, dot product, and component-by-component multiplication.
- each of the units have individual clock-trees that are implicitly enabled by the instruction set when a particular unit is used.
- FIGURE 20 illustrates an exemplary system incorporating the processor 1 20.
- the processor 1 20 performs demodulation operations.
- a master control within the processor 1 20 fetches instructions from a program RAM and executes the instructions via processing units A, B, and C.
- the input to the processing units is either from buffers that contain the original samples from the A/D, or from other buffers that contain intermediate results.
- the communication symbols are burst over to a symbol processor 1 22.
- the symbol processor 1 22 does the de-mapping, de- interleaving, and decoding and, at this point, the decoded bits are sent to a MAC (media access control) 1 24.
- the processor 1 20 is used to perform the FFT of the transmitter functionality.
- FIGURE 23 illustrates a portion of the processor 1 20 including buffers 1 32, a Unit A 1 34, a Unit B 1 36, a Unit C 1 38, a master control 140, a program memory 142, an ARM interface 144, and buffers 146.
- the master control 1 40 controls the processor 1 20.
- the master control 1 40 controls the sequence of instructions in program memory from either sequential incrementing of the Instruction Pointer or Conditional/Unconditional Branching from the instructions in program memory.
- the master control 1 40 also controls the synchronization of the processor 1 20 with the synchronous sample control and the routing of the parameters in the instruction bus to the appropriate places in other blocks.
- the master control 1 40 also contains the state machine responsible for operating multi-cycle instructions.
- the Instruction Pointer is a state variable describing the current instruction in program memory to be executed.
- the Instruction Pointer is adjusted by either a sequential increment or based upon program flow control.
- the Instruction Pointer is stalled during the operation of a multi-cycle vector operation.
- FIGURE 24 illustrates a portion of the processor 1 20 including address generators 1 52, switches 1 54, and switches 1 56.
- FIGURE 25 shows exemplary operation states of the master control state machine 1 40. From State 1 (SLEEP state), a signal indicates that a buffer fill has occurred, starting an iteration and transition to State 2 (Program RAM Access). The following events occur during State 2: Initialization of Address Generators from the instruction fields, Initialization of Vector Operation Length Counter, turning the correct clock-trees on, setting of appropriate memory switches, and setting of appropriate memory enables and proper selection of R/W.
- State 1 SLEEP state
- State 2 Program RAM Access
- the Input/Combine/Output buffers are in place and enabled for read/write as appropriate.
- the address generators are at the correct values for fetching data from the buffers appropriate for the particular vector arithmetic being executed, and the output of this vector arithmetic is sent to the correct address of the appropriate buffer.
- the Maxjndex and Status Time Stamps can be used as either the input source or the combine source in lieu of buffers.
- one of the following 3 registers of the Address Generators can be the output in lieu of buffers: AGJnputJnitial, AG Comb lnitial, and AG Comb Stride.
- the processor 1 20 has access to two of the buffers that are logically functioning as one.
- the buffering of scheme of FIGURE 24 is substantially the same as the buffering scheme described with reference to FIGURE 4.
- Buffer 1 and Buffer 2 are serving as a single logical data source for the processor 1 20 operation.
- Those symbols whose earliest paths occur in Buffer 2 are not processed until iteration N + 1 as shown in FIGURE 26.
- Buffer 3 is receiving the samples occurring during the processing of the logical combination of Buffer 1 and Buffer 2.
- the processor 1 20 processes those symbols whose earliest sample is in Buffer 2 while using the contents of Buffer 3 as the necessary later arriving samples which also must be present to complete the symbol processing.
- the input buffers look like a contiguous logical buffer to the instruction set. Therefore, the master controller 1 40 keeps track of whether the address generator assigned to sample buffer has wrapped.
- Buffers 7-10 are channel asynchronous buffers. These are the subset of buffers that the instruction set references specifically and are not directly loaded with A/D samples.
- the address to these buffers are generated from the address generators 1 52.
- the mapping of the physical RAMs to its role is set by the switches 1 54 based upon fields in the processor 1 20.
- FIGURE 24 shows the role of the address generators used for the buffers.
- the address generator router (switches 1 54) is responsible for routing the address generator output to the correct RAM. The following are the possible routing options coupled with the corresponding instruction fields. As shown in FIGURE 24, there are a number of possibilities for the address lines of each of the RAMs (each possible source is assigned a number between 1 -5) . This would most likely correspond to a MUX in front of each of the RAMs with the switch settings enforcing one of the options shown in the figure.
- the address generators 1 52 are instantiated three times -a generator 1 58 for input, a generator 1 60 for combine, and a generator 1 62 for output.
- the address generators 1 52 form the vector that can be expressed in MATLAB notation as a:b:c which means that a is the initial address, b is the "stride” through the buffer (the value the address generator adds each clock of the vector operation), and c is the ending value which is a dependent parameter of the vector operation length.
- FIGURE 27 illustrates a more detailed view of address generators 1 52.
- Address generators 1 52 can be directly loaded with a particular initial value and stride.
- the address generators 1 52 can have an initial value and stride loaded indirectly via the output of a previous Unit C operation.
- the register load field in the instruction is set to allow an "indirect" address mode access during a future instruction.
- an indication is sent to the master control 1 40 in case the wrapping was due to an access of the logical sample Buffer so that the master control 1 40 may update the buffer enables and R/W to reflect the current physical buffer.
- an offset can be added to the address output of the previous buffer which now becomes a:mod(. c /oor(b/64) ', wrapping _rate:c + offset.
- the offset addition may be a concatenation of LSB's and MSB's so that an adder would not be physically required (i.e., the offset would be an integral multiple of 2 n would n is the number of LSBs.)
- FIGURE 28 illustrates Unit A.
- Unit A 1 34 is the vector instruction engine responsible for performing a convolution (aka FIR filtering).
- An 8-tap FIR is performed in this mode as the constituent operation.
- Tap Loading the master controller 140 asserts a signal for the duration of the vector operation (which will be set to 8 to load all of the taps.) This signal causes the shifting in of taps values from the Input Buffer.
- FIR Operation the input of the FIR operation is physically from the Single Port Switch (input) and determined logically from the instruction field. This is the stream of data that is convolved with the taps. The convolved stream is added to the data stream from the Single Port Switch (combine) and determined logically from the instruction field.
- the master controller 1 40 asserts the signal Unit A FIR for the duration of the vector operations. This signal causes the shifting of the Input Buffer contents through the data path with the calculated FIR filter value appearing at the output.
- FIGURE 29 illustrates the input shifter that allows the left shifting of the input data by 2, the right shifting of the data by 5, and everything in between.
- a saturation detect follows the left shifting operation to eliminate the need for saturation detect upon inversion.
- the bits in the SELECT field of the instruction map directly to mux settings as shown.
- FIGURE 30 illustrates the output shifter that allows the right shifting of the data by any shift between 0 and 7 inclusive.
- the bits in the SELECT field of the instruction map directly to mux settings as shown.
- the Output Shifter supports saturation detection for the situation where the output does not fit within the 1 0 LSBs after shifting.
- FIGURE 31 illustrates Unit B.
- Unit B handles the FFT operation which takes its input from one of two quad-port RAMs (Buffer 8 or Buffer 9) and outputs to one of two quad-port RAMs (Buffer 8 or Buffer 9).
- the addresses for Unit B can actually be generated from the Unit B Augmented Address Generation.
- the Twiddle Factors sit in a separate ROM because they require 80 bits access (unlike the Utility RAM) .
- the Radix-4 FFT engine is optimized such that 8 complex additions are performed to produce 4 outputs.
- the Radix-4 consists of 2 sets of cascaded adders.
- the first set of adders produce the following partial sums based on the 4 complex inputs:
- a second set of adders computes the outputs based upon the partial sums as:
- FIGURE 32 illustrates Unit C which serves as the vector instruction engine for those vector operations not specifically contained in Unit A (FIR functionality) and Unit B (FFT functionality).
- the maximum circuitry in Unit C keeps track of the max and the index of the max for a Unit C vector operation.
- a Max Value Exceed notification is sent to the Master Control which causes Master Control to latch the current value of the Vector Instruction Counter.
- Table 1 below is a representation of the vector engine processing of Unit C.
- the inputs to the engine come from the buffers that are switched in as the Input Buffer and the Combination Buffer and are referred to as X and Y respectively in the Table.
- the output of the vector engine goes to the buffer that is switched in as the Output Buffer which is referred to as Z in the table.
- the intermediate variables A,A',A",B,B'",C,D, and D" are not directly output, rather are used to represent the processing of the Unit C vector engine.
- Unit C receives its stream of input from the output of the Single Port Switch (input) depicted in FIGURE 23.
- the Input Address generator is used to index into the appropriate buffer and is represented in the Table via the MATLAB notation X(a1 :b1 :c1 ) which means that a1 is the initial address, b1 is the "stride” through the buffer (the value the address generator adds each clock of the vector operation), and d is the ending value which is a dependent parameter of the Vector Operation Length.
- Unit C receives its stream of combine input from the output of the Single Port Switch (input) depicted in FIGURE 20.
- the Combination Address generator is used to index into the appropriate buffer and is represented in the Table via the MATLAB notation Y(a2:b2:c2) which means that a2 is the initial address, b2 is the "stride” through the buffer (the value the address generator adds each clock of the vector operation), and c2 is the ending value which is a dependent parameter of the Vector Operation Length.
- the vector operation is configured via the main switch depicted in FIGURE 29.
- the following are four types of vector operations that Unit C supports.
- Unit C performs complex addition of the input vector with the combination vector.
- Unit C performs complex subtraction of the combination vector from the unit vector.
- Unit C performs complex component- by-component multiplication of the input buffer with the combination buffer. This operation also performs the complex conjugate the contents of the combination buffer.
- Magnitude - Unit C performs an accurate approximation vector component-by-component of the magnitude of the complex quantity originating from the input buffer. The combination buffer is not used in this mode. A good approximation for magnitude would be:
- Ci reaKAi") + imag(Ai") - 1 / 2 (min(real(A ⁇ "),imag(Ai")))
- Accumulation is the mechanism for performing a variety of required vector operations efficiently such as dot products, de-spreading, etc.
- the output of the vector operation is accumulated over a variable number of clocks and output at this decimated rate.
- the state machine adjusts its time-domain timing to properly process the First Long-Code Sync, which starts 24 chips into the guard interval, or equivalently 8 chips before T1 .
- the state machine adjusts to the Second Long-Code Sync timing which starts place 8 chips before T2.
- the timing remains the same, at 8 chips before each symbol. The timing remains constant because the beginning of the header and data symbols take place in multiples of 80 chips after the Second Long-Code sync symbol.
- the sample timing of the two long syncs as well as the header and data symbols is shown in FIGURE 33. It should be noted that 1 ⁇ of guard interval 2 (GI2) is equivalent to Vz of guard interval 1 (GI1 ) at a value of 8 chips.
- buffer contents are no longer indexed by chip timing but by the sub-carrier number.
- the sub-carriers range in number from -32 to 31 , but in reality only -26 to 26 are used (excluding the zeroth sub-carrier as well) since the extreme frequencies are set to zero. Since MATLAB allows only positive indexing, the sub-carriers are indexed from 1 to 64 within a buffer. If we exclude the zero sub-carriers, the indexing is 7 to 59. All sub-carriers contain modulated data except for the pilot sub-carriers which are at -21 , -7, 7, 21 and indexed to 1 2, 26, 40, 54 within the buffers.
- FIGURE 34 shows the operation states used in the instruction set of processor 1 20.
- States 1 -3 are used to obtain timing information.
- state 1 is used to obtain sub-symbol timing while state 3 is used to obtain symbol timing.
- States 4-6 continue to predominantly take place in the time domain where frequency offset is estimated and (mostly) corrected.
- Only state 6 contains some frequency domain processing wherein initial sub-carrier channel estimates are made based on the sub-carrier values of the combined Long-codes.
- State 7 handles Header processing while state 8 handles data processing. While State 7 and state 8 include some time domain processing (e.g. rotation of data to counter frequency offset) the processing predominantly takes place in the frequency domain.
- both residual frequency offset and timing drift are estimated and corrected from and within the sub-carriers themselves.
- Short Sync Search (State 1 ), there are 10 repeated Short Sync symbols that are transmitted by the AP which spans 8 microseconds.
- the processor 1 20 only searches a fraction of samples for a short sync symbol.
- State 1 involves searching for a Short Sync symbol only at the end of the sample buffer. Since the iteration is 4 microseconds in duration, the requirement is that the RF/analog provides at least 4 microseconds worth of clean, valid short sync sequence to guarantee that the short sync sequence exists at the end of one of the buffers during at least one iteration.
- the processor 1 20 only performs the processing required to find the 1 6 possible correlations against the known time domain short sync symbol. If one of these exceeds a threshold, then detection of a short sync symbol is assumed which gives us sub-symbol timing which will be stored for future use. If none of these correlation exceed a threshold, then the processor 1 20 goes to sleep until the next iteration. [0145] Unit A is used for both of the channel filtering and the "matched filter" functionality that will compute all 1 6 correlations concurrently because both operations can support the 8 x parallelism of this unit.
- Unit C is used to form the non-coherent output of the matched filter (T2 + Q 2) and gauge the energy of the incoming samples which is required to normalize the matched filter outputs.
- Instruction mapping of the processor 1 20 during State 1 includes a first iteration of 2 to build up 1 6 tap short sync matched filter at end of the buffer.
- the last 23 complex samples are input as determined by the 3- Buffer scheme into Unit A.
- Unit A holds off the output for the first 7 samples (as the box-car is filling) and outputs 1 6 correlation against the low half of the short-sync (complex quantity).
- the complex result is stored at the beginning of Buffer 6. Currently the 1 0 Isb's are discarded on output.
- the processor 1 20 computes the non-coherent (l 2 + Q A 2) value of the 1 6 correlations.
- the phase of the short sync symbol is unknown - so the rotationally invariant quantity l A 2 + Q ⁇ 2 is computed on the complex contents of Buffer 7 to wipe out the phase information.
- the maximum tracking circuitry is enabled such that the value of the maximum along with the sample index at which this occurs are stored in registers.
- the processor 120 finds the signal energy for the baseline comparison.
- the energy of the received signal (or noise) will not be known with certainty due to potentially non-ideal AGC functionality, therefore the matched filter output needs to be normalized by the received energy level.
- This functionality is performed by Unit C using the last 33 samples using the non-coherent functionality (l A 2 + Q 2) on each of the input samples, and using the accumulation functionality of Unit C which will add the 33 noncoherent outputs together and output only a single real value to the first address of Buffer 6.
- the last 7 Isb's will be discarded which, along with setting the dynamic range of the output, also divides by the required power of 2 that makes the thresholding in the next step yield suitable performance at high SNRs ( but probably not low SNRs).
- the processor 1 20 determines if a "matched filter" spike is present.
- Unit C is used to determine whether the maximum found in step 3) is greater than the quantity found in step 4) (which has been divided by an appropriate power of 2). This condition will set the appropriate bit in the Status Register (which is not currently modeled in the simulation), which will be unmasked by the Status Mask Register and cause a branching that will functionally result in entering State 2.
- the processor 1 20 waits for one iteration, and in State 3, the processor 120 finds the long sync beginning. Now that a probable OFDM (orthogonal frequency division multiplexing) frame has been found, the sub-symbol timing is known via State 1 . The next step is to find the OFDM symbol timing. Based on the known duration of the short sync sequence and the length of the sample buffers, the first 1 6 samples of the long sync are guaranteed to be inside of the sample buffer at this point. This state determines exactly where in the buffer the long sync symbol begins.
- the mechanism for finding the long sync symbol involves using the sub-sync symbol timing to perform a series of correlations against the known short sync time domain waveform. This should result in a series of "spikes" that will be output at a 1 6 x decimated rate relative to the input. Unit C is used to perform this operation since the timing is known and a matched filter functionality is not required.
- Instruction mapping for the processor 1 20 includes setting up address generator correctly using degenerate Mode C operation and store this value for future use as well. Indirection must now be performed to access samples based on this value.
- Unit C is allowed to output into the Initial Address Register of the address generator governing the input of Unit C so that the next "button" push can begin at this pre-configured address. This is referred to as a "degenerate” mode because this button push does not perform any data processing, rather, it is used to set up correct operation for the data processing of the next "button push.”
- the input to Unit C is selected as the maximum index register, and the output is stored in a location in Buffer 7 designated for this purpose (currently we use address 1 000) for future use.
- Unit C is configured such that the output of this operation is identical to the input and this output is used to initialize the address generator with the value corresponding to sub-symbol timing (in other words Unit C acts as a "wire” in this instruction).
- the processor 1 20 correlates with known timing of the known time domain short sync symbols. Since the address generator is initialized to the correct sub-symbol timing, Unit C is how used to perform correlations with this timing of the entire waveform stored in the sample buffer against the short sync time domain waveform. The multiplication mode of Unit C is selected and the combine buffer selected is the Utility Buffer. The address generator associated with this combine buffer is initialized to point to a vector that contains the short sync time domain waveform repeated 1 0 times. The accumulator functionality of Unit C is set to 1 6 to perform successive correlations of the entire contents of the sample buffer with the short sync train stored in the Utility Buffer. The complex output of this operation comprises 1 0 values which are placed in the beginning of Buffer 6 after discarding the 1 0 Isb's after the accumulation.
- the processor 1 20 correlates with known timing of the known time domain partial long sync symbols. Since the address generator is initialized to the correct sub-symbol timing, Unit C is now used to perform correlations with this timing of the entire waveform stored in the sample buffer against the partial long sync time domain waveform. The multiplication mode of Unit C is selected and the combine buffer selected is the Utility Buffer. The address generator associated with this combine buffer is initialized to point to a vector that contains the partial long sync time domain waveform repeated 10 times. The accumulator functionality of Unit C is set to 1 6 to perform successive correlations of the entire contents of the sample buffer with the partial long sync train stored in the Utility Buffer.
- the complex output of this operation comprises 10 values which are placed in Buffer 6 beginning at address 1 1 so as not to overwrite the output of step 2).
- the 1 0 Isb's are discarded upon output.
- the processor 1 20 forms non-coherent calculation (l A 2 + Q A 2) on short sync correlations.
- the 1 0 values at the beginning of Buffer 6 that correspond to a series of short sync correlations serve as input to Unit C.
- Unit C is configured to perform the non-coherent calculation and outputs this value to the beginning of buffer 7 after discarding the 7 Isb's.
- the processor 1 20 forms non-coherent calculation (T2 + Q 2) on partial long sync correlations.
- the 1 0 values beginning at location 1 1 in Buffer 6 that correspond to a series of partial long sync correlations serve as input to Unit C.
- Unit C is configured to perform the non-coherent calculation and outputs this value to the beginning of buffer 1 0 after discarding the 7 Isb's.
- the processor 1 20 finds where partial long sync correlation exceeds short sync correlation.
- the very beginning of Buffer 7 and 1 0 are selected for the subtraction mode of Unit C.
- the 1 0 values of short sync correlations are subtracted from the 1 0 values of partial long sync correlations.
- the thresholding circuit of Unit C is enabled with the actual threshold set to 0. This has the functionality of flagging at which sample the partial long sync correlation exceeds that of the short sync correlations. This index of this occurrence is placed in a register by the thresholding circuit.
- the processor 1 20 multiplies index by 1 6.
- Unit C is used to select the index returned in step 6), multiply this by 1 6 using the Utility Buffer, and store in the beginning location of Buffer 7. This is the first step in the arithmetic to form the address corresponding to the long sync symbol timing.
- the utility buffer contains values corresponding to the input index for the lower values (i.e address 1 contains value 1 , address 2 contains value 2, etc.) so the complexity of multiple addressing modes need not be implemented (only indirect arithmetic need by supported.)
- the processor 1 20 adds 9 to the previous result.
- Unit C is used to select the value in Buffer 7 produced by the previous result, add 9 to the result using the utility buffer, and place in Buffer 6.
- the processor 1 20 adds this result to sub-symbol timing to compute long sync symbol timing.
- the short sync timing currently stored in memory location 1 000 of Buffer 7 is added to the value computed in step 8) and residing at the beginning of Buffer 6. This quantity is currently stored location 1 000 in Buffer 1 0. This corresponds to the beginning of the long sync waveform of interest.
- the processor 1 20 decides whether entire long sync is available. If the result of 9 is greater than 96, then the entire long sync is not currently available and state 4 is entered using the branching functionality of the processor 1 20. If the result is less than 96, then the long sync processing may continue by entering state 5 without waiting for the next iteration.
- the processor 1 20 waits for the first long sync to be available. Since the entire long sync symbol is not available until the following iteration, it is necessary to subtract 4 microseconds of samples (currently a value of 80) form the long sync symbol timing computed in State 3 to be able to correctly address the first long sync symbol in State 5.
- Instruction mapping for the processor 1 20 subtracts 80 from symbol timing.
- Unit C is used.
- the original estimate in Buffer 1 0 is used as input, the Utility Buffer is selected with an address of 80 (which contains the value of 80), subtraction is performed, and the result is placed into address 1 000 of Buffer 7.
- the processor 1 20 writes back to original location in Buffer 1 0.
- Unit C is used to transfer from Buffer 7 to Buffer 1 0.
- State 5 the first long sync symbol is buffered. This step is where the first long sync symbol must be stored for future use. Since the symbol timing is known, the exact 64 samples can be grabbed. Instruction mapping for the processor 1 20 sets up input address generator. Degenerate mode which uses Unit C to place the contents of Buffer 10 (long sync symbol timing) in the input address generator initial value register.
- the processor 1 20 grabs first long sync symbol and put in Buffer 6.
- Unit C is used to grab its input from the sample buffer for 64 clocks and directly output this to Buffer 6.
- the processor 1 20 sets up address generator for second long sync in upcoming iteration.
- the beginning of the second long sync resides 64 addresses away from the beginning of the first. So, the address generator is configured for operation by subtracting 1 6 (80-64) so that the correct long sync access will be made in State 6. In addition the result is stored for future use in state 8.
- Instruction mapping for the processor 1 20 includes forming the dot product of Buffer 6 and Input Buffer. Functionally, this step takes time domain samples of Long Code symbol number 1 (found in Buffer 6) and correlates it against the time domain samples of Long Code symbol number 2 (found in the Input Buffer). By correlation it is meant that Buffer 6 is multiplied sample by sample with the complex conjugate of the Input Buffer followed by an accumulation. The accumulation takes place after each multiplication such that the entire step takes 64 clocks. Because of the accumulation only one complex correlation value is outputted into Buffer 1 0c The final output is currently right-shifted by 9 bits. [0173] The processor 1 20 places addresses into an inverse look-up-table.
- the processor 1 20 gets an inverse value from the lookup-table.
- the address to the inverse LUT is accessed (via the initialization command from step 3), and the value at that address is written to Buffer 6.
- the utility buffer is used as the input buffer since it contains the LUT.
- the processor 1 20 uses the previous operation to find quotient (angle tangent) .
- This step finds the quotient between the imaginary part of Buffer 10 (written in step 2) and the real part. It uses the inverse value in Buffer 6 as the input buffer and it uses the absolute imaginary part of Buffer 10 as the combination buffer.
- the combination buffer format of Unit C must be set to the absolute of the imaginary. Unit C is set to multiplication between the input and combination buffer, and the output is written to buffer 7 with a right shift of 7.
- the processor 1 20 forms address into arctangent lookup-table. This step is almost exactly the same as step 3. Here the output of step 4 found in Buffer 7 is used as the input buffer and the arctangent LUT offset is found in the Utility Buffer location 1 02.
- the processor 1 20 determines angle from the LUT and adds an adjustment to get to the right quadrant.
- the address to the arctangent LUT is accessed (via the initialization command from step 6), and the value at that address is utilized to write into Buffer 6.
- By "utilized” it is meant that the proper adjustment must be added to get to the right quadrant.
- the complex value of the sample written in step 2 (Buffer 1 0) needs to be used in picking the right adjustment. If both the real and imaginary values of that complex sample are positive, then LUT value can be used "as is”. If the real is positive and the imaginary is negative then the negative of the LUT value should be outputted.
- the Unit C combination buffer stride is also initialized to the output buffer value. This sets up the stride in the next step.
- the processor 1 20 performs rotator operation on first long sync symbol. Overall this step rotates the first 64 complex samples from Buffer 6 by selected contents of the rotator LUT found within the Utility Buffer. Hence, Buffer 6 is selected as the input buffer while the Utility Buffer is selected as the combination buffer. Ultimately all 64 samples from Buffer 6 must be rotated separately into Buffer 1 0, so this entire step is a vector operation of length 64 without accumulation.
- the combination buffer offset is set to 4001 .
- the process of rotation at each of the 64 clock operations is now described.
- the baseline combination address is initialized to the combination buffer initial value which here is zero. (Since this is the first symbol to be rotated it makes sense that the initial rotation value be set to the very beginning of the rotator table.)
- the baseline combination address is utilized to obtain the exact address into the combination buffer. More precisely it is divided by 64, floored, and added to the Combination Buffer Offset to obtain the final combination buffer address.
- the value of the combination buffer at this address is then used for the current rotation operation on the current input buffer sample.
- the complex conjugate value of the combination buffer sample is multiplied by the input buffer sample via the Unit C multiplication operation.
- the output is written to Buffer 10 at the first address.
- the baseline combination address is incremented by the combination stride value initialized from step 6. It is then used utilized in the same fashion described above to obtain the next final combination buffer address. Again, multiplication between the combination buffer sample and input sample buffer occur with the input buffer address having been incremented by 1 . The output is written to the next address of Buffer 1 0, and the process repeats for a total of 64 times.
- the processor 1 20 sets a rotate pointer and stores for future use in state. Since Buffer 10[1003] estimates the AFC drift per input symbol sample, 64 times this value would represent the drift between the 1 st long code symbol and 2 nd long code symbol. Hence the value of 64*Buffer[1003] is desired to be used for the de-rotation of the 2 nd Long code symbol. In addition this resultant value needs to be stored in a buffer to update the rotator pointer again in state 7.
- Buffer 10 is used as the input buffer and the input buffer address is currently set to 1003.
- the combination buffer is set to the utility buffer, the 64 th address of which is used since the contents therein are conveniently set to 64.
- Unit C is set to multiply the input and combination buffers, and the output is written to address location 1003 of Buffer 7.
- the unit combine address generator in Unit C is initialized to this output for the next step of de-rotating the second long sync symbol.
- the processor 1 20 sets up the input address generator for rotation of data symbols.
- the value contained in Buffer 6[1 007] is used to setup the input address generator for rotation of the 2 nd long sync symbol in the next step. This value is the proper starting address for the input buffer which contains the time domain data.
- the processor 1 20 performs rotation on second long sync symbol. This step proceeds almost exactly as step 7.
- the baseline combination buffer address is initialized from the step 8 and the input buffer address is initialized from the last step. Also, the output is written to Buffer 6.
- the processor 1 20 sums the two long sync symbols together.
- the operation of summing the de-rotated long sync symbols is accomplished here.
- the input buffer is set to Buffer 6 (containing the 1 st long sync) while the combination buffer is set to buffer 1 0 (containing the 2 nd long sync).
- Unit C is set to addition, which takes place sequentially using addresses 1 through 64 of the two buffers. After a right shift of 1 , the outputs are written sequentially from addresses 1 to 64 into Buffer 8. For this to be accomplished Unit C must have a vector operation length of 64 and its output rate must be set to 1 so that there is an output written at all 64 clocks.
- the processor 1 20 performs a FFT stage. Each of the three FFT stages are processed by Unit B in the same manner except for the read and write buffers. In the 1 st stage buffer 8 is read while buffer 9 is written to; in the 2 nd stage buffer 9 is read and buffer 8 is written to; the 3 rd stage repeats the 1 st .
- the next step is multiplication of each of the y values with the appropriate twiddle factor (note that 4 twiddle factors are grabbed from the TWIDDLE_FACTOR_ROM each clock).
- the second FFT Stage is the same similar to the first FFT Stage but with different read and write buffers.
- the third FFT State is the same as stage 1 2.
- the processor 1 20 correlates the FFT output with the long code frequency domain sequence.
- the FFT output, contained in Buffer 9 is multiplied by the long code frequency domain sequence, contained in the Utility Buffer.
- Buffer 9 is set as the input buffer while the combination buffer is set to the Utility Buffer. Since the first 6 carriers are zero the initial input address is set to 7.
- address 501 of the combination buffer is used for the initial address, since this is the address offset to the non-zero long code sequence. Since the last 5 sub-carriers are also zero, the multiplication takes places over 53 successive clocks with no accumulation enabled. After each multiplication the result is written into Buffer 7 at successive address locations, starting in location 7.
- header processing is performed.
- this state simply sets up operation. No header demodulation yet occurs.
- the rotator pointer is incremented by 80 strides due to header symbol being 80 samples in length. Since the pointer moves by this amount in state 8, the amount is stored for future updates.
- Instruction mapping of the processor 120 includes determining the amount to move the rotator pointer from this state on. Every symbol contains 80 time domain samples. Thus, to properly account for frequency drift, the rotator pointer must be move 80 times the single-sample frequency offset estimate given by the value in Buffer 10[1003].
- Buffer 10 is used as the input buffer and the input buffer address is currently set to 1 003.
- the combination buffer is set to the utility buffer, the 80 th address of which is used since the contents therein are conveniently set to 80.
- Unit C is set to multiply the input and combination buffers, and the output is written to address location 1 005 of Buffer 6.
- the processor 1 20 updates the rotator pointer.
- the results from the last step are added from the current rotator pointer value to obtain the new rotator pointer value.
- Buffer 7 is set as the input buffer with an initial address of 1 003, while Buffer 6 is set to the combination buffer with an initial address of 1 005.
- Unit C is set to addition with a wrapping of 364*64 enabled. This means that the value of the sum is taken modulus 364*64.
- the resultant value is written into Buffer 10 at location 1004.
- state 8 After the FFT, state 8 must now correct for residual frequency offset and timing offset. It uses the long-code frequency domain sub-carriers as a starting point to estimate these two effects. At the first symbol, the angle between its pilot sub-carriers and the long-code pilot sub- carriers is computed. The average of these angles will determine the residual frequency offset whereas the difference between the first and the fourth derive the timing drift. The frequency offset correction is relatively constant over all sub-carriers whereas the timing drift induces a linear phase across the sub- carriers. The two estimates are used to rotate the long-code sub-carriers in the proper fashion to later compensate for both effects. The former as well as the initial linear phase induced determined from the latter are used to compute a rotator address.
- Instruction mapping of the processor 1 20 includes setting the stride to be used on rotation of the data symbols.
- the single- sample frequency drift amount is stored in Buffer 10[1 003], This is the amount the rotator needs to move per symbol sample.
- This value is read into the output buffer via Unit C degenerate mode.
- the combination buffer stride is initialized to the output buffer value. This step sets up the stride in step 5.
- the processor 1 20 stores the rotator pointer so that it can be properly updated.
- the rotator pointer must be incremented every symbol by the value in Buffer 6[1 005] (see step 1 of State 7) . Therefore, it is necessary to store the current rotator pointer value before updating it.
- Buffer 1 0 is set to the input buffer with the address set to 1 004. There is no combination buffer.
- Unit C is set to degenerate mode since there is no combine and the output is written to address 1003 of Buffer 7.
- the processor 1 20 updates the rotator pointer and set its value to the combiner buffer's address for rotation.
- the rotator pointer is now incremented by the value in Buffer 6[1005] which contains the symbol by symbol rotation adjustment.
- Buffer 6[1 005] is added to Buffer 7[1 003] and after taken modulus 360*64 written to Buffer 1 0[1 004]. In addition this sum is used to set up the combination buffer initial value for the rotation of step 5.
- the processor 1 20 sets up input address generator for rotation of data symbols in step 6.
- the value contained in Buffer 6[1 007] is used to setup the input address generator for rotation of data symbols in step 6. This value is the proper starting address for the input buffer which contains the time domain data.
- the processor 1 20 performs rotation on data symbols. This step proceeds very similar to state 6.
- the output is written to Buffer 8.
- the processor 1 20 performs a first FFT stage. This proceeds exactly the same as described in state 6.
- the second FFT state is performed the same as state 6 but with different read and write buffers.
- the third FFT stage correlates between the current channel estimate and the pilot symbols. Functionally, this step multiplies the channel estimate pilot sub- carrier samples (Buffer 7), written at the previous symbol iteration on state 8, and the complex conjugate of the pilot sub-carriers of the current symbol. Thus, there are four multiply operations corresponding to the 4 pilot sub- carriers.
- the read addresses are initialized to 1 2 corresponding to the location of the first pilot sub-carrier. Both read strides are set to 1 4 corresponding to the sub-carrier separation of each of the pilots. The writing, however, is done sequentially into Buffer 1 0.
- the processor 1 20 forms address into the inverse lookup table (LUT). This step is similar to step 2 of state 6 where it is desired to find the inverse of the absolute real output of step 9. This step is entered a total of four times (see step 1 2) . Each time a different read address from Buffer 1 0 is used. The first time address 1 is used, and subsequently the read address is incremented by 1 .
- LUT inverse lookup table
- the processor 1 20 gets an inverse value from LUT. This step is similar to step 3 of state 6 where the address to the inverse LUT is accessed. This step is entered a total of four times (see step 1 2). Each time a different write address is used on Buffer 6. The first time address 1 000 is used, and subsequently the write address is incremented by 1 .
- the processor 1 20 forms addresses into the inverse LUT and obtains the inverse value from the LUT three more times. These values are used to find quotients (i.e., angle tangents). This step is similar to state 6 where the quotient between the imaginary parts of Buffer 6 and its real parts are determined. The difference is that this step must determine 4 quotients instead of 1 . Thus, the number of vector operations is 4 and a write occurs at each multiply. The outputs are written sequentially into Buffer 7 starting at location 1 001 .
- the processor 1 20 forms addresses into an arctangent look-up table (LUT). This step is similar to state 6 and is entered a total of 4 times. The input buffer read address depends on how many times this step has already been entered. If zero, then it reads from location 1 001 of Buffer 7. Each subsequent time the read address location is incremented by 1 .
- LUT arctangent look-up table
- the processor 1 20 determines angle from the LUT and adds adjustment to get to the correct quadrant. This step is similar to state 6 and is entered a total of 4 times. The write address depends on the how many times this step has already been entered. If zero, then location 1000 of Buffer 1 0 is written to. Each subsequent time the write address location is incremented by 1 .
- the processor 1 20 forms addresses into an arctangent LUT, determines angles from the LUT, and adds an adjustment to get to the correct quadrant three times. Using these angles, the timing drift correction factor is determined. Functionally this step determines the difference between outputted angle the first time, and the outputted angle when step 1 5 was entered the fourth time. The difference is then multiplied by a constant very close to 1 /42.
- the input buffer is set to Buffer 10 which contains the four angles. Since only the first and fourth addresses are needed the stride is set to 3.
- the combination buffer is set to the Utility Buffer where locations 601 & 602 are used. Thus, the initial combination address is set to 601 with a stride of 2.
- the values at these LUT addresses are approximately 8*2 7* 1 /42 and -8*2 7* 1 /42 respectively.
- the "8" exists in the LUT so that the output contains 3 fractional bits. These fractional bits improve the performance of the demodulator.
- Unit C is enabled to multiplication and accumulation over a vector operation of 2. The output is right shifted by 7. This right shift eliminates the 2 7 factor which exists in the LUT.
- the residual frequency offset correction factor is determined. Functionally this step determines the average of the four outputs. Thus, each angle element from Buffer 1 0 needs to be multiplied by one and then summed together.
- the input buffer is set to Buffer 1 0 which contains the four angles.
- the combination buffer is set to the Utility Buffer.
- address 1 contains the value one which is used to multiply all four angles.
- the combination initial address is set to 1 and the stride is set to zero.
- Unit C is set to multiply and accumulate over 4 operations.
- the output is written into address 1 007 of Buffer 7.
- the processor 1 20 multiplies the timing correction factor by 26.
- the timing correction factor is not applied uniformly to each sub- carrier. Instead, the timing correction factor ultimately needs to be multiplied by the sub-carrier number to obtain the timing correction for that particular sub-carrier. For instance, at sub-carrier -26 the timing correction needs to be multiplied by -26.
- the rotation stride set in step 21 will be the timing correction factor.
- the initial rotator pointer is determined to determine the effect of timing drift on the initial rotator. Since the first data symbol occurs at sub-carrier -26, the timing correction factor is multiplied by the said number.
- the Utility Buffer contains the value 26 at the same address number, this is used as the combination buffer.
- Unit C is set to multiply and the output is written into address 1000 of Buffer 6. Although a negative is needed to create the proper offset, this is not done until step 1 9 where subtraction is used instead of addition.
- the processor 1 20 subtracts the output of the multiplication of the timing correction factor from the frequency offset correction factor to determine the rotator pointer address.
- the second aspect of setting the initial rotator pointer is the frequency offset. Since the frequency offset is constant over all sub-carriers, it is simply added to the negative of the output of the multiplication of the timing correction factor. The result is then divided by eight. This divide by eight is hot simply a right shift by 3, for the LSBs are NOT discarded. This particular functionality has not yet been exactly modeled within the UE as seen by additional MATLAB code below the UE instructions.
- the processor 1 20 sets the stride for the rotation to be performed.
- the combination buffer stride is now set to the value in address 1000 of buffer 7 divided by 8. This divide by eight is not simply a right shift by 3, for the LSBs are not discarded.
- the processor 1 20 rotates the data to eliminate timing drift and residual frequency offset. This step proceeds similarly to state 6. Here, however, there is no divide by 64. In addition, since only 53 sub-carriers are of interest a vector operation of 53 is used instead of 64. This also means that the starting input read and output write addresses are seven since the first 6 sub-carriers have no content.
- the baseline combination buffer address is initialized from step 20, and the stride for the rotation is initialized from the previous step. There is also some branching involved in the output buffer of this step. The output buffer is Buffer 10 on even iterations and Buffer 7 on odd iterations.
- FIGURE 35 illustrates an exemplary state diagram for an 802.1 1 a/b/g multi-mode program.
- a short sync match filtering is performed over 1 6 possible times for OFDM acquisition.
- a Barker Sync acquisition can be performed to enable multi-mode acquisition.
- state 1 culminate in the maximum short sync match filter energy being compared to a threshold. If the short sync threshold is exceeded, then OFDM demodulation takes place exactly as described in states 2-8 of FIGURE 34. In FIGURE 35, these states have been renamed to states 2a-8a to denote 802.1 1 a-only states.
- the rest of the Barker sync acquisition process is similar to the OFDM acquisition instructions.
- the phase of the 22 match filter outputs is eliminated via Unit C non-coherent operation and the maximum among these values is computed. This maximum value is compared against a threshold to determine if a Barker sync sequence has been sent. Upon exceeding the threshold, this state is exited and an address pointer is set (via a Unit C instruction) so that on-time Barker correlation (vis-a-vis match filtering) can subsequently take place.
- a Barker correlation against 1 1 chips takes places via a Unit C multiply and accumulate command using the Utility Buffer as source for the Barker sequence.
- the output of this instruction feeds into a non-coherent DBPSK (differential binary phase shift keying) set of instructions.
- the most recent set of outputs is multiplied by the complex conjugate of a delayed by one set of recent outputs to obtain the change of phase between bits. This can be accomplished via a Unit C multiply vector operation.
- the sign of the real part of these outputs can be used to determine the scrambled sync bit sent. This bit is sent to the RX Symbol Processor for descrambling and SFD detect. The sign is also used for modulation wiping which is used later for coarse frequency offset correction.
- the complex output is multiplied by -1 and written sequentially into a buffer; otherwise it is written as is. This operation can be accomplished via individual branching instructions or via an additional Unit C format operation which would be based on the current abs(real(-)) circuitry. Ultimately, the contents of this buffer must be averaged.
- State 2b is exited upon an SFD (start frame delimiter) detect indication from the RX Symbol Processor.
- SFD start frame delimiter
- SFD processing is performed.
- the RX Symbol Processor also provides the exact timing of the SFD detect. Such timing information is used by the processor to know when header as well as payload processing starts and finishes.
- a simple counter, implemented by simple Unit C copy, add, and compare instructions suffice to properly handle this timing information.
- State 3b completes the process of coarse frequency estimation wherein it initially determines the final mean of the wiped data. The angle of the result is then determined. This angle is used as the stride of a rotator to perform coarse frequency correction on the Barker correlator output.
- the last few (e.g. 5) decorrelated, derotated SFD symbols are used to determine the absolute phase used subsequently for phase tracking applied in coherent DBPSK demodulation.
- the symbols can be unwiped using the timing of the SFD detect, a lookup table (containing the relative phase reference of each of the symbols to the first) and a vector multiply instruction.
- the mean of these symbols is taken and the subsequent angle computed, all through previously described Unit C instructions. This mean angle is used as the initial phase reference for header and payload coherent demodulation.
- Barker despread data is once again derotated.
- the rotation instruction uses the same stride as before in State 3b.
- an offset is also needed. This is set to the negative of the initial phase from State 3b added to the final offset from the previous rotator operation.
- phase is not continually being updated.
- the phase need only be updated every 5-10 symbols because residual frequency offset is small. This allows the processor to decrease the clock budget (e.g., derotation can be applied on a vector of despread data and the phase angle need only be computed every few symbols) and decrease power consumption.
- the absolute phase is also used for the locked method of time tracking. Every time the phase wraps from 1 80° to -1 80° a wrap counter is incremented, and conversely, a wrap in the opposite direction will make the wrap counter decrement. This can be accomplished via Unit C branching, copy, add and subtract instructions. Once the wrap counter reaches a certain value, accomplished through more branch instructions, the address pointer feeding into the interpolation tap values is either incremented or decremented. As in phase adjustment, this set of instructions need not take place after each decorrelated, wiped output. Because timing drift is slow it can take place every N symbols so that clock budget and hence power is reduced.
- a payload demodulation is performed.
- the RX MAC sends the processor an indication as to the type of demodulation needed at this point as well as the length of packet. If the modulation type is DBPSK, then this state is almost identical to State 4a with the difference being the number of symbols demodulated. If the modulation type is DQBPSK, then modulation wiping must be enhanced. Not only must the sign of real part of the decorrrelated output be used but also whether the sign of the real equals the sign of imaginary. If the signs are equal, the same logic as DBPSK wiping can be used. If the signs are different, the real and imaginary values must be swapped.
- Unit D has specific circuitry used to accomplish a Fast Walsh Transform and max picker.
- Unit D inputs 8 chips at a time and outputs both the index of the max picker as well as the complex value corresponding to the index.
- the former can be used to derive the demodulated CCK bits via a combination of Unit C instructions and RX Symbol Processor logic. Upon processing the last symbol, the processor returns to State 1 .
- FIGURE 36 illustrates an exemplary state diagram for OFDM only TX processing.
- the processor does no TX processing in this state. It waits for an indication from the MAC before exiting this state.
- the processor writes the short code five times to the sample buffer. Since the short code sequence is stored in the Utility buffer, this instruction is accomplished via a Unit C copy command with address wrapping enabled in the Utility buffer. This state is entered a total of two times so that all 1 0 short codes are written.
- a 64 sample sequence of the Long Code is also stored in the Utility Buffer.
- the 32 Long Code guard interval samples as well as the first 48 samples of the first long code are written into the sample buffer using a Unit C copy command coupled with address wrapping.
- the last 1 6 samples of the first long code as well as all 64 samples of the 2 nd long code are written into the sample buffer using a Unit C copy command coupled with address wrapping into the Uitlity Buffer.
- the processor writes the pilot sub-carrier samples in the pilot subcarrier addresses by reading from the Utility Buffer wherein the scrambling LUT is located. Two different sets of operations are required, one for writing the pilot subcarriers at addreses 43 and 57 and the other for writing at addresses 7 and 21 . Subsequently, the scrambling address pointer is incremented.
- the data subcarrier samples are written into the same buffer as the pilot subcarrier values according to proper shift address mapping. These data samples are modulated (e.g., 1 6-QAM) data written into the sample buffer by the TX Symbol Processor. Before an IFFT (inverse Fast Fourier Transform) can be performed on the data and pilot subcarriers, the outlying subcarrier addresses as well as the DC subcarrier address are filled in with zeros. Both the data and zero filling are accomplished via a series of vectorized Unit C copy instructions.
- IFFT inverse Fast Fourier Transform
- the parsed data serves as the input to the 3-stage IFFT which is accomplished via Unit B instructions.
- the output of the IFFT output is written to the sample buffer including its prepended guard interval using address wrapping.
Abstract
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AU2003256386A8 (en) | 2004-01-23 |
US20040004995A1 (en) | 2004-01-08 |
US20040047405A1 (en) | 2004-03-11 |
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