WO2004008486A3 - Wafer bonding of thinned electronic materials and circuits to high performance substrates - Google Patents

Wafer bonding of thinned electronic materials and circuits to high performance substrates Download PDF

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Publication number
WO2004008486A3
WO2004008486A3 PCT/US2003/016233 US0316233W WO2004008486A3 WO 2004008486 A3 WO2004008486 A3 WO 2004008486A3 US 0316233 W US0316233 W US 0316233W WO 2004008486 A3 WO2004008486 A3 WO 2004008486A3
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WO
WIPO (PCT)
Prior art keywords
wafer
circuits
high performance
wafer bonding
electronic materials
Prior art date
Application number
PCT/US2003/016233
Other languages
French (fr)
Other versions
WO2004008486A2 (en
Inventor
Francis J Kub
Karl D Hobart
Original Assignee
Us Gov Sec Navy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Us Gov Sec Navy filed Critical Us Gov Sec Navy
Priority to AU2003261075A priority Critical patent/AU2003261075A1/en
Publication of WO2004008486A2 publication Critical patent/WO2004008486A2/en
Publication of WO2004008486A3 publication Critical patent/WO2004008486A3/en

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    • H—ELECTRICITY
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    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
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Abstract

A method of bonding a wafer (10) to a substrate (24) comprising the steps of: providing a wafer having a front surface and a back surface;attaching the front surface of the wafer to a support ; thinning the wafer from the back surface; bonding the back surface of the wafer to a substrate using a thin bonding technique; and removing the support (20) from the front surface of the wafer. A circuit comprising: a substrate; and a wafer; wherein the wafer is at most about 50 microns thick; wherein the wafer has a front surface comprising features; and wherein the wafer has a back surface bonded to the substrate using a thin bonding technique.
PCT/US2003/016233 2002-07-12 2003-06-26 Wafer bonding of thinned electronic materials and circuits to high performance substrates WO2004008486A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003261075A AU2003261075A1 (en) 2002-07-12 2003-06-26 Wafer bonding of thinned electronic materials and circuits to high performance substrates

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US39534002P 2002-07-12 2002-07-12
US60/395,340 2002-07-12

Publications (2)

Publication Number Publication Date
WO2004008486A2 WO2004008486A2 (en) 2004-01-22
WO2004008486A3 true WO2004008486A3 (en) 2004-03-04

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PCT/US2003/016233 WO2004008486A2 (en) 2002-07-12 2003-06-26 Wafer bonding of thinned electronic materials and circuits to high performance substrates

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US (2) US7535100B2 (en)
AU (1) AU2003261075A1 (en)
WO (1) WO2004008486A2 (en)

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FR2773261B1 (en) 1997-12-30 2000-01-28 Commissariat Energie Atomique METHOD FOR THE TRANSFER OF A THIN FILM COMPRISING A STEP OF CREATING INCLUSIONS
US6984571B1 (en) 1999-10-01 2006-01-10 Ziptronix, Inc. Three dimensional device integration method and integrated device
US6573126B2 (en) * 2000-08-16 2003-06-03 Massachusetts Institute Of Technology Process for producing semiconductor article using graded epitaxial growth
US6940089B2 (en) * 2001-04-04 2005-09-06 Massachusetts Institute Of Technology Semiconductor device structure
FR2823596B1 (en) * 2001-04-13 2004-08-20 Commissariat Energie Atomique SUBSTRATE OR DISMOUNTABLE STRUCTURE AND METHOD OF MAKING SAME
US7387913B2 (en) * 2001-08-08 2008-06-17 Jsr Corporation 3D optoelectronic micro system
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WO2004008486A2 (en) 2004-01-22
US7358152B2 (en) 2008-04-15
US20040009649A1 (en) 2004-01-15
AU2003261075A1 (en) 2004-02-02
US7535100B2 (en) 2009-05-19
US20060199353A1 (en) 2006-09-07

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