WO2004010496A1 - Hetero integration of semiconductor materials on silicon - Google Patents
Hetero integration of semiconductor materials on silicon Download PDFInfo
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- WO2004010496A1 WO2004010496A1 PCT/US2003/020344 US0320344W WO2004010496A1 WO 2004010496 A1 WO2004010496 A1 WO 2004010496A1 US 0320344 W US0320344 W US 0320344W WO 2004010496 A1 WO2004010496 A1 WO 2004010496A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02441—Group 14 semiconducting materials
- H01L21/0245—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02488—Insulating materials
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/02546—Arsenides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/8258—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213, H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
Definitions
- This invention relates generally to semiconductor structures, and more specifically to the monolithic integration and coexistence of mixed material systems, such as gallium arsenide on silicon.
- Semiconductor devices often include multiple layers of conductive, insulating, and semiconductive layers. Often, the desirable properties of such layers improve with the crystallinity of the layer. For example, the electron mobility and electron lifetime of semiconductive layers improves as the crystallinity of the layer increases. Similarly, the free electron concentration of conductive layers and the electron charge displacement and electron energy recoverability of insulative or dielectric films improves as the crystallinity of these layers increases.
- hetero-integration for short
- the term hetero- integration means the monolithically integrated coexistence of mixed material systems on a common substrate. Hetero-integration thus provides the ability to integrate multiple material based technologies (and therefore devices) in a single semiconductor structure. Accordingly, a need exists for a semiconductor structure having improved monolithic integration of GaAs (and other compound semiconductors) and silicon. Such a semiconductor structure would enable high performance, low power, RF, analog, digital, and optical sub-systems, as well as allow for hetero-integration of systems formed by interconnecting these sub-systems.
- FIGs. 1-11 illustrate, in cross section, a device structure in various stages of being formed in accordance with the present invention
- FIG. 12 is a flowchart in accordance with the present invention
- FIGs. 13-19 illustrates, in cross section, a device structure in various stages of development in accordance with an alternative embodiment of the invention
- FIGs. 20-25 illustrates, in cross section, the formation of the device structure further including a P+ buried layer as part of a further alternative embodiment of the invention
- FIGs. 26-27 illustrate, in cross section, further developmental stages of FIG. 25 including selective GaAs growth
- FIGs. 28 and 29 illustrate the further development of the structure of FIG. 25 including non-selective GaAs growth
- FIGs. 30 shows GaAs devices formed in either of the structures of FIGs. 27 or 29;
- FIG. 31 illustrates the interconnect between GaAs and silicon devices for these structure of FIG. 30;
- FIGs. 32 and 33 illustrate cross sectional views of structures in accordance with the present invention.
- FIG. 34 is a flowchart in accordance with yet another alternative embodiment of the invention.
- a hetero-integrated structure and method of forming same in which a high quality compound semiconductor material, such as high quality gallium arsenide (GaAs), is grown over a thin germanium layer to co-exist with silicon for hetero-integration of devices.
- a high quality compound semiconductor material such as high quality gallium arsenide (GaAs)
- GaAs gallium arsenide
- a bonded germanium wafer of silicon , oxide, and germanium is formed and capped.
- the cap and germanium layer are partially removed so as to expose a silicon region and leave a stack of oxide, germanium, and capping layer on the silicon.
- Silicon is grown over the exposed silicon region.
- Silicon devices are made in the grown region of silicon.
- the remaining capping layer is etched away to expose the thin layer of germanium.
- GaAs is grown on the thin germanium layer, and GaAs devices are built which can interoperate with the silicon devices.
- a smaller portion of the remaining cap can be removed and germanium or silicon-germanium can be grown on the exposed germanium in order to form germanium or silicon-germanium devices.
- the smaller remaining cap can subsequently be removed to access the germanium and form GaAs devices thereby allowing, GaAs, germanium-based, and silicon devices to co-exist.
- FIGs. 1-11 illustrate, in cross section, a device structure 20 in various stages of being formed in accordance with the present invention. While the present invention is described in terms of a GaAs on silicon example, other compound semiconductors, such as AlGaAs, InGaAs, InP, and GaN, can also benefit from this approach.
- FIGs. 1-4 represent the formation stages of a wafer having germanium on oxide on a silicon substrate.
- FIG. 5 represents a protection stage for the germanium layer.
- FIGs. 6-8 represent the stages for forming silicon devices.
- FIGs. 9-10 represent the stages for forming GaAs devices.
- FIG. 1 there is shown in cross section, a structure 20 of a silicon wafer 22 having oxide layer 24 and germanium layer 26. Layers 22, 24, and
- FIG. 2 shows hydrogen being implanted 28 into the germanium layer 26.
- the purpose of the infusion of hydrogen into the germanium layer 26 is to separate the bonded Ge layer as indicated by designator 29 which will assist in thinning the Ge layer.
- FIG. 3 shows the germanium layer 26 having been cut down to achieve a thin Ge layer of preferably less than one-micron thickness. Various cutting and planarization techniques known in the art can be used to achieve the desired thickness.
- FIG. 4 shows the germanium layer 26 having been polished, preferably by chemical mechanical polish (CMP) techniques, to achieve an even thinner layer of germanium of preferably less than half-micron thickness.
- CMP chemical mechanical polish
- FIG. 5 shows a protection layer 30 deposited over the thin layer of germanium 26, in accordance with the present invention.
- Protection layer 30 is preferably formed of oxide material but can also be nitride, oxy-nitride, or similar dielectrics. Deposition techniques such as sputtering, CVD, ALD, MOCVD, as well as other techniques can be used to accomplish the deposition of the protection layer 30 over the thin germanium layer 26.
- the protection layer 30 operates as a capping layer and will also be referred to as capping layer 30.
- a bonded wafer of silicon 22, oxide 24, and germanium 26 is formed and capped 30, as shown in FIG. 5.
- FIG. 6 shows an exposed silicon region 32 that is achieved by etching through a portion of the cap, germanium, and oxide layers 30, 26, and 24. Selective silicon growth is performed on the exposed silicon region 32 forming a plane of silicon 34 adjacent to top surface
- the silicon growth process can also be accomplished using epitaxial over-growth techniques in which the silicon is overgrown higher than the cap layer 30 and then cut back or planarized to align with the cap surface 37.
- Epitaxial over-growth techniques of silicon will allow for undesirable crystal facets to be removed as will be described in conjunction with a further embodiment later on.
- non-selective growth techniques of GaAs will also be described in conjunction with a further embodiment.
- silicon devices 36 are formed on the silicon surface 34.
- Silicon devices 36 while shown in the figure as a MOSFET, can be a resistor, a capacitor, an active semiconductor component such as a diode or a transistor or an integrated circuit such as a CMOS integrated circuit.
- silicon devices 36 can comprise a CMOS integrated circuit configured to perform digital signal processing or another function for which silicon integrated circuits are well suited.
- the electrical semiconductor component formed on the silicon surface 34 can be formed by conventional semiconductor processing as well known and widely practiced in the semiconductor industry.
- a layer of insulating material 40 such as a layer of silicon dioxide or the like may overlie electrical semiconductor component 36.
- FIG. 9 shows structure 20 having been etched down to expose the thin germanium layer 26.
- a GaAs layer 38 is then grown over the exposed germanium layer 26 such that the GaAs layer 38 and silicon layer 40 are now co-planar.
- the GaAs layer 38 can be grown with molecular beam epitaxy (MBE) techniques.
- MBE molecular beam epitaxy
- GaAs is lattice matched to germanium, very high quality GaAs layers are possible without having to grow a very thick GaAs layer. Thicknesses of GaAs in the 100 to 10000 angstroms range are now possible. Alternate IH-V compounds such as AlGaAs, InGaAs, InGaAlP, InGaAsN can be included as part of the epitaxial layer to form a variety of devices. GaAs semiconductor devices are then formed on the GaAs layer 38 as shown in FIG. 11.
- GaAs Semiconductor devices can be formed by processing steps conventionally used in the fabrication of gallium arsenide or other ILT-V compound semiconductor material devices. While a GaAs MESFET is shown in the figure, semiconductor devices can be any active or passive component, and preferably is a semiconductor laser, light emitting diode, photodetector, heteroj unction bipolar transistor (HBT), high frequency MESFETs and High Electron Mobility Transistors (HEMT)s, or other component that utilizes and takes advantage of the physical properties of compound semiconductor materials.
- the GaAs device implemented in the GaAs layer 38 depends on the epitaxial layer design used to form the GaAs layer 38.
- An additional layer of dielectric 42 is deposited and planarized over the GaAs 38 and GaAs devices 39 so that the GaAs devices can be prepared for contact metallization.
- the growth of GaAs can be selective or non selective. (An alternative embodiment to be described later on will discuss non- selective GaAs growth in greater detail.) Thus, the co-existence of GaAs and Si and GaAs and Si devices is now possible.
- FIG. 12 is a flowchart 120 summarizing the steps of forming a hetero- integrated semiconductor structure in accordance with the present invention.
- the process begins at step 122 by forming a wafer having a germanium layer on an oxide layer on a silicon substrate.
- the next few steps include protecting a germanium region at step 124, followed by exposing a silicon region at step 126 and growing silicon in the exposed silicon region at step 128. Forming silicon devices in the silicon region occurs at step 130.
- by performing the steps of exposing the germanium layer at step 132 and growing compound semiconductor material on the exposed germanium layer at step 134 this allows for constructing compound semiconductor devices in the compound semiconductor material at step 136.
- step 122 of forming the wafer having the germanium layer on the oxide layer on the silicon substrate is preferably performed by wafer bonding.
- step 124 of protecting the germanium region is preferably achieved by capping the region with silicon di-oxide and using silicon nitride spacers for side protection (to be described in a later).
- Growing the silicon at step 128 is preferably achieved by selective growth techniques, but non-selective growth techniques can be used as well.
- FIGs. 13-19 illustrates, in cross section, a device structure in various stages of development in accordance with an alternative embodiment of the invention in which sidewall spacers are used. Like reference numerals have been be carried forward where appropriate.
- FIG. 13 starts with the formation of the thin germanium layer 26 on the oxide layer 24, on the silicon substrate 22 (like that obtained by the completion of development stage of FIG. 4 or other appropriate means).
- the structure is shown to further include cap layer 30.
- FIG. 15 shows a portion of the capping, germanium, and oxide layers 30, 26, 24 removed to form a well or trench 51 between two stacks 31.
- Well known techniques such as photoresist masking and plasma etching can be used to form the trench 51.
- FIG. 16 shows the addition of spacer material 52 on the inner sidewalls of the trench 51.
- the spacers 52 are preferably either an oxide or nitride material.
- FIG. 17 shows the selective growth of silicon material 54 within trench 51 and demonstrates how the silicon can tend to overgrow some of the capping layer 30 and form facets determined by crystal structure of silicon as indicated by designators 56.
- FIG. 18 shows the silicon after it has been planarized down to become substantially co-planar with the capping layer 30 of the stacks 31.
- CMOS devices 58 such as CMOS devices
- the silicon can also be used to make other silicon-based technologies and devices such as analog, RF, Bi-CMOS, and bipolar-based technologies.
- FIGs. 20-25 illustrates, in cross section, the formation of a device structure including a P+ buried layer as part of a further alternative embodiment of the invention.
- FIG. 20 there is again shown the structure of FIG. 16, with germanium on oxide on silicon with trench 51, and side spacers 52.
- a P+ buried layer is again shown in FIG. 20, with germanium on oxide on silicon with trench 51, and side spacers 52.
- FIG. 22 illustrates the silicon material 64 having been planarized such that the silicon material and capping layers 30 become substantially co-planar.
- Silicon devices 68 such as CMOS devices, or other silicon-based devices are formed in the planarized silicon 64 as shown in FIG. 23. These silicon devices will have been formed in regions of low resistivity, which can improve circuit performance in selected applications.
- FIG. 24 shows the addition of an oxide layer 70 planarized over the capping layers 30 and silicon devices 68, as well as the location of a masking region 72 over the silicon device region.
- FIG. 25 shows the structure with the planarized oxide layer 70 and the capping layer 30 removed.
- the structure is prepared for either selective or non- selective growth of GaAs as will be described with reference to FIGs. 26-29.
- the masking layers are typically removed prior to GaAs growth.
- FIGs. 26 shows how GaAs material 38 is selectively grown on the germanium layer 26.
- the mask 72 has been removed before the selective growth process of GaAs is completed.
- a capping layer 74 is then added as seen in FIG. 27 to cover the entire surface of the structure.
- This capping layer 74 can be a variety of materials including silicon nitride (SiN), silicon carbide (SiC) or aluminum nitride (A1N) to passivate the GaAs.
- FIG. 28 shows how the non-selective growth of GaAs material over the germanium layer 26 results in GaAs overgrowth on non-Ge regions.
- the GaAs on non-Ge regions creates amorphous GaAs regions 76 while the GaAs on germanium creates crystalline GaAs regions 78.
- the GaAs in regions 76 and 78 are polished away or planarized using one of a variety of techniques, such as resist etch back, chemical mechanical polishing (CMP), or mask and etch techniques to become substantially co-planar with the silicon region.
- CMP chemical mechanical polishing
- the structure is then covered with passivation layer 74 as shown in FIG. 29, and similar to that shown in FIG. 27.
- the two end structures of FIGs. 27 and FIG. 29 are substantially similar whether they were formed with selective or non-selective growth techniques.
- FIGs. 30 and 31 illustrate the implementation of GaAs devices 80 into the passivated structure.
- FIG. 30 shows the formation of MESFET or HEMT type devices with gate 82 and source/drain 84, 86.
- Other GaAs devices can be similarly formed in the GaAs regions of the wafer and is not limited to the formation of MESFETs or HEMTs.
- dielectric 88 such as nitride or oxide or oxide-nitride mixture
- the contacts 90 are etched in the dielectric layer 88 to contact the necessary regions of the devices, both in the GaAs as well as the silicon regions.
- the contacts 90 are filled with conducting materials, and metal 92 is patterned on top to provide connectivity between the GaAs devices 80 and silicon devices 68.
- the details of contact formation and metallization are well understood by those familiar with the backend processing in the semiconductor industry.
- FIG. 32 provides first and second structures that in and of themselves are believed to be novel.
- FIG. 32 is a structure that can provide for the hetero- integrated structure of islands of silicon and island of some compound semiconductor over a silicon substrate.
- the structure includes a silicon substrate 22 having first and second stacks 31 with side spacers 52 forming a trench 51 filled with silicon 94 (grown either by selective or non-selective growth) between the stacks 31.
- the stacks 31 are formed of a capping layer 30, a germanium layer 26, and an oxide layer 24 formed over the silicon substrate 22.
- germanium is prepared for the subsequent growth of high quality compound semiconductors.
- the germanium can be grown to the level of the silicon for the creation of Ge based devices as well.
- FIG. 33 shows the co-existence of silicon and GaAs by taking the structure of FIG. 33, removing the capping layer 30 and growing GaAs or other compound semiconductor 96.
- the use of the bonded germanium allows for high quality GaAs to be grown thus creating a useable high quality structure of hetero- integrated materials. While only two islands are shown in the figure, one each for silicon and GaAs, it is clear that the structure can be extended to include multiple silicon and GaAs islands separated by the spacer regions. Furthermore, islands of Ge or SiGe (for Ge-based devices like photodetectors) can also be created in like fashion. In accordance with another alternative embodiment, the coexistence of GaAs
- germanium (or other compound semiconductor), germanium, and silicon can be achieved by totally encapsulating the germanium with side wall spacers (in a similar manner to that described previously for Si encapsulation) and then capping and etching down to the portion of the germanium contained within the spacers, and then growing the germanium up to the level of the silicon and GaAs surfaces.
- a flow chart 200 is provided in FIG. 34 to describe the formation of devices in each of the Si, Ge, and
- FIG. 34 is a flowchart 200 of a method of forming the hetero-integrated semiconductor structure in accordance with the alternative embodiment in which GaAs, Si, and Ge devices are formed and co-exist.
- the initial steps involve the creation of the base structure(steps 202, 204) followed by the formation of silicon devices (steps 206-210), followed by the formation of germanium devices (steps 212-216), and finally the formation of GaAs devices (steps 218-222).
- Flowchart 200 begins with the step of forming a germanium wafer having germanium, oxide, and silicon layers at step 202, followed by the step of capping the wafer with a mask at step 204. Then, by partially etching the wafer down to the silicon layer so as to create a stack on top of the silicon at step 206 and growing silicon material adjacent to the stack(s) at step 208, the silicon devices can be formed in the silicon material at step 210.
- the next few steps involve the creation of germanium devices. These steps include removing a portion of the mask to expose a portion of the germanium layer at step 212, growing germanium or silicon germanium over the exposed germanium region at step 214, and forming germanium or silicon-germanium devices in the region at step 216.
- the remaining steps involve the formation of GaAs devices. These steps include removing the remaining mask to expose the remaining germanium region at step 218, growing gallium arsenide on the exposed portion of the germanium layer at step 220, and forming gallium arsenide devices in the GaAs layer at step 222.
- the method provided by the alternative embodiment provides for extended hetero-integration of Si, Ge, and GaAs.
- gallium arsenide is the preferred compound semiconductor material, but other ULN or U-TV compound semiconductor materials, as previously mentioned, can also be used.
- high quality GaAs on thin epilayers on silicon has been achieved. This enhances the ability to create hetero-integrated systems such as optical integration with CMOS, GaAs RF and analog with CMOS digital, and SiGe bipolar with GaAs optical and electronic to name but a few.
- the structures and techniques formed in accordance with the present invention and alternative embodiments provide for the coexistence of islands of silicon and high quality IH-N and II-IV compound semiconductors, such as GaAs.
Abstract
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AU2003281568A AU2003281568A1 (en) | 2002-07-18 | 2003-06-27 | Hetero integration of semiconductor materials on silicon |
EP03742271A EP1525614A1 (en) | 2002-07-18 | 2003-06-27 | Hetero integration of semiconductor materials on silicon |
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Also Published As
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US20040012037A1 (en) | 2004-01-22 |
TW200409304A (en) | 2004-06-01 |
EP1525614A1 (en) | 2005-04-27 |
AU2003281568A1 (en) | 2004-02-09 |
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