WO2004017196A3 - Timing ring mechanism - Google Patents

Timing ring mechanism Download PDF

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Publication number
WO2004017196A3
WO2004017196A3 PCT/US2003/025688 US0325688W WO2004017196A3 WO 2004017196 A3 WO2004017196 A3 WO 2004017196A3 US 0325688 W US0325688 W US 0325688W WO 2004017196 A3 WO2004017196 A3 WO 2004017196A3
Authority
WO
WIPO (PCT)
Prior art keywords
devices
timer
cpu
lifo
slots
Prior art date
Application number
PCT/US2003/025688
Other languages
French (fr)
Other versions
WO2004017196A2 (en
Inventor
Mark Justin Moore
Original Assignee
Globespan Virata Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Globespan Virata Inc filed Critical Globespan Virata Inc
Priority to AU2003259871A priority Critical patent/AU2003259871A1/en
Publication of WO2004017196A2 publication Critical patent/WO2004017196A2/en
Publication of WO2004017196A3 publication Critical patent/WO2004017196A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G06F9/4825—Interrupt from clock, e.g. time of day

Abstract

A method and system for scheduling threads and timer mechanisms of events in a computer system that includes a central processing unit (CPU), a plurality of input/output (I/O) devices, such devices as storage devices, network interface devices (NIDs) and a memory which s typically used to store various applications or other instructions which, when invoked enable the CPU to perform various tasks, the timer structure provides a ring structure and an associated control block is provided. The timer mechanism of the present invention comprises a ring structure that includes an array of ring slots, with the slots relating to pointers for implementing a circular array of LIFO (Last In, First Out) queues generally where each LIFO queue maintains a listing of EventDescriptors that relate to functions which must be performed during the time slot associated with the particular pointer position.
PCT/US2003/025688 2002-08-16 2003-08-18 Timing ring mechanism WO2004017196A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003259871A AU2003259871A1 (en) 2002-08-16 2003-08-18 Timing ring mechanism

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US40365602P 2002-08-16 2002-08-16
US60/403,656 2002-08-16

Publications (2)

Publication Number Publication Date
WO2004017196A2 WO2004017196A2 (en) 2004-02-26
WO2004017196A3 true WO2004017196A3 (en) 2005-12-22

Family

ID=31888264

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/025688 WO2004017196A2 (en) 2002-08-16 2003-08-18 Timing ring mechanism

Country Status (3)

Country Link
US (1) US20040205753A1 (en)
AU (1) AU2003259871A1 (en)
WO (1) WO2004017196A2 (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU2003300948A1 (en) * 2002-12-16 2004-07-22 Globespanvirata Incorporated System and method for scheduling thread execution
US7522516B1 (en) * 2004-03-30 2009-04-21 Extreme Networks, Inc. Exception handling system for packet processing system
US7292591B2 (en) * 2004-03-30 2007-11-06 Extreme Networks, Inc. Packet processing system architecture and method
US7649879B2 (en) * 2004-03-30 2010-01-19 Extreme Networks, Inc. Pipelined packet processor
US7889750B1 (en) 2004-04-28 2011-02-15 Extreme Networks, Inc. Method of extending default fixed number of processing cycles in pipelined packet processor architecture
US7817633B1 (en) 2005-12-30 2010-10-19 Extreme Networks, Inc. Method of providing virtual router functionality through abstracted virtual identifiers
US7822033B1 (en) 2005-12-30 2010-10-26 Extreme Networks, Inc. MAC address detection device for virtual routers
US7894451B2 (en) * 2005-12-30 2011-02-22 Extreme Networks, Inc. Method of providing virtual router functionality
US8605732B2 (en) 2011-02-15 2013-12-10 Extreme Networks, Inc. Method of providing virtual router functionality
US20140223436A1 (en) * 2013-02-04 2014-08-07 Avaya Inc. Method, apparatus, and system for providing and using a scheduling delta queue
US9904313B2 (en) 2015-07-13 2018-02-27 Nxp Usa, Inc. Timer rings having different time unit granularities
US9915969B2 (en) 2015-07-13 2018-03-13 Nxp Usa, Inc. Coherent timer management in a multicore or multithreaded system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0723235A2 (en) * 1995-01-23 1996-07-24 Tandem Computers Incorporated Software-driven timer and method of using same
US6195725B1 (en) * 1998-12-14 2001-02-27 Intel Corporation Dynamically varying interrupt bundle size

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4123794A (en) * 1974-02-15 1978-10-31 Tokyo Shibaura Electric Co., Limited Multi-computer system
US4989133A (en) * 1984-11-30 1991-01-29 Inmos Limited System for executing, scheduling, and selectively linking time dependent processes based upon scheduling time thereof
US5905913A (en) * 1997-04-24 1999-05-18 International Business Machines Corporation System for collecting a specified number of peripheral interrupts and transferring the interrupts as a group to the processor
US6182238B1 (en) * 1998-05-14 2001-01-30 Intel Corporation Fault tolerant task dispatching
US6427161B1 (en) * 1998-06-12 2002-07-30 International Business Machines Corporation Thread scheduling techniques for multithreaded servers
US6115779A (en) * 1999-01-21 2000-09-05 Advanced Micro Devices, Inc. Interrupt management system having batch mechanism for handling interrupt events
US6754690B2 (en) * 1999-09-16 2004-06-22 Honeywell, Inc. Method for time partitioned application scheduling in a computer operating system
US6782461B2 (en) * 2002-02-25 2004-08-24 Intel Corporation Dynamically adjustable load-sharing circular queues

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0723235A2 (en) * 1995-01-23 1996-07-24 Tandem Computers Incorporated Software-driven timer and method of using same
US6195725B1 (en) * 1998-12-14 2001-02-27 Intel Corporation Dynamically varying interrupt bundle size

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
VARGHESE G ET AL: "HASHED AND HIERARCHICAL TIMING WHEELS: EFFICIENT DATA STRUCTURES FOR IMPLEMENTING A TIMER FACILITY", IEEE / ACM TRANSACTIONS ON NETWORKING, IEEE INC. NEW YORK, US, vol. 5, no. 6, December 1997 (1997-12-01), pages 824 - 834, XP000734410, ISSN: 1063-6692 *

Also Published As

Publication number Publication date
WO2004017196A2 (en) 2004-02-26
AU2003259871A1 (en) 2004-03-03
US20040205753A1 (en) 2004-10-14

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