WO2004021358A1

WO2004021358A1 - Memory arrangement, method for operating a memory arrangement, and method for producing a memory arrangement

Info

Publication number: WO2004021358A1
Application number: PCT/DE2003/002559
Authority: WO
Inventors: Franz Hofmann; Michael Specht
Original assignee: Infineon Technologies Ag
Priority date: 2002-08-08
Filing date: 2003-07-30
Publication date: 2004-03-11
Also published as: TW200405533A; DE10236439B3

Abstract

The invention relates to a memory arrangement, a method for operating a memory arrangement, and a method for producing a memory arrangement. Said memory arrangement contains a substrate and a plurality of memory areas formed on and/or in said substrate, each memory area being arranged in such a way that the electrical resistance of the respective memory area can be selectively adjusted, by means of heat treatment, to a first value or to a second value which is higher than the first. Furthermore, a heat dissipating structure is arranged between the memory areas, for dissipating heat supplied to said memory areas.

Description

description

Memory arrangement, method for operating a memory arrangement and method for producing a memory arrangement

The invention relates to a memory arrangement, a method for operating a memory arrangement and a method for producing a memory arrangement.

A non-volatile memory using Ge _x Sb _y Te _z as a memory area is known from [1], [2]. With the material Ge _x Sb _y Te _z , a phase change can take place between an amorphous and a crystalline phase. With this conversion, the electrical resistance of the

Material significant. In the case of a brief current pulse, the material is visually melted. During a subsequent rapid cooling, the material remains in an amorphous state in which the material has a high electrical resistance. Reprogramming to a crystalline state is done using a weaker current pulse that is applied for a long time. As a result, the material cools sufficiently slowly to form a crystalline phase that has a lower resistance.

FIG. 6 shows a memory cell 600 known from the prior art based on the principle described.

Between a first electrode 601 and a second

Electrode 602 is an arrangement of a heating element 603 and a Ge _x Sb _y Te _z layer 604. By applying an electrical current between the electrodes 601, 602, using the heating element 603, a programmable region 605 of the Ge _x Sb _y Te _z layer 604 can be heated to such an extent that a conversion between an amorphous and a crystalline phase is made possible. at If the pulse is sufficiently long and weak enough, the programmable area 605 is brought into a crystalline state; if a sufficiently short and strong pulse is applied, the programmable area 605 is brought into an amorphous state. Since the amorphous state has a significantly higher electrical resistance than the crystalline state, by applying a small reading current between the electrodes 601, 602 it can be scanned in which state the programmable area 605 is located as a memory area.

If memory cells such as the memory cell 600 shown in FIG. 6 are packed in a high-density array, undesired heat coupling between the individual cells can occur. With a long programming time (typically 100 ns), as is required to set the crystalline phase, heat can be undesirably transferred to a memory cell adjacent to the memory cell to be programmed, and the state thereof can thus be changed unintentionally. As a result, the information contained in the adjacent memory cell can be lost. The high temperature for generating the amorphous phase remains essentially localized on a memory cell to be programmed because of the shorter time period (typically 5 ns), in which case a part of the heat can also be undesirably dissipated from the memory cell. This is particularly critical in the case of two adjacent cells, one of which is in the amorphous and the other in the crystalline phase, one cell being converted from the amorphous state to the crystalline state. For this purpose, a certain temperature must be maintained in the memory cell to be programmed for a longer period of time, which can be transferred to the neighboring cell and whose state can also change.

For the reasons described, among others, it has not been possible to date to use a memory arrangement Generate Ge _x Sb _y Te _z areas with a sufficiently high packing density, since a high packing density results in a short distance and therefore problems with heat coupling between individual cells.

The invention is based on the problem of creating a memory cell arrangement with memory cells with variable electrical resistance, in which the integration density is increased and simultaneously sufficiently safe programming is made possible.

The problem is solved by a memory arrangement, by a method for operating a memory arrangement and by a method for producing a memory arrangement with the features according to the independent patent claims.

The memory arrangement according to the invention contains a substrate and a plurality of storage areas formed on and / or in the substrate, each of which is set up in such a way that the electrical resistance of the respective storage area can be selectively adjusted to a first value or to a second value by means of thermal treatment is greater than the first value. Furthermore, the storage arrangement according to the invention has a heat dissipation structure arranged between the storage areas for dissipating heat supplied to one of the storage areas.

Furthermore, the invention provides a method for operating a memory arrangement with the features described above, an electrical write signal being applied in accordance with the method, which is set up in such a way that the value of its electrical resistance to the first or the second value is set. Alternatively, according to the

Method applied an electrical read signal, which is set up in such a way that for a respective Memory area the value of its electrical resistance is detectable.

According to a method for producing a memory arrangement, a plurality of memory areas are formed on and / or in a substrate, each of which is set up in such a way that the electrical resistance of the respective memory area is selectively adjusted to a first value or to a second value by means of thermal treatment is adjustable, which is greater than the first value. A heat dissipation structure for dissipating heat supplied to one of the storage areas is arranged between the storage areas.

A basic idea of the invention is to arrange a sufficiently good heat-conducting structure between the memory areas of the memory arrangement according to the invention, and thus to prevent undesired heat transfer to a memory cell adjacent to a memory cell to be programmed (or read). This ensures according to the invention that information can be stored or read out sufficiently securely in a memory cell, and that the other memory cells are simultaneously protected against an undesired change in the memory content during a programming or reading process.

This increases the hold time and improves the robustness of the memory arrangement.

The heat dissipation structure is clearly a heat bath with a sufficiently large heat capacity so that a high one

Amount of heat, such as occurs during programming of the storage areas, can be absorbed by the heat dissipation structure, and at most a very small proportion of the heat released is transferred to adjacent storage cells. As a result, these neighboring memory cells are protected from being undesirably reprogrammed. The storage arrangement according to the invention has the advantage that it can be scaled with increasing integration density, since the energy to be injected is proportional to the volume of a storage area. Furthermore, very good write and read times can be achieved with the memory arrangement, for example much better than with flash memories. Furthermore, very low write and read voltages (of the order of one volt) are sufficient, whereas high voltages of typically 10 volts and more are required for flash memories. This saves energy, the waste heat is reduced and sensitive integrated components are protected against unwanted influences by high electrical voltages.

Preferred developments of the invention result from the dependent claims.

The memory arrangement of the invention can be set up in such a way that an electrical write signal can be selectively applied to each of the storage areas, which is set up in such a way that the value of its electrical resistance for the respective storage area is set to the first or the second value , Alternatively, an electrical read signal can be applied which is set up in such a way that the value of its electrical resistance can be detected for a respective memory area. Particularly when an electrical write signal is applied, sufficiently high electrical currents are required to reprogram the memory content of a memory area. Due to the use of the heat dissipation structure according to the invention, however, memory areas adjacent to a programmable memory area are protected against undesired reprogramming during programming. The heat dissipation structure can be set up in such a way that when the write signal is applied to a respective memory area for setting the value of an electrical resistance, the heat resulting from the write signal is dissipated in such a way that the other memory areas result from a change in their electrical resistance of the write signal are protected.

The write signal can be, in particular, an electric current with a predeterminable strength, which can be applied to a respective memory area for a predefinable time.

At least some of the storage areas are preferably at least partially surrounded by a heat insulation structure, which is set up in such a way that they have the

Heat coupling between the associated storage area and the other storage areas prevented. Particularly in the case of short heating pulses, as are typically required to move a storage area from a state with the low electrical resistance to a state with the high electrical resistance, the heat insulation structure can prevent or at least reduce the heat dissipation from a respective storage area. As a result, the amount of heat in the memory area to be reprogrammed is located with sufficient certainty so that the memory area to be reprogrammed can be safely reprogrammed and adjacent memory areas are protected against unwanted programming.

Clearly, due to the functionality of the thermal insulation structure, with short heating pulses (typically 5ns), as are required to generate the state of the storage area with a high electrical resistance, almost all of the heat remains within the selected storage area. With longer heating pulses (typically 100 ns), as are often required to convert the storage area into a state with the low electrical resistance, part of the heat is given off to the heat dissipation structure, the heat structure preferably being set up in such a way that it is only slightly warmed up.

The memory arrangement can be set up in such a way that each of the memory areas can be switched between an amorphous and a crystalline phase (ie in particular a lattice structure), the memory area having the first value in the crystalline phase and the second value of the electrical resistance in the amorphous phase ,

The memory areas of the memory arrangement are preferably set up in such a way that the crystalline phase can be set for a first time interval by applying the write signal and that the amorphous phase can be set for a second time interval by applying the write signal, the first time interval being greater than the second time interval.

The crystalline phase of the storage area is clearly generated by heating by applying a heating signal for a sufficiently long time (or by cooling it slowly enough). An amorphous phase can be generated by exposing the storage area to a brief heating signal (or cooling it down sufficiently quickly).

The storage areas preferably have a chalcogenide material, in particular an alloy Ge _x Sb _y Te _z (germanium, antimony, tellurium). Such materials have the advantage that they can be reprogrammed using sufficiently small electrical currents with short programming times (5ns or 100ns). The difference in the electrical resistances in the two phase states is significant, so that programming and reading of memory information that is robust in error is made possible. typical Values of the electrical resistances of chalcogenide storage areas are in the range of lkΩ for the crystalline phase and in the range of lOOkΩ for the amorphous phase.

As an alternative to chalcogenides, any other material can be used, which can be selectively converted into an amorphous or crystalline state by means of tempering. The material combination of crystalline silicon / amorphous silicon is to be mentioned as an example of a further suitable material, which is particularly advantageous for the integrability of the memory arrangement according to the invention into silicon microtechnology.

The material of the heat dissipation structure is preferably a metal, polycrystalline silicon or an aluminate (in particular aluminum oxide, Al0 ₃ ). When using a metal, the advantageous effect can be used that metals typically have a thermal conductivity which is a factor of a hundred greater than that under typical conditions

Insulators. As a result, a heat bath is created which is suitable for distributing heat quantities accumulating during the programming of storage areas with sufficient certainty over the storage arrangement according to the invention and thus protecting storage areas which are not to be reprogrammed from an undesired change in their phase state and thus storage state.

In the memory arrangement according to the invention, the insulation structure can be set up such that it electrically decouples the associated memory area from the other memory areas.

In other words, the heat insulation structure can be set up and function not only for heat insulation, but also for electrical decoupling. For example, the thermal insulation structure can be a cavity or it can be made of an electrically insulating material. In particular, the heat insulation structure can be made from silicon oxide (Si0 ₂ ) or silicon nitride (Si ₃ N).

The storage areas are preferably arranged in a matrix on and / or in the substrate. The heat dissipation structure can surround the storage areas essentially in a lattice shape. Alternatively, the heat dissipation structure can also surround the storage areas in a zigzag, meandering, or other functionally suitable form.

A substrate is particularly suitable as a substrate, furthermore in particular a silicon substrate. However, any other substrate (for example glass, ceramic) can also be used.

At least a part of the storage areas can have a heating element which is thermally conductively coupled to the respective storage area and by means of which the heating element can be coupled

Storage area thermal energy can be supplied. By coupling a heating element, preferably made of a material with a sufficiently high ohmic resistance, to a respective storage area, it is ensured that the heating element is heated sufficiently strongly when an electric current is applied, as a result of which the storage area coupled to it is also heated in a spatially defined manner , The heating element can have tungsten and / or polycrystalline silicon.

It should be noted that the configurations described above for the memory arrangement according to the invention also apply to the method for operating a memory arrangement or for the method for producing a memory arrangement. Exemplary embodiments of the invention are shown in the figures and are explained in more detail below.

Show it:

Figures 1A to 1E layer sequences to different

Times during a method for producing a memory arrangement according to a first exemplary embodiment of the invention,

FIG. 2 shows a layout view of a memory arrangement according to the first exemplary embodiment of the invention,

FIG. 3 shows a cross-sectional view of a memory arrangement according to the first exemplary embodiment of the invention,

FIG. 4 shows a cross-sectional view of a memory arrangement according to a second exemplary embodiment of the invention,

Figure 5A is a schematic cross-sectional view of a

Memory area of the memory arrangement according to the invention,

FIG. 5B shows another schematic cross-sectional view of a memory area of a memory arrangement according to the invention,

Figure 6 shows a memory cell according to the prior art.

The same or similar components in different figures are provided with the same reference numbers.

A method for producing a memory arrangement according to a first exemplary embodiment of the invention is described below with reference to FIGS. 1A to 1E. This method shows a 6F ² cell field based in part on the DRAM technology. Alternatively, any other cell array from DRAM technology can be used to apply the invention to this technology.

In order to obtain the layer sequence 100 shown in FIG. 1A, n ⁺ -doped regions 102 to 104 are formed in a silicon substrate 101 as first to third source / drain regions. Furthermore, first and second silicon oxide regions 105, 106 are formed in surface regions of the silicon substrate by etching trenches and filling the trenches with silicon oxide material. An electrical decoupling of different memory cells of a memory arrangement to be formed is clearly realized by means of the silicon oxide regions 105, 106. Furthermore, first and second word lines 107, 108 are made of an electrically conductive material on the substrate 101 in regions between the first source / drain region 102 and the second source / drain region 103 and between the second

Source / drain region 103 and the third source / drain region 104 are formed, a thin silicon oxide film being formed as a gate insulating layer between the substrate 101 and the word lines 107, 108. At the second source / drain region 103, a common

Drive line 111 made of polycrystalline silicon. First and second auxiliary structures 109, 110 are constructed like the word lines 107, 108 and serve to set a self-aligned contact between the lines 108, 110 and 109, 107. The control line 111 can be generated in a self-aligned manner between the word lines 107, 108. Furthermore, the layer sequence thus obtained is encapsulated with silicon oxide material, whereby a silicon oxide encapsulation 112 is formed.

In order to obtain the layer sequence 120 shown in FIG. 1B, a lithography and an etching Process trenches 121 etched into silicon encapsulation 112, thereby exposing the first and third source / drain regions 102, 104. Furthermore, doped polysilicon material is introduced into the trenches 121 and etched back, as a result of which first heating element components 122 are formed. Subsequently, tungsten material is deposited in the trenches 121 on the first heating element components 122, as a result of which second heating element components 123 are formed.

In order to obtain the layer sequence 140 shown in FIG. IC, chalcogenide material (Ge _x Sb _y Te _z ) is deposited on the surface of the layer sequence 120 and a part of the chalcogenide material is etched back, whereby chalcogenide structures 141 are formed. Silicon oxide material of silicon oxide encapsulation 112 is also etched back.

In order to obtain the layer sequence 160 shown in FIG. 1D, the exposed chalcogenide structures 141 are surrounded by lateral silicon oxide spacers 161 by means of deposition and etching back of silicon oxide material. Furthermore, copper material or aluminum material is deposited on the surface of the layer sequence thus obtained and etched back, as a result of which a copper-metal grid 162 (alternatively an aluminum-metal grid), embedded between adjacent ones, is electrically and thermally conductive from the surroundings by means of the silicon oxide spacers 161 largely decoupled chalcogenide structures 141, is formed. Furthermore, additional silicon oxide material is deposited on the surface of the layer sequence obtained in this way and planarized using a CMP process ("chemical mechanical polishing").

In order to obtain the memory arrangement 180 shown in FIG. 1E, metal material is deposited on the layer sequence 160 and structured to form a bit line 181 using a lithography and an etching method. The functionality of the memory arrangement 180 according to the first exemplary embodiment of the invention is described below with reference to FIG. 1E.

The memory information of the respective memory cell is clearly stored in the phase state of the chalcogenide structures 141. The memory arrangement 180 from FIG. 1E shows two memory cells, belonging to the two chalcogenide structures 141. The chalcogenide structures 141 can each be in a crystalline state in which the electrical resistance of the chalcogenide structures 141 is lower than in an amorphous one Status. By applying an electrical current, a selected chalcogenide structure 141, supported by the heating element components 122, 123, is heated so strongly that depending on the length of the application of the pulse (or depending on the cooling rate and the strength of the pulse) Chalcogenide structures 141 can be selectively brought into the crystalline or amorphous state. By applying a sufficiently long heating signal (typically 100ns), the chalcogenide structure 141 is brought into the crystalline state, by applying a sufficiently short heating signal (typically 5ns), the respective chalcogenide structure 141 is brought into the amorphous state. In order to localize the resulting amount of heat in the immediate vicinity of the respective chalcogenide structure 141 when the heating pulses are applied, the chalcogenide structures 141 are surrounded with the silicon oxide spacers 161 as thermal and electrical insulators. If, which can occur in particular in the case of a longer heating pulse, part of the heat of the chalcogenide structures 141 can pass through the associated silicon oxide spacer 161, this heat is released to the metallic grid 162, which heats up only slightly. Thus, there are other chalcogenide structures 141 that are not the subject of a programming process in the present scenario should be protected from unintentionally experiencing a change in their phase state (crystalline or amorphous).

The following describes how information is programmed into the left of the chalcogenide structures 141 shown in FIG. 1E. For this purpose, the left chalcogenide structure 141 is first selected as the memory cell of the memory arrangement 180 by applying an electrical voltage to the first word line 107, clearly the gate region of a selection transistor, such that the region of the substrate 101 (channel Region) between the first and the second source / drain regions 102, 103 is electrically conductive. By applying a sufficiently strong heating current as a result of a programming signal to the common drive line 111, the electrical heating signal is conducted through the channel region via the heating element components 122, 123 into the left chalcogenide structure 141, as a result of which the chalcogenide structure 141 is strongly heated. The chalcogenide structure 141 is converted into an amorphous state with a high electrical resistance by means of a sufficiently short heating pulse; with a sufficiently long heating pulse, the chalcogenide structure 141 is converted into a crystalline state with a low ohmic resistance. The heating element components 122, 123 are formed from a sufficiently high-resistance material so that ohmic heat resulting from the heating signal is generated in the heating element components 122, 123, which heat heats the associated chalcogenide structure 141. For example, the crystalline state of the chalcogenide structure 141 with the low value of the ohmic resistance can be assigned a logic value "1", and the amorphous state of the chalcogenide structure 141 with the high value of the ohmic resistance can be assigned a logic value "0" be assigned.

In order to read out information stored in one of the chalcogenide structures 141, such an electrical voltage is again applied to the first word line 107. that the common drive line 111 is coupled to the bit line 181 via the chalcogenide structure 141. If an electrical read signal (for example a sufficiently small electrical current that does not change the state of the associated chalcogenide structure) is now applied, it flows depending on whether the chalcogenide structure 141 is in the amorphous state with the high ohmic resistance or in the crystalline state State with the low ohmic resistance is on the bit line 181, a large or a smaller electrical current that is detected. In this way, the storage information can be read out.

2, a layout top view 210 of the memory arrangement 180 according to the first exemplary embodiment of the invention is described below.

In particular, FIG. ² shows that the 6F ² memory cells 200 of the memory arrangement 180 are arranged in a matrix. F is the minimum structural dimension that can be achieved in a technology generation. The bit lines 181 run along a first direction, whereas the word lines 107, 108 run along a direction orthogonal thereto. It should be noted that the silicon oxide spacers 161 and the metal grid 162 are not shown in FIG.

A sectional view 300 of the memory arrangement 180 along a section line I-I 'shown in FIG. 1E is described below with reference to FIG.

The memory arrangement 180 contains memory cells with a space requirement of 6F ² per memory cell, each of the memory cells, as shown in FIG. 3, having a chalcogenide structure 141 and a silicon oxide spacer 161 surrounding them. Each of the memory cells is embedded in the grid-shaped metal grid 162 as a heat dissipation structure. The silicon oxide spacers 161 serve as a heat insulation structure. Particularly in areas 301 of the memory arrangement 180, in which adjacent memory cells are arranged closely adjacent, the provision of the heat dissipation structure and the heat insulation structure is decisive in order to prevent thermal crosstalk between adjacent memory cells.

A memory arrangement 400 according to a second exemplary embodiment of the invention is described below with reference to FIG.

The memory arrangement 400 essentially corresponds to the memory arrangement 180, but is designed as a memory arrangement with an area requirement of 4F ² per memory cell, that is to say with an even greater integration density than the memory arrangement 180.

In the storage arrangement 400, the individual memory cells, each having a chalcogenide structure 141 and a silicon oxide spacer 161 surrounding them, are in turn embedded in a grid-shaped metal structure 162. In contrast to the storage arrangement 180, the memory cells in the storage arrangement 400 are regularly arranged in a lattice shape, that is to say in the horizontal direction or in the vertical direction at a fixed distance from one another in each case.

5A, 5B, an estimation of the heat exchange characteristic between a chalcogenide structure 141 and its surroundings is carried out, wherein the chalcogenide structure 141 is surrounded by an o-cylindrical silicon oxide spacer 161 to which the metal structure 162 borders. FIG. 5A shows a cross-sectional view 500, and FIG. 5B shows a top view 501 of the structure. The height of the cylindrical chalcogenide structure 141 or of the hollow cylindrical silicon oxide spacer 161 is assumed to be 100 nm, the diameter of the chalcogenide structure 141 is assumed to be 50 nm and the thickness of the hollow cylinder wall of the silicon oxide spacer 161 is assumed to be 10 nm.

The volume of the chalcogenide cylinder 141 is 2-10 ^_22 m ³ .

The dissipated power ΔP in the cylindrical volume with the height of 100 nm and the diameter of 50 nm during programming results in

ΔP = 0.2mA x 0.5V = 0.1mW (1)

if 0.2mA current and 0.5V voltage are assumed. This corresponds to a heat generated in a time of Δt = 100ns when programming the crystalline state (5ns when programming the amorphous state) of:

ΔQp _ro g = ΔP Δt = 10 ^{~ n} J (5-10 ^{~ 13} J) (2)

The heat flow through a cross section with the surface A and the length L of the insulator 161 surrounding the chalcogenide structure 141 results with a thermal conductivity λ and a temperature difference Δt

ΔQ _ab / Δt = A / L λ ΔT (3)

For the given dimensions and the given materials, a heat quantity of

can be removed from the side walls of the volume if ΔT = 600K is assumed. This corresponds to a transported energy in a time of 100ns (5ns)

ΔQ _ab = l-10 ^"10 J (0.5-10 ^{" u} J) (4) This leads to heating of the cylindrical volume of the chalcogenide structure 141 in FIG. 5ns

ΔT = ΔQ _prog (Δt = 5ns) / C _v V = 1000K (5)

for the above volume in the case of ideal insulation.

A thickness of the silicon oxide spacers 161 of 10 nm is sufficient for good insulation, since the heat removed in 5 ns is smaller than the heat produced.

Since the melting point of chalcogenides is around 900K, the heating caused is large enough to bring about a change in phase.

With a volume of chalcogenide structure 141 with a diameter of 50 nm and a height of 100 nm, a programming current of approximately 0.2 mA or more is a good choice.

Furthermore, the heating of the surrounding metal 162 is calculated. Under typical operating conditions, metal conducts approximately 100 times better than silicon dioxide. Therefore, a volume roughly 100 times larger than the volume of the chalcogenide structure 141 and the silicon oxide spacer 161 is heated within 100 ns by:

ΔT = Q _prog (Δt = 100ns) / C _v V = 10K [6]

Therefore, a metal absorbs most of the energy without being significantly heated, provided that for each cell to be programmed a metal volume of approximately 100 times the volume of the cell is provided.

In a block of 256 x 256 cells, 256 cells can be programmed in parallel. In the proposed layout, the metal volume for a unit cell is V _m = 3-V _C haikogenxd. As a result, each cell has a metal volume of approximately 700 times the volume of a cell volume. The proposed layout therefore helps to dissipate the energy from the programming cell into the surrounding area without significantly heating up neighboring cells.

The following publications are cited in this document:

[1] Lai, S, Lowrey, T "OUM - A 180nm Nonvolatile Memory Cell Element Technology For Stand Alone and Embedded Applications", 2001 International Electron Devices

Meeting, December 5, 2001

[2] Gill, M, Lowrey, T, Park, J "Ovonic Unified Memory - A High-Performance Nonvolatile Memory Technology for Stand Alone Memory and Embedded Applications", IEEE

International Solid State Circuits Conference, February 4-6, 2002, Session 12, Section 12.4

LIST OF REFERENCE NUMBERS

100 sequence of layers

101 silicon substrate

102 first source / drain region

103 second source / drain region

104 third source / drain region

105 first silicon oxide area

106 second silicon oxide region

107 first word line

108 second word line

109 first auxiliary structure

110 second auxiliary structure

111 common control line

112 silicon oxide encapsulation

120 layer sequence

121 trenches

122 first heating element components

123 second heating element components

140 sequence of layers

141 chalcogenide structures

160 sequence of layers

161 silicon oxide spacers

162 metal grille

163 silicon oxide intermediate layer

180 spear arrangement

181 bit line

200 6F ² memory cell 210 layout top view 300 sectional view 301 areas 400 memory arrangement

500 cross section

501 top view 600 memory cell 601 first electrode

602 second electrode

603 heating element

604 Ge _x Sb _y Te _z layer

605 programmable area

Claims

claims:

1. Storage arrangement with

• a substrate; A plurality of storage areas formed on and / or in the substrate, each of which is set up in such a way that the electrical resistance of the respective storage area can be selectively set to a first value or to a second value by means of thermal treatment, which is greater than the first Value;

A heat dissipation structure arranged between the storage areas for dissipating heat supplied to one of the storage areas.

2. Storage arrangement according to claim 1, which is set up such that it is selective to each of the memory areas

• An electrical write signal can be applied, which is set up in such a way that for the respective

Memory area the value of its electrical resistance is set to the first or the second value; or

• An electrical read signal can be applied, which is set up in such a way that for a respective

Memory area the value of its electrical resistance is detectable.

3. Storage arrangement according to claim 2, in which the heat dissipation structure is set up in such a way that when the write signal is applied to a respective storage area for setting the value of its electrical resistance, the heat resulting from the write signal is dissipated in such a way that the other memory areas are protected from a change in their electrical resistance as a result of the write signal.

4. Storage arrangement according to one of claims 1 to 3, wherein at least a part of the storage areas is at least partially surrounded by a heat insulation structure which is set up in such a way that it reduces the heat coupling between the associated storage area and the other storage areas.

5. Memory arrangement according to one of claims 1 to 4, wherein each of the memory areas is switchable between an amorphous and a crystalline phase, the

Storage area in the crystalline phase has the first value and in the amorphous phase the second value of the electrical resistance.

6. The memory arrangement as claimed in claim 5, in which the memory areas are set up in such a way that the crystalline phase can be set for a first time interval by applying the write signal and that the amorphous phase can be set for a second time interval by applying the write signal, wherein the first time interval is greater than the second time interval.

7. The memory arrangement as claimed in claim 6, in which the memory regions comprise a chalcogenide material.

8. memory arrangement according to claim 7, wherein the memory areas have Ge _x Sb _y Te ₂ .

9. Storage arrangement according to one of claims 1 to 8, wherein the material of the heat dissipation structure

• a metal;

• polycrystalline silicon; or

• is an aluminate.

10. Speieher arrangement according to one of claims 4 to 9, in which the heat insulation structure is set up in such a way that it electrically decouples the associated storage area from the other storage areas.

11. Storage arrangement according to one of claims 4 to 10, wherein the heat insulation structure

• silicon oxide; or

• Silicon nitride is produced.

12. Storage arrangement according to one of claims 1 to 11, in which the storage areas are arranged in a matrix on and / or in the substrate and in which the heat dissipation structure substantially surrounds the storage areas in a lattice shape.

13. Storage arrangement according to one of claims 1 to 12, in which at least a part of the storage areas has a heating element coupled to the respective storage area in a thermally conductive manner, by means of which thermal energy can be supplied to the respective storage area.

14. Storage arrangement according to claim 13, wherein at least one heating element

• tungsten; and / or • has polycrystalline silicon.

15. Method for operating a memory arrangement

• with a memory arrangement with o a substrate; o a plurality of storage areas formed on and / or in the substrate, each of which is set up in such a way that the electrical resistance of the respective storage area is selectively applied to a first by means of thermal treatment

Value or adjustable to a second value that is greater than the first value; o a heat dissipation structure arranged between the storage areas for dissipating heat supplied to one of the storage areas;

• wherein according to the method o an electrical write signal is applied which is set up in such a way that the value of its electrical resistance is set to the first or the second value for the respective memory area; or o an electrical read signal is applied which is set up in such a way that the value of its electrical resistance can be detected for a respective memory area.

16. A method of manufacturing a memory array in which

• A plurality of storage areas is formed on and / or in a substrate, each of which is set up in such a way that the electrical resistance of the respective storage area is by means of thermal

Treatment is selectively adjustable to a first value or to a second value that is greater than the ■ first value;

• a heat dissipation structure between the storage areas for removal from one of the storage areas

Heat is arranged.