WO2004025693A2 - Method for the production of a semi-conductive structure comprising a plurality of gate stacks arranged on a semi-conductor substrate and corresponding semi-conductive structure - Google Patents

Method for the production of a semi-conductive structure comprising a plurality of gate stacks arranged on a semi-conductor substrate and corresponding semi-conductive structure Download PDF

Info

Publication number
WO2004025693A2
WO2004025693A2 PCT/EP2003/008946 EP0308946W WO2004025693A2 WO 2004025693 A2 WO2004025693 A2 WO 2004025693A2 EP 0308946 W EP0308946 W EP 0308946W WO 2004025693 A2 WO2004025693 A2 WO 2004025693A2
Authority
WO
WIPO (PCT)
Prior art keywords
gate
gsl
gate stacks
channel doping
semiconductor substrate
Prior art date
Application number
PCT/EP2003/008946
Other languages
German (de)
French (fr)
Other versions
WO2004025693A3 (en
Inventor
Gerhard Enders
Jürgen Faul
Björn Fischer
Lars Heineck
Matthias Hierlemann
Martin Popp
Peter Voigt
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Publication of WO2004025693A2 publication Critical patent/WO2004025693A2/en
Publication of WO2004025693A3 publication Critical patent/WO2004025693A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts

Definitions

  • the present invention relates to a method for producing a semiconductor structure with a plurality of gate stacks on a semiconductor substrate and a corresponding semiconductor structure.
  • Planar selection transistors for DRAM memory devices reach technological limits at gate lengths below 100 nm, since on the one hand sufficient switching behavior of the transistors produced must be guaranteed and on the other hand the occurring electric fields in the transition or junction area must be controllable , In particular, taking into account the inevitable tolerances in the core production process, such a high doping in the channel would have to be selected for setting the threshold voltage that the resulting electric fields led to an insufficient retention period of the stored charge (retention).
  • the object on which the present invention is based is to improve the scalability of planar array selection transistors, in particular for gate lengths below 100 nm, and also to improve the device properties. Shafts of planar logic transistors to be provided by field reduction in transistors in unidirectional operation.
  • An advantage of the method according to the invention for producing a semiconductor structure is that a further downsizing of DRAM memory cells is possible, which justifies a cost advantage.
  • the application is also advantageous for all DRAM circuits with very strongly scaled planar transistors, since transistors that are as short as possible with ideal switch properties (on-off current ratio) with the lowest possible gate voltage swing are required.
  • Further advantageous applications are in highly integrated circuits, since the semiconductor structure generated in the production method according to the invention enables an increased driver current with a low connection resistance in the drain region due to the reduction in the halo or well doping concentration near the source / drain surface. This also reduces the drain-side field of the transistor, which is responsible for degradation effects due to "not carrier” or "non-conducting stress". However, this is only possible if the source and drain are defined on the design side (e.g. in unidirectional operation).
  • the idea on which the invention is based essentially consists in introducing one-sided doping into a transistor (for example boron for an n-channel transistor), specifically in a self-aligned manner with respect to the gate edge after the gate stack has been produced.
  • a transistor for example boron for an n-channel transistor
  • this is done, depending on the layout of the cell, for example by means of an appropriate photo mask on which the side of the device to be implanted is exposed.
  • an appropriate photo mask on which the side of the device to be implanted is exposed.
  • Stripe mask is used, in contrast to an LM block mask with a checkerboard layout.
  • the additional doping is introduced through a mask opened on the source side. In both cases, this additional doping increases the potential barriers and thus increases the threshold voltage in the short-channel region of the transistors. In addition, in the case of logic transistors, the device current is increased by the associated "velocity" overshoot.
  • the implantation of the doping is carried out after the etching of the gate stack directly before or during the so-called sidewall oxidation. Subsequent oxidation of the gate sidewall causes the dopant to diffuse under the gate edge.
  • the doping concentration near the exposed surface next to the gate or in the so-called source / dram region is reduced by segregation (Aoreich für ms arising oxide), while the concentration at the gate edge by an oxygen-enhanced diffusion increases.
  • the above-mentioned problem is solved in particular by applying gate stacks to a gate dielectric over a semiconductor substrate, implanting self-aligned doping to edges of the gate stacks, and sidewall oxide on exposed rare walls of the gate Stack is generated with simultaneous formation under the gate edge of diffused doping regions.
  • the gate stacks are placed approximately equidistant from one another and under each A storage capacitor is arranged in the semiconductor substrate in the second adjacent gate stack.
  • the implantation of the doping takes place asymmetrically from a predetermined direction at a predetermined angle.
  • the gate stacks are applied approximately equidistant from one another, alternating under every third or first adjacent one
  • a storage capacitor is arranged in the gate stack in the semiconductor substrate.
  • a mask is provided between every second pair of gate stacks before the doping is implanted.
  • the doping is implanted from two predetermined directions in each case at a predetermined angle.
  • the doping after the implantation is diffused through a predetermined, extra tempering step.
  • the sidewall oxidation is divided into two or more sub-steps, with the doping implantation taking place between sub-steps.
  • the doping is implanted on only one side of the gate stack.
  • the method is used to manufacture logic transistors or logic circuits, especially for DRAMs.
  • the method is used to manufacture selection transistors. These selection transistors are preferably separated from one another by STI (Shalow Trench Isolation) trenches.
  • STI Shalow Trench Isolation
  • the gate stacks are produced with a length of less than 100 nm.
  • the gate stacks are provided in parallel in the form of strips on the semiconductor substrate.
  • the gate stacks have a lower first layer made of a polysilicon and an overlying second layer made of a metal silicide or a metal.
  • the first, the second layer lying thereon and a third layer arranged thereon are applied and structured on the gate dielectric.
  • the third layer has silicon nitride or oxide.
  • sidewall spacers are preferably provided on the rare sides of the gate stack, preferably made of silicon oxide or oxide. Exemplary embodiments of the invention are shown in the drawings and are explained in more detail in the description below.
  • 1 to 4 are schematic representations of successive stages in the manufacturing process to explain a first embodiment of the present invention.
  • 5 to 8 are schematic representations of successive stages in the manufacturing process to explain a second embodiment of the present invention.
  • Storage capacitors TK1, TK2, TK3 and TK4 are arranged vertically to the surface of the semiconductor substrate 1 in a semiconductor substrate 1.
  • a dielectric 5 is applied over the semiconductor substrate 1, which dielectric is used to passivate the
  • Semiconductor substrate 1 is used.
  • a plurality of gate stacks GS1 to GS8 are applied approximately equidistantly to the gate dielectric 5, each gate stack preferably being provided in three layers 10, 20 and 30 of the same structure.
  • the first gate stack layer 10, which directly adjoins the gate dielectric 5, preferably has polysilicon.
  • the gate stacks GS1 to GS8 preferably extend parallel and in strip form in the plane of the drawing and essentially have the same dimensions.
  • ST denotes STI (shallow trench isolation) trenches which separate the cells from one another. For reasons of clarity, these STI (shallow trench isolation) trenches are not mentioned further below or are not shown in the further drawings.
  • the storage capacitors TK1, TK2, TK3 and TK4 are arranged such that alternately every third or first gate stack GS1, GS4, GS5 and GS8 come to lie above a capacitor TK1, TK2, TK3, TK4.
  • FIG. 2 shows the semiconductor structure according to FIG. 1 in a subsequent stage of the manufacturing process.
  • a, preferably photolithographically structured, mask M is provided, with a mask section M between two gate stacks, e.g. GSl and GS2, and one of the gate stacks GSl is located above a capacitor TKl, whereas the laterally adjacent gate stack GS2 is not located above a storage capacitor.
  • Such a mask section M preferably extends in the vertical direction over the gate stacks, e.g. GSl, GS2, and is structured in width in such a way that an implantation beam used from a predetermined direction II, 12 for doping the semiconductor substrate 1 in the areas not covered by the mask is not impaired by the mask or the mask sections M.
  • a dopant is implanted in the semiconductor substrate 1 in areas not covered by the mask sections M, the implantation taking place from one or two predetermined directions II, 12 and doping accordingly 100, 110, 105, 120, 130 preferably self-aligned to the gate edge in the semiconductor substrate 1.
  • a dopant in the case of an n-channel transistor is, for example, boron, which according to the first embodiment is introduced into the semiconductor substrate 1 with the mask sections M using a stripe mask.
  • a doping 100, 110, 105, 120 and 130 is only provided on one side or gate edge of a corresponding gate stack GS2, GS3, GS4, GS5, GS ⁇ , GS7, which leads to an asymmetrical design.
  • the regions 105 lie in the STI trench and have no electrical function or can also be omitted by suitable masking.
  • FIG. 3 shows the semiconductor structure according to FIG. 2 after further method steps according to the first embodiment of the present invention.
  • a sidewall oxidation is carried out over the oxidizable rare walls of the two lower gate stack layers 10, 20, whereby a sidewall oxidation layer 40 is formed.
  • the dopant profiles of the dopings 100 ', 110', 120 ', 130' change in the semiconductor substrate 1, in particular in the source junction area.
  • the distribution of the dopants in the semiconductor substrate 1 is possible for use a specifically set extra tempering step or to divide the sidewall oxidation into two or more sub-steps, the implantation of the doping, as with reference to FIG. 2 shown, is executed between individual substeps.
  • the spatial distribution of the dopants 100 ', 110', 120 ', 130' can be optimized.
  • the sidewall oxidation is thus used to generate predetermined suitable dopant profiles, which can also be generated by a multi-stage sequence of anneals and / or oxidations.
  • the dopings 100 ', 110', 120 'and 130' which have changed their concentration profile in the course of the sidewall oxidation accordingly extend by diffusion under the gate edge of the corresponding gate stacks GS2, GS3, GS ⁇ and GS7.
  • the potential barrier on the source side of the device can be influenced, i.e. using the segregation (depletion of the doping into the resulting oxide) in the oxide growing on the transition or junction regions and diffusion under the gate edge. are designed, and the junction fields (E fields) on the drain side are greatly reduced.
  • the segregation depletion of the doping into the resulting oxide
  • the junction fields (E fields) on the drain side are greatly reduced.
  • boron in an n-FET device a lower one
  • junction series resistance can be generated without the desired increase in the potential barrier suffering.
  • Fig. 4 shows a semiconductor structure according to Fig. 3 after steps following in the manufacturing process, a side wall spacer 50, e.g. made of silicon nitride, are applied over the side walls of the gate stacks GS1 to G ⁇ 8 or over the side wall oxide layers 40.
  • active semiconductor regions 60, 61, 62, 63, 64 and 65 were formed between the corresponding gate stacks GS1 to GS8. Further manufacturing steps such as removing the gate dielectric and subsequent provision of a contacting device (not shown in each case) should only be mentioned in addition.
  • a semiconductor structure produced in this way with asymmetrical doping which is immediately before, immediately after and / or Adjusting the concentration profile of the sidewall oxidation by diffusion improves the short-channel behavior of the transistor and at the same time reduces the electrical fields on the drain side of the device.
  • the drain side is the node or node side with the storage capacitor, while in the case of a logic application it is the side of the device with the higher potential characterized.
  • this method can be used both for n- and for p-FET structures or devices using appropriate species or substrate dopant combinations, the diffusion under the gate and the segregation in the on the source / drain Oxide growing region depends heavily on the dopant used.
  • FIG. 5 shows a semiconductor structure which differs essentially from the semiconductor structure according to FIG. 1 in that the storage capacitors TKl 1 , TK2 ', TK3' and TK4 ', which are arranged vertically in the semiconductor substrate 1, under every second, laterally adjacent Gate stacks GS1, GS3, GS5 and GS7 are provided. This corresponds to a checkerboard layout. Strip-shaped STI trenches can also be provided with this layout, but are not visible in this section.
  • FIG. 6 shows the semiconductor structure according to FIG. 5, with doping 105 ′ *, 110 ′′, 120 ′′, 130 ′′ and 140 ′′ on the right edges of the gate stacks GS1 to GS8 without using a mask an angled implantation II 'are provided in the semiconductor substrate 1.
  • the explanation given with reference to FIG. 2 applies to the predetermined implantation angle .alpha.
  • implantation is carried out only from one direction II ', namely for each adjacent gate stack GS1 to GS8 on the same side in the region of the Transition between the gate dielectric 5 and the first gate stack layer 10 in Semiconductor substrate.
  • the implantation can also be carried out from the corresponding other direction (not shown), a negative angle ⁇ occurring and the other edge region of each gate stack GS1 to GS8 at the transition between the gate dielectric 5 and the first gate stack layer 10 in Semiconductor substrate 1 m_t is provided with a corresponding doping.
  • FIG. 7 shows an arrangement according to FIG. 6 after process steps following in the manufacturing process.
  • a sidewall oxidation 40 is generated over the oxidizable rare walls of the gate stacks GS1 to GS8, during which the doping at the gate edges 110 '' ', 120' '', 130 '' * , 140 '' 'of the gate stacks GS2, GS4, GS6 and GS8, which are not arranged above a storage capacitor, diffuses under the corresponding gate edge.
  • FIG. 7 shows an arrangement according to FIG. 6 after process steps following in the manufacturing process.
  • a specifically set extra tempering step can be provided or the sidewall oxidation can be divided into two or more sub-steps and the implantation of the doping substance, which with reference was explained in FIG. 6, executable in between, in order to generate an optimized spatial doping concentration distribution.
  • FIG. 8 shows a structure in accordance with FIG. 7, a side wall spacer 50, which preferably being made of silicon, being applied over the rare walls or the side wall oxide 40 of the gate stacks GS1 to GS8.
  • active semiconductor regions 60 ', 61', 62 ', 63', 64 ', 65', 66 'and 67' are provided, which after a subsequent removal of the gate dielectric 5 in from the encased gate stack 10, 20, 30 , 40 and 50 uncovered areas between the individual gate stacks GS1 to GS8 are used for connection to an electrical contact device (not shown).
  • the layer materials for the gate stacks, their arrangement and the dopant mentioned are only examples.
  • the present invention and the object on which it is based can in principle be applied to any integrated circuits, although they have been explained with reference to integrated DRAM memories or logic circuits in silicon technology.
  • both n- and p-channel field-effect transistors or devices can be implemented.
  • sidewall spacers e.g. made of silicon nitride

Abstract

The invention relates to a method for the production of a semi-conductor structure comprising a plurality of gate stacks (GS1 - GS8) which are arranged on a semi-conductor substrate (1). Said method comprises the following steps: applying the gate-stack (GS1 - GS8) to a gate dielectric (5) via the semi-conductor substrate (1); implanting doping (100, 105, 110, 120, 130; 105''', 110''', 120''', 130''', 140''') which is self-adjusted in relation to the edges of the gate stack (GS1 - GS8); and forming an side wall oxide (40) on the free side walls of the gate stack (GS1 - GS8) while at the same time forming diffused doping areas (100', 110', 120', 130'; 110''', 120''', 130''', 140''') below the gate stack. The invention also relates to said type of semi-conductor structure.

Description

Beschreibungdescription
Verfahren zur Herstellung einer Halbleiterstruktur mit einer Mehrzahl von Gate-Stapeln auf einem Halbleitersubstrat und entsprechende HalbleiterstrukturMethod for producing a semiconductor structure with a plurality of gate stacks on a semiconductor substrate and corresponding semiconductor structure
Die vorliegende Erfindung betrifft ein Verfahren zur Herstellung einer Halbleiterstruktur mit einer Mehrzahl von Gate- Stapeln auf einem Halbleitersubstrat und eine entsprechende Halbleiterstruktur.The present invention relates to a method for producing a semiconductor structure with a plurality of gate stacks on a semiconductor substrate and a corresponding semiconductor structure.
Planare Auswahl-Transistoren für DRAM-Speichereinrichtur.gen stoßen bei Gate-Längen unter 100 nm an technologische Grenzen, da einerseits ein ausreichendes Abschaltverhalten der hergestellten Transistoren zu garantieren ist und andererseits die auftretenden elektrischen Felder im Übergangs- bzw. Junction-Bereich kontrollierbar sein müssen. Insbesondere unter Berücksichtigung der im Kerstellungsprozess unvermeidbaren Toleranzen müsste für die Einstellung der Einsatzspannung eine derart hohe Dotierung im Kanal gewählt werden, dass die daraus resultierenden elektrischen Felder zu einer unzureichenden Haltedauer der gespeicherten Ladung (retention) führte.Planar selection transistors for DRAM memory devices reach technological limits at gate lengths below 100 nm, since on the one hand sufficient switching behavior of the transistors produced must be guaranteed and on the other hand the occurring electric fields in the transition or junction area must be controllable , In particular, taking into account the inevitable tolerances in the core production process, such a high doping in the channel would have to be selected for setting the threshold voltage that the resulting electric fields led to an insufficient retention period of the stored charge (retention).
Bei Logik-Transistoren hingegen führen sehr hohe Kanal- bzw. Kalo-Dotierungen, welche zur Verhinderung eines Durchschlags bzw. Punch through nötig sind, durch auftretende hohe Feldstärken zu Problemen in der Zuverlässigkeit an der Drain- Seite. Darüber hinaus erhöhen sich durch die hohen Dotierun- gen die Serienwiderstände auf Source- und Drain-Seite der Halbleitereinrichtung bzw. des Devices.In the case of logic transistors, on the other hand, very high channel or kalo doping, which is necessary to prevent breakdown or punch through, leads to reliability problems on the drain side due to the high field strengths that occur. In addition, the high doping increases the series resistances on the source and drain side of the semiconductor device or of the device.
Die der vorliegenden Erfindung zugrunde liegende Aufgabe besteht darin, die Skalierbarkeit von planaran Array-Auswahl- Transistoren, insbesondere für Gate-Langen unter 100 nm, zu verbessern und ebenfalls eine Verbesserung der Device-Eigen- Schäften planarer Logik-Transistoren durch Feldreduktion bei Transistoren in unidirektionalem Betrieb vorzusehen.The object on which the present invention is based is to improve the scalability of planar array selection transistors, in particular for gate lengths below 100 nm, and also to improve the device properties. Shafts of planar logic transistors to be provided by field reduction in transistors in unidirectional operation.
Erfindungsgemäß wird diese Aufgabe ^durch das in Anspruch 1 angegebene Herstellungsverfahren einer Halbleiterstruktur und die entsprechende Halbleiterstruktur nach Anspruch 19 gelöst.According to the invention this object is achieved by the ^ defined in claim 1 manufacturing method of a semiconductor structure and the corresponding semiconductor structure as claimed in claim 19th
Von Vorteil beim erfindungsgemäßen Verfahren zur Herstellung einer Halbleiterstruktur ist, dass eine weitere Verkleinerung von DRAM-Speicherzellen möglich wird, wodurch ein Kostenvorteil begründet wird. Die Anwendung ist darüber hinaus für alle DRAM-Schaltungen mit sehr stark skalierten planaren Transistoren vorteilhaft, da dort möglichst kurze Transistoren mit möglichst idealen Schaltereigenschaften (on-off current ratio) bei möglichst niedrigem Gate-Spannungshub erforderlich sind. Weitere vorteilhafte Anwendungen liegen bei hochintegrierten Schaltungen, da durch die im erfindungsgemäßen Herstellungsverfahren generierte Halbleiterstruktur aufgrund der Reduktion der Halo- bzw. Wannen-Dotierungskonzentration nahe der Source/Drain-Oberflache ein erhöhter Treiberstrom bei gleichzeitig niedrigem Anschlußwiderstand im Drain-Gebiet ermöglicht wird. Auch reduziert sich dadurch das Drain-seitige Feld des Transistors, das für Degradationseffekte aufgrund von "not carrier-" oder "non conducting-stress" verantwort- lieh ist. Dies ist jedoch nur möglich, wenn Source und Drain Design-seitig definiert werden (z.B. bei unidirektionalem Betrieb) .An advantage of the method according to the invention for producing a semiconductor structure is that a further downsizing of DRAM memory cells is possible, which justifies a cost advantage. The application is also advantageous for all DRAM circuits with very strongly scaled planar transistors, since transistors that are as short as possible with ideal switch properties (on-off current ratio) with the lowest possible gate voltage swing are required. Further advantageous applications are in highly integrated circuits, since the semiconductor structure generated in the production method according to the invention enables an increased driver current with a low connection resistance in the drain region due to the reduction in the halo or well doping concentration near the source / drain surface. This also reduces the drain-side field of the transistor, which is responsible for degradation effects due to "not carrier" or "non-conducting stress". However, this is only possible if the source and drain are defined on the design side (e.g. in unidirectional operation).
Die der Erfindung zugrunde liegende Idee besteht im wesentli- chen darin, eine einseitige Dotierung in einen Transistor einzubringen (z.B. Bor für einen n-Kanal-Transistor) , und zwar selbstjustiert zur Gate-Kante nach Herstellung des Gate- Stack. Bei einer Speichertechnologie erfolgt dies - abhängig vom Layout der Zelle - z.B. durch eine entsprechende Photo- maske, auf der die zu implantierende Seite des Devices aufbelichtet ist. So wird beispielsweise für ein MINT-Layout eine Streifenmaske verwendet, im Gegensatz zu einer l-lme-Block- maske bei einem Checkerboard-Layout.The idea on which the invention is based essentially consists in introducing one-sided doping into a transistor (for example boron for an n-channel transistor), specifically in a self-aligned manner with respect to the gate edge after the gate stack has been produced. In the case of a memory technology, this is done, depending on the layout of the cell, for example by means of an appropriate photo mask on which the side of the device to be implanted is exposed. For example, for a MINT layout Stripe mask is used, in contrast to an LM block mask with a checkerboard layout.
Bei Logik-Transistoren wird im Gegensatz dazu die zusatzlicne Dotierung durch eine auf der Source-Seite geöffnete Maske eingebracht. In beiden Fallen vergrößert diese zusätzliche Dotierung die Potentialbaπerre und erhöht somit die Einsatzspannung im Kurzkanalbereich der Transistoren. Darüber hinaus ist bei Logik-Transistoren eine Ernohung des Device-Stromes durch den damit verbundenen "velocιty"-Overshoot verbunden.In the case of logic transistors, in contrast, the additional doping is introduced through a mask opened on the source side. In both cases, this additional doping increases the potential barriers and thus increases the threshold voltage in the short-channel region of the transistors. In addition, in the case of logic transistors, the device current is increased by the associated "velocity" overshoot.
Die Implantation der Dotierung wird nach der Atzung des Gate- Stapels direkt vor oder wahrend der sogenannten Seitenwand- Oxidation durchgeführt. Durch die anschließende Oxidation der Gate-Seitenwand diffundiert der Dotierstoff unter die Gate- Kante. Im Falle einer p-Dotierung mittels Bor beispielsweise verringert sich dadurch die Dotierungskonzentration nahe der freiliegenden Oberflache neben dem Gate bzw. m sogenannten Source/Dram-Gebiet durch Segregation (Aoreicherung ms ent- stehende Oxid) , wahrend die Konzentration an der Gate-Kante durch eine Oxygen-enhanced Diffusion zunimmt.The implantation of the doping is carried out after the etching of the gate stack directly before or during the so-called sidewall oxidation. Subsequent oxidation of the gate sidewall causes the dopant to diffuse under the gate edge. In the case of p-doping by means of boron, for example, the doping concentration near the exposed surface next to the gate or in the so-called source / dram region is reduced by segregation (Aoreicherung ms arising oxide), while the concentration at the gate edge by an oxygen-enhanced diffusion increases.
In der vorliegenden Erfindung wird das eingangs erwähnte Problem insbesondere dadurch gelost, dass Gate-Stapel auf ein Gate-Dielektrikum über einem Halbleitersubstrat aufgebracht werden, eine Dotierung selbstjustiert zu Kanten der Gate- Stapel implantiert werden, und ein Seitenwand-Oxid an freiliegenden Seltenwanden der Gate-Stapel unter gleichzeitiger Bildung unter die Gate-Kante diffundierter Dotierungsbereiche generiert wird.In the present invention, the above-mentioned problem is solved in particular by applying gate stacks to a gate dielectric over a semiconductor substrate, implanting self-aligned doping to edges of the gate stacks, and sidewall oxide on exposed rare walls of the gate Stack is generated with simultaneous formation under the gate edge of diffused doping regions.
In den Unteranspruchen finden sich vorteilhafte Weiterbildungen und Verbesserungen des jeweiligen Erfindungsgegenstandes.Advantageous further developments and improvements of the respective subject matter of the invention can be found in the subclaims.
Gemäß einer bevorzugten Weiterbildung werden die Gate-Stapel in etwa aquidistant zueinander aufgeoracht und unter jedem zweiten benachbarten Gate-Stapel ist im Halbleitersubstrat ein Speicherkondensator angeordnet.According to a preferred development, the gate stacks are placed approximately equidistant from one another and under each A storage capacitor is arranged in the semiconductor substrate in the second adjacent gate stack.
Gemäß einer weiteren bevorzugten Weiterbildung erfolgt die Implantation der Dotierung asymmetrisch aus einer vorbestimmten Richtung unter einem vorbestimmten Winkel.According to a further preferred development, the implantation of the doping takes place asymmetrically from a predetermined direction at a predetermined angle.
Gemäß einer weiteren bevorzugten Weiterbildung werden die Gate-Stapel in etwa äquidistant zueinander aufgebracht, wobei alternierend unter jedem dritten oder ersten benachbartenAccording to a further preferred development, the gate stacks are applied approximately equidistant from one another, alternating under every third or first adjacent one
Gate-Stapel im Halbleitersubstrat ein Speicherkondensator angeordnet ist.A storage capacitor is arranged in the gate stack in the semiconductor substrate.
Gemäß einer weiteren bevorzugten Weiterbildung wird zwischen jedem zweiten Gate-Stapelpaar eine Maske vor dem Implantieren der Dotierung vorgesehen.According to a further preferred development, a mask is provided between every second pair of gate stacks before the doping is implanted.
Gemäß einer weiteren bevorzugten Weiterbildung wird die Dotierung aus zwei vorbestimmten Richtungen jeweils unter einem vorbestimmten Winkel implantiert.According to a further preferred development, the doping is implanted from two predetermined directions in each case at a predetermined angle.
Gemäß einer weiteren bevorzugten Weiterbildung wird die Dotierung unter einem vorbestimmten Winkel von α = 0° implantiert .According to a further preferred development, the doping is implanted at a predetermined angle of α = 0 °.
Gemäß einer weiteren bevorzugten Weiterbildung wird die Dotierung nach der Implantation durch einen vorbestimmt eingestellten Extra-Temperschritt diffundiert.According to a further preferred development, the doping after the implantation is diffused through a predetermined, extra tempering step.
Gemäß einer weiteren bevorzugten Weiterbildung wird die Sei- tenwand-Oxidation auf zwei oder mehrere Teilschritte aufgeteilt, wobei die Dotierungsimplantation zwischen Teilschritten erfolgt.According to a further preferred development, the sidewall oxidation is divided into two or more sub-steps, with the doping implantation taking place between sub-steps.
Gemäß einer weiteren bevorzugten Weiterbildung wird die Dotierung jeweils auf nur einer Seite der Gate-Stapel implantiert . Gemäß einer weiteren bevorzugten Weiterbildung vird das Verfahren zur Herstellung von Logik-Transistoren bzw. Logik- schaltkreisen, msoesondere für DRAMs, eingesetzt.According to a further preferred development, the doping is implanted on only one side of the gate stack. According to a further preferred development, the method is used to manufacture logic transistors or logic circuits, especially for DRAMs.
Gemäß einer weiteren bevorzugten Weiterbildung wird das Verfahren zur Herstellung von Auswahl-Transistoren eingesetzt. Diese Auswahl-Transistoren sind vorzugsweise durch STI (Shal- low Trench Isolation) -Graben voneinander gertrennt.According to a further preferred development, the method is used to manufacture selection transistors. These selection transistors are preferably separated from one another by STI (Shalow Trench Isolation) trenches.
Gemäß einer weiteren bevorzugten Weiterbildung werden die Gate-Stapel mit einer Lange von unter 100 nm hergestellt.According to a further preferred development, the gate stacks are produced with a length of less than 100 nm.
Gemäß einer weiteren bevorzugten Weiterbildung werden die Gate-Stapel parallel, streifenformig auf dem Halbleitersubstrat vorgesehen.According to a further preferred development, the gate stacks are provided in parallel in the form of strips on the semiconductor substrate.
Gemäß einer weiteren bevorzugten Weiterbildung weisen die Gate-Stapel e ne untere erste Schicht aus einem Polysilizium und eine daruberliegende zweite Schicht aus einem Metall- Silizid oder einem Metall auf.According to a further preferred development, the gate stacks have a lower first layer made of a polysilicon and an overlying second layer made of a metal silicide or a metal.
Gemäß einer weiteren bevorzugten Weiterbildung wird zum Erstellen der Gate-Stapel ein Aufbringen und Strukturieren der ersten, der daruberliegenden zweiten und einer darauf angeordneten dritten Schicht auf dem Gate-Dielektrikum durchgeführt.According to a further preferred development, in order to create the gate stacks, the first, the second layer lying thereon and a third layer arranged thereon are applied and structured on the gate dielectric.
Gemäß einer weiteren bevorzugten Weiterbildung weist die dritte Schicht Siliziumnitπd bzw. -oxid auf.According to a further preferred development, the third layer has silicon nitride or oxide.
Gemäß einer weiteren bevorzugten Weiterbildung werden an den Seltenwanden der Gate-Stapel Seitenwand-Spacer vorzugsweise aus Siliziummtrid bzw. -oxid vorgesehen. Ausfuhrungsbeispiele der Erfindung sind in den Zeichnungen dargestellt und m der nachfolgenden Beschreibung naher erläutert .According to a further preferred development, sidewall spacers are preferably provided on the rare sides of the gate stack, preferably made of silicon oxide or oxide. Exemplary embodiments of the invention are shown in the drawings and are explained in more detail in the description below.
Es zeigen:Show it:
Fig. 1 bis 4 schematische Darstellungen aufeinanderfolgender Stadien im Herstellungsverfanren zur Erläuterung einer ersten Ausfuhrungsform der vorliegenden Erfindung; und1 to 4 are schematic representations of successive stages in the manufacturing process to explain a first embodiment of the present invention; and
Fig. 5 bis 8 schematische Darstellungen aufeinanderfolgender Stadien im Herstellungsverfahren zur Erläuterung einer zweiten Ausfuhrungsform der vorliegenden Erfindung.5 to 8 are schematic representations of successive stages in the manufacturing process to explain a second embodiment of the present invention.
In den Figuren bezeichnen gleiche Bezugszeichen gleiche oder funktionsgleiche Bestandteile.In the figures, identical reference symbols designate identical or functionally identical components.
In Fig. 1 ist eine Halbleiterstruktur nach vorausgehenden elementaren Schritten im Herstellungsprozess dargestellt. In einem Halbleitersubstrat 1 sind Speicherkondensatoren TK1, TK2, TK3 und TK4 vertikal zur Oberflache des Halbleitersub- strats 1 angeordnet, über dem Halbleitersubstrat 1 ist ein Dielektrikum 5 aufgebracht, welches zur Passivierung des1 shows a semiconductor structure after preceding elementary steps in the manufacturing process. Storage capacitors TK1, TK2, TK3 and TK4 are arranged vertically to the surface of the semiconductor substrate 1 in a semiconductor substrate 1. A dielectric 5 is applied over the semiconductor substrate 1, which dielectric is used to passivate the
Halbleitersubstrats 1 dient. Auf dem Gate-Dielektrikum 5 ist in etwa aquidistant eine Vielzahl von Gate-Stapeln GSl bis GS8 aufgebracht, wobei jeder Gate-Stapel vorzugsweise in drei gleichartig strukturierten Schichten 10, 20 und 30 vorgesehen ist. Die erste Gate-Stapelschicht 10, welche sicn direkt an das Gate-Dielektrikum 5 anschließt, weist vorzugsweise Poly- silizium auf. Darüber schließt sich eine zweite Gate-Stapel- schicht 20 an, die insbesondere aus einem Metall-Siliziα besteht, und auf welche e_ne dritte Gate-Stapelschicht 30 folgt, die vorzugsweise Siliziumnitrid aufweist. Die Gate- Stapel GSl bis GS8 erstrecken sich in Zeichenebene vorzugsweise parallel und streifenformig und weisen im wesentlichen dieselben Abmessungen auf. ST bezeichnet in Fig. 1 STI (Shal- low Trench Isolation) -Gräben, welche die Zellen voneinander trennen. Aus Gründen der Übersichtlichkeit werden diese STI (Shallow Trench Isolation) -Gräben im folgenden nicht weiter erwähnt bzw. sind nicht in den weiteren Zeichnungen dargestellt.Semiconductor substrate 1 is used. A plurality of gate stacks GS1 to GS8 are applied approximately equidistantly to the gate dielectric 5, each gate stack preferably being provided in three layers 10, 20 and 30 of the same structure. The first gate stack layer 10, which directly adjoins the gate dielectric 5, preferably has polysilicon. This is followed by a second gate stack layer 20, which consists in particular of a metal silicon, and which is followed by a third gate stack layer 30, which preferably has silicon nitride. The gate stacks GS1 to GS8 preferably extend parallel and in strip form in the plane of the drawing and essentially have the same dimensions. In FIG. 1, ST denotes STI (shallow trench isolation) trenches which separate the cells from one another. For reasons of clarity, these STI (shallow trench isolation) trenches are not mentioned further below or are not shown in the further drawings.
Gemäß der ersten vorliegenden Ausführungsform sind die Speicherkondensatoren TK1, TK2, TK3 und TK4 derart angeordnet, dass alternierend jeweils jeder dritte oder erste Gate-Stapel GSl, GS4, GS5 und GS8 über einem Kondensator TKl, TK2, TK3, TK4 zu liegen kommen.According to the first present embodiment, the storage capacitors TK1, TK2, TK3 and TK4 are arranged such that alternately every third or first gate stack GS1, GS4, GS5 and GS8 come to lie above a capacitor TK1, TK2, TK3, TK4.
In Fig. 2 ist die Halbleiterstruktur gemäß Fig. 1 in einem nachfolgenden Stadium des Herstellungsprozesses dargestellt. Zwischen jedem zweiten lateral benachbarten Gate-Stapelpaar GSl, GS2; GS3, GS4; GS5, GSβ; GS7, GS8 ist eine, vorzugsweise photolithographisch strukturierte, Maske M vorgesehen, wobei ein Maskenabschnitt M zwischen zwei Gate-Stapeln, z.B. GSl und GS2, angeordnet ist und einer der Gate-Stapel GSl über einem Kondensator TKl liegt, wohingegen der lateral benachbarte Gate-Stapel GS2 nicht über einem Speicherkondensator angeordnet ist. Ein solcher Maskenabschnitt M erstreckt sich vorzugsweise in vertikaler Richtung über die Gate-Stapel, z.B. GSl, GS2, hinaus und ist in der Breite derart strukturiert, dass ein aus einer vorbestimmten Richtung II, 12 eingesetzter Implantationsstrahl zur Dotierung des Halbleitersubstrats 1 in den von der Maske unbedeckten Bereichen durch die Maske bzw. die Maskenabschnitte M nicht beeinträchtigt wird.FIG. 2 shows the semiconductor structure according to FIG. 1 in a subsequent stage of the manufacturing process. Between every second laterally adjacent gate stack pair GS1, GS2; GS3, GS4; GS5, GSβ; GS7, GS8, a, preferably photolithographically structured, mask M is provided, with a mask section M between two gate stacks, e.g. GSl and GS2, and one of the gate stacks GSl is located above a capacitor TKl, whereas the laterally adjacent gate stack GS2 is not located above a storage capacitor. Such a mask section M preferably extends in the vertical direction over the gate stacks, e.g. GSl, GS2, and is structured in width in such a way that an implantation beam used from a predetermined direction II, 12 for doping the semiconductor substrate 1 in the areas not covered by the mask is not impaired by the mask or the mask sections M.
Gemäß der ersten Ausführungsform der vorliegenden Erfindung wird in von den Maskenabschnitten M nicht bedeckten Bereichen ein Dotierstoff in das Halbleitersubstrat 1 implantiert, wo- bei die Implantation aus einer bzw. zwei vorbestimmten Richtungen II, 12 erfolgt und sich dementsprechend Dotierungen 100, 110, 105, 120, 130 vorzugsweise selbstjustiert zur Gate- Kante im Halbleitersubstrat 1 bilden.According to the first embodiment of the present invention, a dopant is implanted in the semiconductor substrate 1 in areas not covered by the mask sections M, the implantation taking place from one or two predetermined directions II, 12 and doping accordingly 100, 110, 105, 120, 130 preferably self-aligned to the gate edge in the semiconductor substrate 1.
Die Implantationsπchtungen II, 12 bilden mit der Vertikalen einen Winkel bzw. -α, welcher zwischen 0°, d.h. II = 12, und ce Winkel zwischen der Vertikalen und einer Geraden, welche sich vom unteren Übergang zwischen Gate-Dielektrikum 5 und Gate-Stapel, z.B. GS3, unter Beruhren der oberen seitlichen Außenkante eines lateral benachbarten Gate-Stapels, z.B. GS2, erstreckt. Ein Dotierstoff im Falle eines n-Kanal-Tran- sistors ist beispielsweise Bor, welches gemäß der ersten Ausfuhrungsform unter Einsatz einer Streifenmaske mit dem Maskenabschnitten M in das Halbleitersubstrat 1 eingebracht wird. Eine Dotierung 100, 110, 105, 120 und 130 wird jeweils nur an einer Seite bzw. Gate-Kante eines entsprechenden Gate- Stapels GS2, GS3, GS4, GS5, GSβ, GS7 vorgesehen, welches zu einem asymmetrischen Design fuhrt. Die Gebiete 105 liegen in den STI-Graben und haben keine elektrische Funktion bzw. können durch geeignete Maskierung auch weggelassen werden.The implantation devices II, 12 form an angle or -α with the vertical, which is between 0 °, i.e. II = 12, and ce angle between the vertical and a straight line, which extends from the lower transition between gate dielectric 5 and gate stack, e.g. GS3, while touching the upper lateral outer edge of a laterally adjacent gate stack, e.g. GS2, extends. A dopant in the case of an n-channel transistor is, for example, boron, which according to the first embodiment is introduced into the semiconductor substrate 1 with the mask sections M using a stripe mask. A doping 100, 110, 105, 120 and 130 is only provided on one side or gate edge of a corresponding gate stack GS2, GS3, GS4, GS5, GSβ, GS7, which leads to an asymmetrical design. The regions 105 lie in the STI trench and have no electrical function or can also be omitted by suitable masking.
Fig. 3 zeigt die Halbleiterstruktur gemäß Fig. 2 nach weiteren Verfahrensschritten gemäß der ersten Ausfuhrungsform der vorliegenden Erfindung. Nach einem Strip der Maskenabschnitte M, d.h. der Streifenmaske bei einem MINT-Layout, wird über den oxidierbaren Seltenwanden der zwei unteren Gate-Stapel- schichten 10, 20 eine Seitenwand-Oxidation durchgeführt, wodurch eine Seitenwand-Oxidationsschicht 40 gebildet wird. Wahrend der thermisch durchgeführten Seitenwand-Oxidation andern sich die Dotierstoffproflle der Dotierungen 100', 110', 120', 130' im Halbleitersubstrat 1 insbesondere im Source- Junction-Bereicn .FIG. 3 shows the semiconductor structure according to FIG. 2 after further method steps according to the first embodiment of the present invention. After a strip of the mask sections M, i.e. of the stripe mask in a MINT layout, a sidewall oxidation is carried out over the oxidizable rare walls of the two lower gate stack layers 10, 20, whereby a sidewall oxidation layer 40 is formed. During the thermally carried out sidewall oxidation, the dopant profiles of the dopings 100 ', 110', 120 ', 130' change in the semiconductor substrate 1, in particular in the source junction area.
Darüber hinaus besteht die Möglichkeit für die Verteilung der Dotierstoffe im Halbleitersubstrat 1, einen gezielt einge- stellten Extra-Temperschritt einzusetzen oder die Seitenwand- Oxidation auf zwei oder mehrere Teilschritte aufzuteilen, wobei die Implantation der Dotierung, wie mit Bezug auf Fig. 2 dargestellt, zwischen einzelnen Teilschritten ausgeführt wird. Auf diese Weise lasst sich die raumliche Verteilung der Dotierstoffe 100', 110', 120', 130' optimieren. Die Seitenwand-Oxidation wird somit zur Erzeugung vorbestimmter geeig- neter Dotierstoffprofile ausgenutzt, welche auch durch eine mehrstufige Abfolge von Anneals und/oder Oxidationen generierbar sind. Die im Zuge der Seitenwand-Oxidation in ihrem Konzentrationsprofil veränderten Dotierungen 100', 110', 120' und 130' erstrecken sich demgemass durch Diffusion unter die Gate-Kante der entsprechenden Gate-Stapel GS2, GS3, GSβ und GS7.In addition, there is the possibility for the distribution of the dopants in the semiconductor substrate 1 to use a specifically set extra tempering step or to divide the sidewall oxidation into two or more sub-steps, the implantation of the doping, as with reference to FIG. 2 shown, is executed between individual substeps. In this way, the spatial distribution of the dopants 100 ', 110', 120 ', 130' can be optimized. The sidewall oxidation is thus used to generate predetermined suitable dopant profiles, which can also be generated by a multi-stage sequence of anneals and / or oxidations. The dopings 100 ', 110', 120 'and 130' which have changed their concentration profile in the course of the sidewall oxidation accordingly extend by diffusion under the gate edge of the corresponding gate stacks GS2, GS3, GSβ and GS7.
Durch geschicktes Ausnutzen der Segregation (Abreicherung der Dotierung ins entstehende Oxid) in das auf den Übergangs- bzw. Junction-Gebieten aufwachsende Oxid und der Diffusion unter die Gate-Kante kann die Potentialbarierre auf der Source-Seite des Devices beeinflußt, d.h. designed, werden, und die Junction-Felder (E-Felder) auf der Drain-Seite werden stark reduziert. Darüber hinaus kann beispielsweise bei der Verwendung von Bor in einem n-FET-Device ein niedrigerThe potential barrier on the source side of the device can be influenced, i.e. using the segregation (depletion of the doping into the resulting oxide) in the oxide growing on the transition or junction regions and diffusion under the gate edge. are designed, and the junction fields (E fields) on the drain side are greatly reduced. In addition, for example, when using boron in an n-FET device, a lower one
Junction-Serienwiderstand generiert werden, ohne dass die erwünschte Erhöhung der Potentialbarierre darunter leidet.Junction series resistance can be generated without the desired increase in the potential barrier suffering.
In Fig. 4 ist eine Halbleiterstruktur gemäß Fig. 3 nach im Herstellungsprozeß nachfolgenden Schritten dargestellt, wobei ein Seitenwand-Spacer 50, z.B. aus Siliziumnitrid, über den Seitenwänden der Gate-Stapel GSl bis GΞ8 bzw. über den Seitenwand-Oxidschichten 40 aufgebracht sind. Darüber hinaus wurden aktive Halbleiterbereiche 60, 61, 62, 63, 64 und 65 zwischen den entsprechenden Gate-Stapeln GSl bis GS8 ausgebildet. Weiter fuhrende Herstellungsschritte wie Entfernen des Gate-Dielektrikums und ein nachfolgendes Vorsehen einer Kontaktierungseinπchtung (jeweils nicht dargestellt) sei nur ergänzend erwähnt.Fig. 4 shows a semiconductor structure according to Fig. 3 after steps following in the manufacturing process, a side wall spacer 50, e.g. made of silicon nitride, are applied over the side walls of the gate stacks GS1 to GΞ8 or over the side wall oxide layers 40. In addition, active semiconductor regions 60, 61, 62, 63, 64 and 65 were formed between the corresponding gate stacks GS1 to GS8. Further manufacturing steps such as removing the gate dielectric and subsequent provision of a contacting device (not shown in each case) should only be mentioned in addition.
Eine derart hergestellte Halbleiterstruktur mit asymmetrischer Dotierung, welche direkt vor, direkt nach und/oder wah- rend der Seitenwand-Oxidation durch Diffusion in ihrem Konzentrationsprofil angepasst wird, verbessert das Kurzkanal- Verhalten des Transistors und reduziert zugleich die elektrischen Felder auf der Drain-Seite des Devices. Die Drain-Seite ist im Falle einer Speicherzelle, bei der eine logische "1" als Information gespeichert ist, die Knoten- bzw. Node-Seite mit dem Speicherkondensator, während sie im Fall einer Logik- Anwendung die Seite des Devices mit dem höheren Potential charakterisiert. Prinzipiell kann dieses Verfahren sowohl für n- als auch für p-FET-Strukturen bzw. Devices unter der Verwendung entsprechender Species bzw. Substrat Dotierstoff- Kombinationen eingesetzt werden, wobei die Diffusion unter das Gate und die Segregation in das auf dem Source/Drain- Gebiet aufwachsende Oxid stark von dem verwendeten Dotier- stoff abhängt.A semiconductor structure produced in this way with asymmetrical doping, which is immediately before, immediately after and / or Adjusting the concentration profile of the sidewall oxidation by diffusion improves the short-channel behavior of the transistor and at the same time reduces the electrical fields on the drain side of the device. In the case of a memory cell in which a logic “1” is stored as information, the drain side is the node or node side with the storage capacitor, while in the case of a logic application it is the side of the device with the higher potential characterized. In principle, this method can be used both for n- and for p-FET structures or devices using appropriate species or substrate dopant combinations, the diffusion under the gate and the segregation in the on the source / drain Oxide growing region depends heavily on the dopant used.
Fig. 5 zeigt eine Halbleiterstruktur, welche sich im wesentlichen von der Halbleiterstruktur gemäß Fig. 1 darin unterscheidet, dass die Speicherkondensatoren TKl1, TK2 ' , TK3 ' und TK4 ' , welche vertikal im Halbleitersubstrat 1 angeordnet sind, unter jedem zweiten, lateral benachbarten Gate-Stapel GSl, GS3, GS5 und GS7 vorgesehen sind. Dies entspricht einem Checkerboard-Layout. Auch bei diesem Layout können streifen- förmige STI-Gräben vorgesehen werden, sind allerdings in die- sem Schnitt nicht sichtbar.FIG. 5 shows a semiconductor structure which differs essentially from the semiconductor structure according to FIG. 1 in that the storage capacitors TKl 1 , TK2 ', TK3' and TK4 ', which are arranged vertically in the semiconductor substrate 1, under every second, laterally adjacent Gate stacks GS1, GS3, GS5 and GS7 are provided. This corresponds to a checkerboard layout. Strip-shaped STI trenches can also be provided with this layout, but are not visible in this section.
In Fig. 6 ist die Halbleiterstruktur gemäß Fig. 5 dargestellt, wobei an den rechten Kanten der Gate-Stapel GSl bis GS8 ohne Einsatz einer Maske Dotierungen 105'*, 110'', 120'', 130'' und 140'' mittels einer gewinkelten Implantation II' in dem Halbleitersubstrat 1 vorgesehen sind. Für den vorbestimmten Implantationswinkel α gilt das mit Bezug auf Fig. 2 Erläuterte, wobei gemäß dieser zweiten Ausführungsform der vorliegenden Erfindung nur aus einer Richtung II' implantiert wird, und zwar bei jedem benachbarten Gate-Stapel GSl bis GS8 auf der gleichen Seite im Bereich des Übergangs zwischen dem Gate-Dielektrikum 5 und der ersten Gate-Stapelschicht 10 im Halbleitersubstrat. Grundsätzlich kann die Implantation ebenfalls aus der entsprechend anderen Richtung (nicht dargestellt) erfolgen, wobei ein negativer Winkel α auftritt und der andere Kantenbereich eines jeden Gate-Stapels GSl bis GS8 am Übergang zwischen dem Gate-Dielektrikum 5 unα der ersten Gate-Stapelschicht 10 im Halbleitersubstrat 1 m_t einer entsprechenden Dotierung versehen wird.FIG. 6 shows the semiconductor structure according to FIG. 5, with doping 105 ′ *, 110 ″, 120 ″, 130 ″ and 140 ″ on the right edges of the gate stacks GS1 to GS8 without using a mask an angled implantation II 'are provided in the semiconductor substrate 1. The explanation given with reference to FIG. 2 applies to the predetermined implantation angle .alpha., According to this second embodiment of the present invention, implantation is carried out only from one direction II ', namely for each adjacent gate stack GS1 to GS8 on the same side in the region of the Transition between the gate dielectric 5 and the first gate stack layer 10 in Semiconductor substrate. In principle, the implantation can also be carried out from the corresponding other direction (not shown), a negative angle α occurring and the other edge region of each gate stack GS1 to GS8 at the transition between the gate dielectric 5 and the first gate stack layer 10 in Semiconductor substrate 1 m_t is provided with a corresponding doping.
In Fig. 7 ist eine Anordnung gemäß Fig. 6 nach im Herstel- lungsverfahren nachfolgenden Prozeßschritten dargestellt. Wie mit Bezug auf Fig. 3 beschrieben, wird über den oxidierbaren Seltenwanden der Gate-Stapel GSl bis GS8 eine Seitenwand- Oxidierung 40 generiert, währenddessen die Dotierung an den Gate-Kanten 110''', 120''', 130''*, 140''' der Gate-Stapel GS2, GS4, GS6 und GS8, welche nicht über einem Speicherkondensator angeordnet sind, unter die entsprechende Gate-Kante diffundiert. Auch hier ist, wie mit Bezug auf Fig. 3 beschrieben, zur Verteilung der Dotierung in dem Halbleitersubstrat 1 ein gezielt eingestellter Extra-Temperschritt vorseh- bar oder die Seitenwand-Oxidation auf zwei oder mehrere Teilschritte aufteilbar und die Implantation des Dotierungsstoffes, welche mit Bezug auf Fig. 6 erläutert wurde, dazwischen ausfuhrbar, um eine optimierte raumliche Dotierungskonzentra- tionsverteilung zu generieren.FIG. 7 shows an arrangement according to FIG. 6 after process steps following in the manufacturing process. As described with reference to FIG. 3, a sidewall oxidation 40 is generated over the oxidizable rare walls of the gate stacks GS1 to GS8, during which the doping at the gate edges 110 '' ', 120' '', 130 '' * , 140 '' 'of the gate stacks GS2, GS4, GS6 and GS8, which are not arranged above a storage capacitor, diffuses under the corresponding gate edge. Here, too, as described with reference to FIG. 3, for the distribution of the doping in the semiconductor substrate 1, a specifically set extra tempering step can be provided or the sidewall oxidation can be divided into two or more sub-steps and the implantation of the doping substance, which with reference was explained in FIG. 6, executable in between, in order to generate an optimized spatial doping concentration distribution.
In Fig. 8 ist eine Struktur gemäß Fig. 7 dargestellt, wobei über den Seltenwanden bzw. dem Seitenwand-Oxid 40 der Gate- Stapel GSl bis GS8 ein Seitenwand-Spacer 50 aufgebracht ist, welcher vorzugsweise aus Siliziumnitnd besteht. Außerdem sind aktive Halbleiterbereiche 60', 61', 62', 63', 64', 65', 66' und 67' vorgesehen, welche nach einer nachfolgenden Entfernung des Gate-Dielektrikums 5 in vom ummantelten Gate- Stack 10, 20, 30, 40 und 50 unbedeckten Bereichen zwischen den einzelnen Gate-Stapeln GSl bis GS8 zur Anbmdung an eine elektrische Kontakteinrichtung (nicht dargestellt) dienen. Obwohl die vorliegende Erfindung vorstehend anhand zweier bevorzugter Ausfuhrungsbeispiele beschrieben wurde, ist sie darauf nicht beschrankt, sondern auf vielfaltige Art und Weise modifizierbar.FIG. 8 shows a structure in accordance with FIG. 7, a side wall spacer 50, which preferably being made of silicon, being applied over the rare walls or the side wall oxide 40 of the gate stacks GS1 to GS8. In addition, active semiconductor regions 60 ', 61', 62 ', 63', 64 ', 65', 66 'and 67' are provided, which after a subsequent removal of the gate dielectric 5 in from the encased gate stack 10, 20, 30 , 40 and 50 uncovered areas between the individual gate stacks GS1 to GS8 are used for connection to an electrical contact device (not shown). Although the present invention has been described above with reference to two preferred exemplary embodiments, it is not restricted to this but can be modified in a variety of ways.
Insbesondere sind die Schichtmaterialien für die Gate-Stapel, deren Anordnung und der genannte Dotierstoff nur beispielhaft. Darüber hinaus ist die vorliegende Erfindung sowie die ihr zugrunde liegende Aufgabe prinzipiell auf beliebige in- tegrierte Schaltungen anwendbar, obwohl sie mit Bezug auf integrierte DRAM-Speicher bzw. Logik-Schaltungen in Silizium- Technologie erläutert wurden. Ebenfalls sind auf Basis des erfindungsgemaßen Herstellungsverfahrens für eine Halbleiterstruktur sowohl n- als auch p-Kanal-Feldeffekt-Transistorεn bzw. -Devices realisierbar. In particular, the layer materials for the gate stacks, their arrangement and the dopant mentioned are only examples. In addition, the present invention and the object on which it is based can in principle be applied to any integrated circuits, although they have been explained with reference to integrated DRAM memories or logic circuits in silicon technology. Likewise, on the basis of the production method according to the invention for a semiconductor structure, both n- and p-channel field-effect transistors or devices can be implemented.
BezugszeichenlisteLIST OF REFERENCE NUMBERS
1 Halbleitersubstrat 5 Dielektrikum1 semiconductor substrate 5 dielectric
10 Gate-Stapelschicht, vorzugsweise aus Poly- silizium 20 Gate-Stapelschicht, vorzugswseise aus Metall- silizid 30 Gate-Stapelschicht, vorzugswseise aus Siliziumnitrid 40 Seitenwand-Oxid10 stacked gate layer, preferably made of polysilicon 20 stacked gate layer, preferably made of metal silicide 30 stacked gate layer, preferably made of silicon nitride 40 sidewall oxide
50 Seitenwand-Spacer, z.B. aus Siliziumnitrid50 sidewall spacers, e.g. made of silicon nitride
60 - 65 aktive Gebiete 60' - 67' aktive Gebiete60 - 65 active areas 60 '- 67' active areas
100, 105, 110, 120, 130 implantierte Dotierung (2-stg. 100', 110', 120', 130' diffundierte, impl . Dotierung100, 105, 110, 120, 130 implanted doping (2-part 100 ', 110', 120 ', 130' diffused, impl. Doping
105*', 110'', 120'', 130'', 140'* implant . Dot. (einseitig) 110'*', 120''', 130''', 140'*' diffundierte, impl. Dot105 * ', 110' ', 120' ', 130' ', 140' * implant. Dot. (one-sided) 110 '*', 120 '' ', 130' '', 140 '*' diffused, impl. dot
GSl - GS8 Gatestapel M MaskeGSl - GS8 gate stack M mask
11 Implantationsrichtung α11 implantation direction α
12 Implantationsrichtung -α II' Implantationsrichtung α α Implantationswinkel zur Vertikalen 12 Implantation direction -α II 'implantation direction α α implantation angle to the vertical

Claims

Patentansprüche claims
1. Verfahren zur Herstellung einer Halbleiterstruktur mit mehreren Gate-Stapeln (GSl - GS8) auf einem Halbleitersubstrat (1) mit den folgenden Schritten:1. A method for producing a semiconductor structure with a plurality of gate stacks (GS1-GS8) on a semiconductor substrate (1) with the following steps:
Aufbringen der Gate-Stapel (GSl - GS8) auf ein Gate-Die- lektrikum (5) über dem Halbleitersubstrat (1);Applying the gate stacks (GS1-GS8) to a gate dielectric (5) above the semiconductor substrate (1);
Implantieren einer Kanaldotierung (100, 105, 110, 120, 130; 105'', 110'', 120'*, 130'*, 140'*) selbstjustiert zu Kanten der Gate-Stapel (GSl - GS8); undImplanting a channel doping (100, 105, 110, 120, 130; 105 '', 110 '', 120 '*, 130' *, 140 '*) self-aligned to edges of the gate stack (GS1 - GS8); and
Bilden eines Seitenwand-Oxids (40) an freiliegenden Sei- tenwanden der Gate-Stapel (GSl - GS8) unter gleichzeitiger Bildung diffundierter Kanaldotierungsbereiche (100*, 110', 120', 130'; 110''', 120''', 130''', 140'*') unter der Gate-Kante.Forming a sidewall oxide (40) on exposed sidewalls of the gate stacks (GS1 - GS8) while simultaneously forming diffused channel doping regions (100 *, 110 ', 120', 130 '; 110' '', 120 '' ', 130 '' ', 140' * ') under the gate edge.
2. Verfahren nach Anspruch 1, d a d u r c h g e k e n n z e i c h n e t, dass die Gate-Stapel (GSl - GS8) in etwa aquidistant zu- einander aufgebracht werden, wobei unter jedem zweiten benachbarten Gate-Stapel (GSl, GS3, GS5, GS7) im Halbleitersubstrat (1) ein Speicherkondensator (TKl*, TK2 ' , TK3', TK4 * ) angeordnet ist.2. The method according to claim 1, characterized in that the gate stacks (GSl - GS8) are applied approximately aquidistantly to one another, with under every second adjacent gate stack (GSl, GS3, GS5, GS7) in the semiconductor substrate (1) a storage capacitor (TK1 *, TK2 ', TK3', TK4 *) is arranged.
3. Verfahren nach Anspruch 2, d a d u r c h g e k e n n z e i c h n e t, dass die Implantation der Kanaldotierung (105'', 110'', 120'*, 130'', 140*') asymmetrisch aus einer vorbestimmten Richtung (II*) unter einem vorbestimmten Winkel (α) erfolgt. 3. The method according to claim 2, characterized in that the implantation of the channel doping (105 '', 110 '', 120 '*, 130'', 140 *') asymmetrically from a predetermined direction (II *) at a predetermined angle (α ) he follows.
4. Verfahren nach Anspruch 1, d a d u r c h g e k e n n z e i c h n e t, dass die Gate-Stapel (GSl - GS8) in etwa äquidistant zu- einander aufgebracht werden, wobei alternierend unter jedem dritten oder ersten benachbarten Gate-Stapel (GSl, GS4, GS5, GS8) im Halbleitersubstrat (1) ein Speicherkondensator (TKl, TK2, TK3, TK4) angeordnet ist.4. The method according to claim 1, characterized in that the gate stacks (GSl - GS8) are applied approximately equidistant from one another, alternating under every third or first adjacent gate stack (GSl, GS4, GS5, GS8) in the semiconductor substrate (1) a storage capacitor (TKl, TK2, TK3, TK4) is arranged.
5. Verfahren nach Anspruch 4, d a d u r c h g e k e'n n z e i c h n e t, dass zwischen jedem zweiten Gate-Stapelpaar (GSl, GS2; GS3, GS4; GS5, GS6; GS7, GS8) eine Maske (M) vor dem Implantieren der Kanaldotierung (100, 105, 110, 120, 130) vorgesehen wird.5. The method according to claim 4, characterized in that between every second pair of gate stacks (GS1, GS2; GS3, GS4; GS5, GS6; GS7, GS8) a mask (M) before implanting the channel doping (100, 105, 110, 120, 130) is provided.
6. Verfahren nach Anspruch 5, d a d u r c h g e k e n n z e i c h n e t, dass die Kanaldotierung (100, 105, 110, 120, 130) aus zwei vorbestimmten Richtungen (II, 12) jeweils unter einem vorbestimmten Winkel (α, -α) implantiert wird.6. The method according to claim 5, so that the channel doping (100, 105, 110, 120, 130) is implanted from two predetermined directions (II, 12) each at a predetermined angle (α, -α).
7. Verfahren nach Anspruch 5, d a d u r c h g e k e n n z e i c h n e t, dass die Kanaldotierung (100, 105, 110, 120, 130) unter einem vorbestimmten Winkel (α) α = 0° implantiert wird.7. The method according to claim 5, so that the channel doping (100, 105, 110, 120, 130) is implanted at a predetermined angle (α) α = 0 °.
8. Verfahren nach einem der vorangehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e t, dass die Kanaldotierung nach der Implantation durch einen vorbestimmt eingestellten Extra-Temperschritt diffundiert wird.8. The method according to any one of the preceding claims, that the channel doping after the implantation is diffused by a predetermined, extra tempering step.
9. Verfahren nach einem der vorangehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e t, dass die Seitenwand-Oxidation auf zwei oder mehrere Teilschritte aufgeteilt wird, wobei die Kanaldotierungs- lmplantation zwischen Teilschritten erfolgt.9. The method according to any one of the preceding claims, characterized in that the sidewall oxidation is divided into two or more substeps, the channel doping implantation taking place between substeps.
10. Verfahren nach einem der vorangehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e t, dass die Kanaldotierung (100, 105, 110, 120, 130; 105'', 110'', 120'', 130'', 140' ') jeweils auf nur einer Seite der Gate-Stapel (GSl - GS8) implantiert wird.10. The method according to any one of the preceding claims, characterized in that the channel doping (100, 105, 110, 120, 130; 105 ", 110", 120 ", 130", 140 ") each on only one side the gate stack (GS1 - GS8) is implanted.
11. Verfahren nach einem der vorangehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e t, dass das Verfahren zur Herstellung von Logik- Transistoren eingesetzt wird.11. The method according to any one of the preceding claims, d a d u r c h g e k e n n z e i c h n e t that the method is used for the production of logic transistors.
12. Verfahren nach einem der vorangehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e t, dass das Verfahren zur Herstellung von Auswahl- Transistoren, vorzugsweise von einem DRAM, eingesetzt wird.12. The method according to any one of the preceding claims, that the method is used to produce selection transistors, preferably from a DRAM.
13. Verfahren nach einem der vorangehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e t, dass die Gate-Stapel (GSl - GS8) mit einer Lange von un- ter 100 nm hergestellt werden.13. The method according to any one of the preceding claims, that the gate stacks (GSl - GS8) are produced with a length of less than 100 nm.
14. Verfahren nach einem der vorangehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e t, dass die Gate-Stapel (GSl - GS8) parallel, streifenfor- mig auf dem Halbleitersubstrat (1) vorgesehen werden.14. The method as claimed in one of the preceding claims, that the gate stacks (GS1 - GS8) are provided in parallel in the form of a strip on the semiconductor substrate (1).
15. Verfahren nach einem der vorangehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e t, dass die Gate-Stapel (GSl - GS8) eine untere erste Schicht (10) aus Polysilizium und eine daruberliegende zweite Schicht (20) aus einem Metall-Silizid oder einem Metall aufweisen.15. The method according to any one of the preceding claims, characterized in that the gate stack (GSl - GS8) a lower first layer (10) made of polysilicon and an overlying have second layer (20) of a metal silicide or a metal.
16. Verfahren nach einem der vorangehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e t, dass zum Erstellen der Gate-Stapel (GSl - GS8) ein Aufbringen und Strukturieren der ersten, der daruberliegenden zweiten und einer darauf angeordneten dritten Schicht (10, 20, 30) auf dem Gate-Dielektrikum (5) durchgeführt wird.16. The method according to any one of the preceding claims, characterized in that for creating the gate stack (GSl - GS8) an application and structuring of the first, the overlying second and a third layer arranged thereon (10, 20, 30) on the gate Dielectric (5) is carried out.
17. Verfahren nach einem der vorangehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e t, dass die dritte Schicht (30) Siliziumnitrid oder -oxid aufweist.17. The method according to any one of the preceding claims, that the third layer (30) comprises silicon nitride or oxide.
18. Verfahren nach einem der vorangehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e t, dass an den Seitenwanden der Gate-Stapel (GSl - GS8) Seitenwand-Spacer (50), vorzugsweise aus Siliziumnitrid oder -oxid, vorgesehen werden.18. The method according to any one of the preceding claims, so that side wall spacers (50), preferably made of silicon nitride or oxide, are provided on the side walls of the gate stack (GS1 - GS8).
19. Halbleiterstruktur mit:19. Semiconductor structure with:
mehreren Gate-Stapeln (GSl - GS8) auf einem mit einemmultiple gate stacks (GSl - GS8) on one with one
Gate-Dilektrikum (5) versehenen Halbleitersubstrat (1) ;Gate dielectric (5) provided semiconductor substrate (1);
einer Oxidschicht (40) auf den Seitenwanden der Gate- Stapel (GSl - GS8); und mitan oxide layer (40) on the side walls of the gate stacks (GS1 - GS8); and with
implantierten, diffundierten Kanaldotierungen (100*, 110', 120', 130'; 110''', 120''', 130'*', 140'''), welche sich unter die Gate-Stapel (GSl - GS8) erstrecken. implanted, diffused channel doping (100 *, 110 ', 120', 130 '; 110' '', 120 '' ', 130' * ', 140' ''), which is under the gate stack (GSl - GS8) extend.
PCT/EP2003/008946 2002-09-02 2003-08-12 Method for the production of a semi-conductive structure comprising a plurality of gate stacks arranged on a semi-conductor substrate and corresponding semi-conductive structure WO2004025693A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10240429.1 2002-09-02
DE10240429A DE10240429A1 (en) 2002-09-02 2002-09-02 Production of a semiconductor structure used in the production of planar logic transistors comprises applying gate stacks onto a gate dielectric over a semiconductor substrate, implanting a dopant, and forming a side wall oxide

Publications (2)

Publication Number Publication Date
WO2004025693A2 true WO2004025693A2 (en) 2004-03-25
WO2004025693A3 WO2004025693A3 (en) 2004-04-29

Family

ID=31724251

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2003/008946 WO2004025693A2 (en) 2002-09-02 2003-08-12 Method for the production of a semi-conductive structure comprising a plurality of gate stacks arranged on a semi-conductor substrate and corresponding semi-conductive structure

Country Status (3)

Country Link
DE (1) DE10240429A1 (en)
TW (1) TW200404352A (en)
WO (1) WO2004025693A2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10356476B3 (en) * 2003-12-03 2005-06-30 Infineon Technologies Ag Method for producing a semiconductor structure
DE102004028852B4 (en) 2004-06-15 2007-04-05 Infineon Technologies Ag Method for forming trench memory cell structures for DRAMs
DE102005034387A1 (en) * 2005-07-22 2007-02-08 Infineon Technologies Ag Trench DRAM semiconductor memory has additional p-type anti-punch zone in semiconductor under neighboring strips of shallow trench isolation

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5355006A (en) * 1991-09-09 1994-10-11 Sharp Kabushiki Kaisha Semiconductor memory device with source and drain limited to areas near the gate electrodes
US5534449A (en) * 1995-07-17 1996-07-09 Micron Technology, Inc. Methods of forming complementary metal oxide semiconductor (CMOS) integrated circuitry
US6008094A (en) * 1997-12-05 1999-12-28 Advanced Micro Devices Optimization of logic gates with criss-cross implants to form asymmetric channel regions
US20010046745A1 (en) * 1999-02-25 2001-11-29 Ramachandra Divakaruni Bitline diffusion with halo for improved array threshold voltage control
US6329235B1 (en) * 1999-10-20 2001-12-11 United Microelectronics Corp. Method of performing a pocket implantation on a MOS transistor of a memory cell of a DRAM
US20010051407A1 (en) * 1999-09-01 2001-12-13 Luan C. Tran Semiconductor processing methods of forming integrated circuitry

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW203148B (en) * 1991-03-27 1993-04-01 American Telephone & Telegraph
DE19842665C2 (en) * 1998-09-17 2001-10-11 Infineon Technologies Ag Manufacturing process for a trench capacitor with an insulation collar

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5355006A (en) * 1991-09-09 1994-10-11 Sharp Kabushiki Kaisha Semiconductor memory device with source and drain limited to areas near the gate electrodes
US5534449A (en) * 1995-07-17 1996-07-09 Micron Technology, Inc. Methods of forming complementary metal oxide semiconductor (CMOS) integrated circuitry
US6008094A (en) * 1997-12-05 1999-12-28 Advanced Micro Devices Optimization of logic gates with criss-cross implants to form asymmetric channel regions
US20010046745A1 (en) * 1999-02-25 2001-11-29 Ramachandra Divakaruni Bitline diffusion with halo for improved array threshold voltage control
US20010051407A1 (en) * 1999-09-01 2001-12-13 Luan C. Tran Semiconductor processing methods of forming integrated circuitry
US6329235B1 (en) * 1999-10-20 2001-12-11 United Microelectronics Corp. Method of performing a pocket implantation on a MOS transistor of a memory cell of a DRAM

Also Published As

Publication number Publication date
TW200404352A (en) 2004-03-16
WO2004025693A3 (en) 2004-04-29
DE10240429A1 (en) 2004-03-18

Similar Documents

Publication Publication Date Title
DE4212829C2 (en) Process for the production of metal oxide semiconductor field effect transistors
DE60213889T2 (en) A semiconductor device
DE112006000208B4 (en) Memory device with trapezoidal bitlines and method of making the same, and array of memory elements
DE19531629C1 (en) Method of manufacturing an EEPROM semiconductor structure
DE102004009597A1 (en) Method of manufacturing a semiconductor device
DE3932621A1 (en) Semiconductor component with gate electrode - buried in groove of substrate element zone, with two=part source and drain zones
DE4224793A1 (en) THIN FILM FIELD EFFECT ELEMENT AND PRODUCTION METHOD DAFUER
DE3334333A1 (en) METHOD FOR PRODUCING A MOS DEVICE WITH SELF-ADJUSTED CONTACTS
DE19747776A1 (en) Semiconductor memory with stacked gate structure
DE102008009086B3 (en) Integrated circuit manufacturing method, involves oxidizing metallic layer of transistor, and implementing temperature step for activating dopants before oxidization of metallic layer or simultaneously for oxidizing metallic layer
DE102006029229A1 (en) Manufacturing method for an integrated semiconductor structure and corresponding integrated semiconductor structure
DE102004058603A1 (en) Electrically erasable and programmable read only memory cell, has common source region with lightly doped drain structure whose impurity region has higher dopant concentration than region of double diffused drain structure
DE2918888C2 (en) MNOS memory cell and process for its operation and for its manufacture
DE102008045344A1 (en) Flash memory and method for its production
WO2004107435A1 (en) Nrom semiconductor memory device and production method
DE4112044A1 (en) SEMICONDUCTOR DEVICE WITH AT LEAST TWO FIELD EFFECT TRANSISTORS AND MANUFACTURING METHOD FOR THE SAME
DE10342028A1 (en) Manufacture of integrated circuit involves doping portion of semiconductor substrate with nitrogen and charge carrier dopant source and forming thin dielectric on the doped portion of the substrate
DE112015003603T5 (en) Split-gate semiconductor device with L-shaped gate
DE10207740B4 (en) Method for producing a p-channel field effect transistor on a semiconductor substrate
WO2004025693A2 (en) Method for the production of a semi-conductive structure comprising a plurality of gate stacks arranged on a semi-conductor substrate and corresponding semi-conductive structure
DE4111519C2 (en) Semiconductor device and manufacturing method therefor
DE102008029791A1 (en) Process for the production of semiconductor devices
DE4311705C2 (en) Mask ROM semiconductor devices with impurity regions for controlling a transistor threshold voltage and method for their production
DE10356476B3 (en) Method for producing a semiconductor structure
DE19836953B4 (en) MOSFET and method for its production

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): JP KR US

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT RO SE SI SK TR

121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP

WWW Wipo information: withdrawn in national office

Country of ref document: JP