WO2004025693A3 - Method for the production of a semi-conductive structure comprising a plurality of gate stacks arranged on a semi-conductor substrate and corresponding semi-conductive structure - Google Patents

Method for the production of a semi-conductive structure comprising a plurality of gate stacks arranged on a semi-conductor substrate and corresponding semi-conductive structure Download PDF

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Publication number
WO2004025693A3
WO2004025693A3 PCT/EP2003/008946 EP0308946W WO2004025693A3 WO 2004025693 A3 WO2004025693 A3 WO 2004025693A3 EP 0308946 W EP0308946 W EP 0308946W WO 2004025693 A3 WO2004025693 A3 WO 2004025693A3
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WO
WIPO (PCT)
Prior art keywords
semi
conductive structure
gate
production
conductor substrate
Prior art date
Application number
PCT/EP2003/008946
Other languages
German (de)
French (fr)
Other versions
WO2004025693A2 (en
Inventor
Gerhard Enders
Juergen Faul
Bjoern Fischer
Lars Heineck
Matthias Hierlemann
Martin Popp
Peter Voigt
Original Assignee
Infineon Technologies Ag
Gerhard Enders
Juergen Faul
Bjoern Fischer
Lars Heineck
Matthias Hierlemann
Martin Popp
Peter Voigt
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Gerhard Enders, Juergen Faul, Bjoern Fischer, Lars Heineck, Matthias Hierlemann, Martin Popp, Peter Voigt filed Critical Infineon Technologies Ag
Publication of WO2004025693A2 publication Critical patent/WO2004025693A2/en
Publication of WO2004025693A3 publication Critical patent/WO2004025693A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Memories (AREA)

Abstract

The invention relates to a method for the production of a semi-conductor structure comprising a plurality of gate stacks (GS1 - GS8) which are arranged on a semi-conductor substrate (1). Said method comprises the following steps: applying the gate-stack (GS1 - GS8) to a gate dielectric (5) via the semi-conductor substrate (1); implanting doping (100, 105, 110, 120, 130; 105''', 110''', 120''', 130''', 140''') which is self-adjusted in relation to the edges of the gate stack (GS1 - GS8); and forming an side wall oxide (40) on the free side walls of the gate stack (GS1 - GS8) while at the same time forming diffused doping areas (100', 110', 120', 130'; 110''', 120''', 130''', 140''') below the gate stack. The invention also relates to said type of semi-conductor structure.
PCT/EP2003/008946 2002-09-02 2003-08-12 Method for the production of a semi-conductive structure comprising a plurality of gate stacks arranged on a semi-conductor substrate and corresponding semi-conductive structure WO2004025693A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10240429A DE10240429A1 (en) 2002-09-02 2002-09-02 Production of a semiconductor structure used in the production of planar logic transistors comprises applying gate stacks onto a gate dielectric over a semiconductor substrate, implanting a dopant, and forming a side wall oxide
DE10240429.1 2002-09-02

Publications (2)

Publication Number Publication Date
WO2004025693A2 WO2004025693A2 (en) 2004-03-25
WO2004025693A3 true WO2004025693A3 (en) 2004-04-29

Family

ID=31724251

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2003/008946 WO2004025693A2 (en) 2002-09-02 2003-08-12 Method for the production of a semi-conductive structure comprising a plurality of gate stacks arranged on a semi-conductor substrate and corresponding semi-conductive structure

Country Status (3)

Country Link
DE (1) DE10240429A1 (en)
TW (1) TW200404352A (en)
WO (1) WO2004025693A2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10356476B3 (en) 2003-12-03 2005-06-30 Infineon Technologies Ag Method for producing a semiconductor structure
DE102004028852B4 (en) 2004-06-15 2007-04-05 Infineon Technologies Ag Method for forming trench memory cell structures for DRAMs
DE102005034387A1 (en) * 2005-07-22 2007-02-08 Infineon Technologies Ag Trench DRAM semiconductor memory has additional p-type anti-punch zone in semiconductor under neighboring strips of shallow trench isolation

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5355006A (en) * 1991-09-09 1994-10-11 Sharp Kabushiki Kaisha Semiconductor memory device with source and drain limited to areas near the gate electrodes
US5534449A (en) * 1995-07-17 1996-07-09 Micron Technology, Inc. Methods of forming complementary metal oxide semiconductor (CMOS) integrated circuitry
US6008094A (en) * 1997-12-05 1999-12-28 Advanced Micro Devices Optimization of logic gates with criss-cross implants to form asymmetric channel regions
US20010046745A1 (en) * 1999-02-25 2001-11-29 Ramachandra Divakaruni Bitline diffusion with halo for improved array threshold voltage control
US6329235B1 (en) * 1999-10-20 2001-12-11 United Microelectronics Corp. Method of performing a pocket implantation on a MOS transistor of a memory cell of a DRAM
US20010051407A1 (en) * 1999-09-01 2001-12-13 Luan C. Tran Semiconductor processing methods of forming integrated circuitry

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW203148B (en) * 1991-03-27 1993-04-01 American Telephone & Telegraph
DE19842665C2 (en) * 1998-09-17 2001-10-11 Infineon Technologies Ag Manufacturing process for a trench capacitor with an insulation collar

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5355006A (en) * 1991-09-09 1994-10-11 Sharp Kabushiki Kaisha Semiconductor memory device with source and drain limited to areas near the gate electrodes
US5534449A (en) * 1995-07-17 1996-07-09 Micron Technology, Inc. Methods of forming complementary metal oxide semiconductor (CMOS) integrated circuitry
US6008094A (en) * 1997-12-05 1999-12-28 Advanced Micro Devices Optimization of logic gates with criss-cross implants to form asymmetric channel regions
US20010046745A1 (en) * 1999-02-25 2001-11-29 Ramachandra Divakaruni Bitline diffusion with halo for improved array threshold voltage control
US20010051407A1 (en) * 1999-09-01 2001-12-13 Luan C. Tran Semiconductor processing methods of forming integrated circuitry
US6329235B1 (en) * 1999-10-20 2001-12-11 United Microelectronics Corp. Method of performing a pocket implantation on a MOS transistor of a memory cell of a DRAM

Also Published As

Publication number Publication date
WO2004025693A2 (en) 2004-03-25
TW200404352A (en) 2004-03-16
DE10240429A1 (en) 2004-03-18

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