WO2004027821A3 - Ferroelectric transistor for storing two data bits - Google Patents

Ferroelectric transistor for storing two data bits Download PDF

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Publication number
WO2004027821A3
WO2004027821A3 PCT/US2003/024385 US0324385W WO2004027821A3 WO 2004027821 A3 WO2004027821 A3 WO 2004027821A3 US 0324385 W US0324385 W US 0324385W WO 2004027821 A3 WO2004027821 A3 WO 2004027821A3
Authority
WO
WIPO (PCT)
Prior art keywords
ferroelectric
region
fet
data bit
storing
Prior art date
Application number
PCT/US2003/024385
Other languages
French (fr)
Other versions
WO2004027821A2 (en
Inventor
Alfred P Gnadinger
Klaus Dimmler
Original Assignee
Cova Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/246,975 external-priority patent/US6714435B1/en
Application filed by Cova Technologies Inc filed Critical Cova Technologies Inc
Priority to AU2003273228A priority Critical patent/AU2003273228A1/en
Publication of WO2004027821A2 publication Critical patent/WO2004027821A2/en
Publication of WO2004027821A3 publication Critical patent/WO2004027821A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5657—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using ferroelectric storage elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/78391—Field effect transistors with field effect produced by an insulated gate the gate comprising a layer which is used for its ferroelectric properties
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors

Abstract

A method of storing and accessing two data bits in a single ferroelectric FET includes selectively polarizing two distinct ferroelectric regions (105, 106) in the same gate dielectric layer separated by a non-ferroelectric dielectric region (107). A first ferroelectric region (106) is sandwiched between the substrate (100) and the gate terminal (108) in the region of the source and is polarized in one of two states to form a first data bit within the FET. A second ferroelectric region (105) is sandwiched between the substrate (100) and the gate terminal (108) in the region of the drain and is polarized in one of two states to form a second data bit within the FET. Detection of the first data bit is accomplished by selectively applying a read bias to the FET terminals, a first current resulting when a first state is stored and a second current resulting when a second state is stored. The polarization of the second data bit is accomplished by reversing the source and drain voltages.
PCT/US2003/024385 2002-09-19 2003-08-04 Ferroelectric transistor for storing two data bits WO2004027821A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003273228A AU2003273228A1 (en) 2002-09-19 2003-08-04 Ferroelectric transistor for storing two data bits

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US10/246,975 US6714435B1 (en) 2002-09-19 2002-09-19 Ferroelectric transistor for storing two data bits
US10/246,975 2002-09-19
US10/305,205 US6888736B2 (en) 2002-09-19 2002-11-26 Ferroelectric transistor for storing two data bits
US10/305,205 2002-11-26

Publications (2)

Publication Number Publication Date
WO2004027821A2 WO2004027821A2 (en) 2004-04-01
WO2004027821A3 true WO2004027821A3 (en) 2004-05-06

Family

ID=32033230

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/024385 WO2004027821A2 (en) 2002-09-19 2003-08-04 Ferroelectric transistor for storing two data bits

Country Status (3)

Country Link
US (1) US6888736B2 (en)
AU (1) AU2003273228A1 (en)
WO (1) WO2004027821A2 (en)

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US8164941B2 (en) * 2006-12-27 2012-04-24 Hynix Semiconductor Inc. Semiconductor memory device with ferroelectric device and refresh method thereof
KR100919559B1 (en) * 2006-12-27 2009-10-01 주식회사 하이닉스반도체 Semiconductor memory device using ferroelectric device and method for refresh thereof
KR101004566B1 (en) 2006-12-27 2011-01-03 주식회사 하이닉스반도체 Semiconductor memory device using ferroelectric device and method for refresh thereof
JP5902111B2 (en) 2013-03-06 2016-04-13 株式会社東芝 Semiconductor memory device
US10090036B2 (en) 2015-12-21 2018-10-02 Imec Vzw Non-volatile memory cell having pinch-off ferroelectric field effect transistor
KR102606923B1 (en) * 2018-06-21 2023-11-27 삼성디스플레이 주식회사 Display device
US11855204B2 (en) * 2020-04-20 2023-12-26 Unist (Ulsan National Institute Of Science And Technology) Ultra high-density memory and multi-level memory device and method of fabricating the same
US11532746B2 (en) * 2020-05-29 2022-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-bit memory storage device and method of operating same
DE102021105038A1 (en) * 2020-05-29 2021-12-02 Taiwan Semiconductor Manufacturing Co., Ltd. MULTI-BIT STORAGE DEVICE AND METHOD OF OPERATING THE SAME
US20240120420A1 (en) * 2022-10-05 2024-04-11 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Ferroelectric field-effect transistors with a hybrid well

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Also Published As

Publication number Publication date
US6888736B2 (en) 2005-05-03
AU2003273228A8 (en) 2004-04-08
US20040057319A1 (en) 2004-03-25
AU2003273228A1 (en) 2004-04-08
WO2004027821A2 (en) 2004-04-01

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