WO2004042506A3 - Methods and apparatus for improved memory access - Google Patents

Methods and apparatus for improved memory access Download PDF

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Publication number
WO2004042506A3
WO2004042506A3 PCT/US2003/033679 US0333679W WO2004042506A3 WO 2004042506 A3 WO2004042506 A3 WO 2004042506A3 US 0333679 W US0333679 W US 0333679W WO 2004042506 A3 WO2004042506 A3 WO 2004042506A3
Authority
WO
WIPO (PCT)
Prior art keywords
shift registers
data
sets
loaded
memory devices
Prior art date
Application number
PCT/US2003/033679
Other languages
French (fr)
Other versions
WO2004042506A2 (en
Inventor
William T Lynch
David J Herbison
Original Assignee
Ring Technology Entpr Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=32174817&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=WO2004042506(A3) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Ring Technology Entpr Llc filed Critical Ring Technology Entpr Llc
Priority to AU2003301774A priority Critical patent/AU2003301774A1/en
Priority to AT03810796T priority patent/ATE472802T1/en
Priority to EP03810796A priority patent/EP1576445B1/en
Priority to JP2004550087A priority patent/JP2006505066A/en
Priority to DE60333227T priority patent/DE60333227D1/en
Publication of WO2004042506A2 publication Critical patent/WO2004042506A2/en
Publication of WO2004042506A3 publication Critical patent/WO2004042506A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C29/32—Serial access; Scan testing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1036—Read-write modes for single port memories, i.e. having either a random port or a serial port using data shift registers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C2029/3202—Scan chain

Abstract

A memory access scheme employing one or more sets of shift registers interconnected in series to which data may be loaded from or written into one or more memory devices. That is, data from the memory devices may be parallel loaded into the sets of shift registers and then serially shifted through the shift registers until it is output from the sets of shift registers and transferred to its destination. Additionally, the data may be read from and loaded into the memory devices to/from the sets of shift registers such that the shifting of the shift registers is uninterrupted during the reading and/or loading of data. Additionally, data from the memory devices may be loaded into two or more parallel chains of shift registers and then serially shifted through the shift register chains.
PCT/US2003/033679 2002-10-31 2003-10-23 Methods and apparatus for improved memory access WO2004042506A2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
AU2003301774A AU2003301774A1 (en) 2002-10-31 2003-10-23 Methods and apparatus for improved memory access
AT03810796T ATE472802T1 (en) 2002-10-31 2003-10-23 METHOD AND APPARATUS FOR IMPROVED MEMORY ACCESS
EP03810796A EP1576445B1 (en) 2002-10-31 2003-10-23 Methods and apparatus for improved memory access
JP2004550087A JP2006505066A (en) 2002-10-31 2003-10-23 Method and apparatus for improved memory access
DE60333227T DE60333227D1 (en) 2002-10-31 2003-10-23 METHOD AND DEVICES FOR IMPROVED MEMORY ACCESS

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/284,198 US6879526B2 (en) 2002-10-31 2002-10-31 Methods and apparatus for improved memory access
US10/284,198 2002-10-31

Publications (2)

Publication Number Publication Date
WO2004042506A2 WO2004042506A2 (en) 2004-05-21
WO2004042506A3 true WO2004042506A3 (en) 2005-09-09

Family

ID=32174817

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/033679 WO2004042506A2 (en) 2002-10-31 2003-10-23 Methods and apparatus for improved memory access

Country Status (8)

Country Link
US (3) US6879526B2 (en)
EP (1) EP1576445B1 (en)
JP (1) JP2006505066A (en)
KR (1) KR100994393B1 (en)
AT (1) ATE472802T1 (en)
AU (1) AU2003301774A1 (en)
DE (1) DE60333227D1 (en)
WO (1) WO2004042506A2 (en)

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Also Published As

Publication number Publication date
DE60333227D1 (en) 2010-08-12
KR100994393B1 (en) 2010-11-16
US6879526B2 (en) 2005-04-12
US20050128823A1 (en) 2005-06-16
ATE472802T1 (en) 2010-07-15
EP1576445A2 (en) 2005-09-21
WO2004042506A2 (en) 2004-05-21
US20070237009A1 (en) 2007-10-11
JP2006505066A (en) 2006-02-09
US7313035B2 (en) 2007-12-25
US20040085818A1 (en) 2004-05-06
AU2003301774A1 (en) 2004-06-07
KR20050062781A (en) 2005-06-27
EP1576445B1 (en) 2010-06-30
EP1576445A4 (en) 2006-08-16
AU2003301774A8 (en) 2004-06-07
US7808844B2 (en) 2010-10-05

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