WO2004042800A3 - Semiconductor arrangement - Google Patents

Semiconductor arrangement Download PDF

Info

Publication number
WO2004042800A3
WO2004042800A3 PCT/DE2003/003567 DE0303567W WO2004042800A3 WO 2004042800 A3 WO2004042800 A3 WO 2004042800A3 DE 0303567 W DE0303567 W DE 0303567W WO 2004042800 A3 WO2004042800 A3 WO 2004042800A3
Authority
WO
WIPO (PCT)
Prior art keywords
lines
type
central region
region
semiconductor arrangement
Prior art date
Application number
PCT/DE2003/003567
Other languages
German (de)
French (fr)
Other versions
WO2004042800A2 (en
Inventor
Dirk Fuhrmann
Reidar Lindstedt
Original Assignee
Infineon Technologies Ag
Dirk Fuhrmann
Reidar Lindstedt
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Dirk Fuhrmann, Reidar Lindstedt filed Critical Infineon Technologies Ag
Priority to AU2003287853A priority Critical patent/AU2003287853A1/en
Priority to EP03779674A priority patent/EP1559131A2/en
Publication of WO2004042800A2 publication Critical patent/WO2004042800A2/en
Publication of WO2004042800A3 publication Critical patent/WO2004042800A3/en
Priority to US11/123,841 priority patent/US7136295B2/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures

Abstract

The invention relates to a semiconductor arrangement in which a plurality of individual element fields (2) are arranged along lines (3) of a first type and lines (4) of a second type, on a semiconductor chip (1). The lines of the first or second type extend from an inner region (A;5) to an outer region (B), and the lines of the respective other type of lines extend around the inner region (A;5). A circular central region (5) is formed in one form of embodiment, e.g. in a DRAM memory, said central region containing logic elements which are standard on memory modules. Memory cells (2) are arranged around the central region (5) in such a way that they are located along word lines (3) embodied in the form of concentric rings.
PCT/DE2003/003567 2002-11-08 2003-10-27 Semiconductor arrangement WO2004042800A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
AU2003287853A AU2003287853A1 (en) 2002-11-08 2003-10-27 Semiconductor arrangement
EP03779674A EP1559131A2 (en) 2002-11-08 2003-10-27 Semiconductor arrangement
US11/123,841 US7136295B2 (en) 2002-11-08 2005-05-06 Semiconductor arrangement

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10252058.5 2002-11-08
DE10252058A DE10252058A1 (en) 2002-11-08 2002-11-08 Semiconducting arrangement has lines of first or second type running from inner to outer region, lines of the other type running around inner region so as to enclose it, auxiliary area in inner region

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11/123,841 Continuation US7136295B2 (en) 2002-11-08 2005-05-06 Semiconductor arrangement

Publications (2)

Publication Number Publication Date
WO2004042800A2 WO2004042800A2 (en) 2004-05-21
WO2004042800A3 true WO2004042800A3 (en) 2004-08-05

Family

ID=32185374

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2003/003567 WO2004042800A2 (en) 2002-11-08 2003-10-27 Semiconductor arrangement

Country Status (6)

Country Link
US (1) US7136295B2 (en)
EP (1) EP1559131A2 (en)
CN (1) CN1711641A (en)
AU (1) AU2003287853A1 (en)
DE (1) DE10252058A1 (en)
WO (1) WO2004042800A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004028076A1 (en) * 2004-06-09 2006-01-05 Infineon Technologies Ag Integrated semiconductor memory, has voltage generators for providing identical electric potential, where generators are arranged in direct proximity to respective memory cell array

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6120349A (en) * 1984-07-06 1986-01-29 Hitachi Ltd Lsi assemblage
US4731643A (en) * 1985-10-21 1988-03-15 International Business Machines Corporation Logic-circuit layout for large-scale integrated circuits
EP0532305A2 (en) * 1991-09-13 1993-03-17 Nec Corporation Power supply system for semiconductor chip
JPH08116036A (en) * 1994-10-14 1996-05-07 Hitachi Ltd Memory chip
JPH1128458A (en) * 1997-07-09 1999-02-02 B M:Kk Water treatment and device therefor
US6154051A (en) * 1998-11-05 2000-11-28 Vantis Corporation Tileable and compact layout for super variable grain blocks within FPGA device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01128458A (en) * 1987-11-13 1989-05-22 Fujitsu Ltd Semiconductor memory device
JPH02268439A (en) * 1989-04-10 1990-11-02 Hitachi Ltd Semiconductor integrated circuit device
JPH0474465A (en) * 1990-07-17 1992-03-09 Nec Corp Semiconductor storage device
US5880492A (en) * 1995-10-16 1999-03-09 Xilinx, Inc. Dedicated local line interconnect layout
KR100213249B1 (en) * 1996-10-10 1999-08-02 윤종용 Layout of semiconductor memory cell
DE10257665B3 (en) * 2002-12-10 2004-07-01 Infineon Technologies Ag Semiconductor memory with an arrangement of memory cells

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6120349A (en) * 1984-07-06 1986-01-29 Hitachi Ltd Lsi assemblage
US4731643A (en) * 1985-10-21 1988-03-15 International Business Machines Corporation Logic-circuit layout for large-scale integrated circuits
EP0532305A2 (en) * 1991-09-13 1993-03-17 Nec Corporation Power supply system for semiconductor chip
JPH08116036A (en) * 1994-10-14 1996-05-07 Hitachi Ltd Memory chip
JPH1128458A (en) * 1997-07-09 1999-02-02 B M:Kk Water treatment and device therefor
US6154051A (en) * 1998-11-05 2000-11-28 Vantis Corporation Tileable and compact layout for super variable grain blocks within FPGA device

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 0101, no. 68 (E - 411) 14 June 1986 (1986-06-14) *
PATENT ABSTRACTS OF JAPAN vol. 0133, no. 74 (E - 808) 18 August 1989 (1989-08-18) *
PATENT ABSTRACTS OF JAPAN vol. 0162, no. 91 (E - 1224) 26 June 1992 (1992-06-26) *
PATENT ABSTRACTS OF JAPAN vol. 1996, no. 09 30 September 1996 (1996-09-30) *

Also Published As

Publication number Publication date
EP1559131A2 (en) 2005-08-03
CN1711641A (en) 2005-12-21
WO2004042800A2 (en) 2004-05-21
AU2003287853A8 (en) 2004-06-07
US20050247959A1 (en) 2005-11-10
DE10252058A1 (en) 2004-05-27
AU2003287853A1 (en) 2004-06-07
US7136295B2 (en) 2006-11-14

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