WO2004042994A1

WO2004042994A1 - Circuit and method for high speed data transfer

Info

Publication number: WO2004042994A1
Application number: PCT/EP2003/012390
Authority: WO
Inventors: Sven Simon; Andreas Wortmann
Original assignee: Hochschule Bremen
Priority date: 2002-11-08
Filing date: 2003-11-06
Publication date: 2004-05-21
Also published as: AU2003286154A1; DE10251950A1

Abstract

The invention relates to a circuit for extracting data from a serial data signal for data high-speed transmission between or inside integrated circuits and to a corresponding method. In order to simplify a layout on an integrated circuit, in particular by means of a semicustom stream, the inventive circuit is provided with an unadjustable scanning unit for the multiple scanning of a data signal during the clock period of a receiver clock signal in such a way that several phase bit streams, which are synchronous with the receiver clock, are produced. Said circuit also comprises an evaluation unit for determining a data sequence which best matches the data of the data signal by evaluating correlating properties of the synchronous phase data streams and for emitting said data sequence.

Description

Circuit arrangement and method for high-speed data transfer

The invention relates to a circuit arrangement for extracting data from a serial data signal for high-bit-rate transmission of data between or within integrated circuits and to a corresponding method.

With each new process technology for integrated circuits, the integration density and the associated maximum possible circuit complexity (currently approx. 10 million transistors per IC) increases significantly. Because design complexity increases with circuit complexity, computer-aided design techniques are essential. State of the art for the design of complex ICs is the automatic generation of a gate network list from a hardware description in a suitable hardware modeling language (eg VHDL, Verilog or SystemC) using a so-called synthesis tool. The generated circuit at the gate level is further expanded by transferred automatic placement and wiring steps into a mask layout for IC production. This design flow is called the semicustom design flow.

In addition to the increasing complexity, the integrated circuits operate at ever higher clock rates or data rates. Furthermore, the amount of data to be exchanged between ICs or between the functional blocks on an IC increases sharply. Since the maximum number of pins of IC packages is in many cases a limitation for the number of data lines, multiple data streams must be transmitted over lines using the time multiplex method. Therefore, or because the output data stream is already high bit rate, it is necessary that serial data streams can be sent and received with very high data rates (e.g. ^ 00 Mbit / s). However, the established circuits for these high-speed connections are based on design processes that require a high degree of manual work and therefore cannot be assigned to the semi-custom design flow. The manual design extends to the level of the mask layout and is called the Fill Custom Design Flow. The implementation of a circuit in a filling custom design flow is also called a hard macro because of the definition of the geometry at the mask layout level

The invention is therefore based on the object of specifying a circuit and a corresponding method for extracting data from a received serial data signal for fast, that is to say high-bit-rate transmission of the data between or within integrated circuits which involve the use of a semicustom design flow in the design and enable easier implementation on an IC.

This object is achieved by a circuit arrangement according to claim 1

an uncontrolled sampling unit for multiple sampling of the data signal within a clock period of a receiver clock signal for generating a plurality of phase bit streams synchronous with the receiver clock, and

- An evaluation unit for determining a data sequence that best matches the data of the data signal by evaluating correlation properties of the synchronous phase bit streams generated and for outputting the data sequence. A corresponding method according to the invention is specified in claim 20. Advantageous refinements are specified in the subclaims.

In contrast to the known solutions, the circuit arrangement according to the invention, which is also referred to as a synthesizable high-speed receiver, is based on a semi-custom design flow. With the exception of placing a few cells, it is possible to use only automatic design steps of a semi-custom design flow. The economic benefits of this circuit architecture lie in a shorter development cycle, easier portability to new process technologies due to the ability to be synthesized, and easier integration into a circuit environment based on a semicustom design flow. In particular, a significant reduction in the number of global timing-critical paths can be achieved in the invention, so that the use of a semicustom design flow is made possible.

The invention can be used both for data transmission between integrated circuits, which should also include data transmission between several chips or different dies, that is to say also within a single integrated circuit, which should also include data transmission on a single chip or a single die come.

According to the invention, so-called phase bit streams are generated from the serial data signal. Their correlation properties are then evaluated, i.e. it is checked whether and to what extent there is agreement or similarity between the phase bit streams, with minor deviations being permitted, if necessary. The data sequence to be output is then determined on the basis of the result, for which there are basically different possibilities.

The correlation properties can be defined, for example, using a so-called correlation measure. The correlation measure assigns a so-called correlation vector to each phase bit stream in an observation period. This correlation vector can be determined according to any calculation rules. A suitable calculation rule is one which, in the case of a phase bit stream matching the other phase bit streams and in the event of a phase bit stream not matching the other phase bit streams, results in differences for the correlation vectors of the phase bit stream. The correlation measure then serves in the evaluation unit to extract the data of the data signal from the phase bit streams on the basis of the differences in the above correlation numbers.

According to the invention, the scanning unit also contains no regulation. This results in a significant reduction in the number of global timing-critical paths, so that the use of a semicustom design flow is possible. Analog subcircuits and components, especially an analog circuit for clock generation, can also be avoided. Data streams with phase shifts of the transmit data stream and receive data stream of more than one bit duration can thus be received.

In the claims 2 to 7 preferred configurations of the scanning unit are given. The sampling is preferably carried out within a clock period of the receiver clock at a fixed point in time, namely using the rising edge of the receiver clock signal.

The scanning unit is preferably operated only with a single receiver clock signal via a single line at the input of the scanning unit, that is to say the scanning unit in particular does not have a plurality of clock phases, e.g. via a bus system. In the preferred embodiment according to claim 3, the data signal is initially delayed in time, so as to generate different phases of the data signal. These are then sampled in parallel with the same receiver clock signal to generate the phase bit streams. An advantageous embodiment for implementing such a scanning unit is defined in claim 4. The preferred embodiments according to claims 3 and 4 use only one clock range, namely the receiver clock.

In the other preferred embodiment of the scanning unit according to claim 5, the receiver clock signal is delayed several times in order to generate different phases of the receiver clock signal. The same data signal is then sampled several times with these phase-shifted receiver clock signals in order to generate the phase currents. A specific embodiment of such a scanning unit is defined in claim 6. The advantage of the preferred embodiments according to claims 5 and 6 lies in the relatively low disturbance of the sampling times for the phase bit streams due to the data dependence of the delay times in the delay chain, since the clock signal is data-independent and strictly periodic. The preferred embodiment of the delay elements of the delay chain according to claim 7 has no means, such as control signals, for setting the delay time. Furthermore, variations in the delay time of the individual delay elements are accepted, and there is no regulating means for regulating the delay elements.

In an advantageous embodiment it is provided that the number of delay elements and / or the delay times of the delay elements is selected such that the sum of the delay times of all delay elements is at least as large as the clock period of the data signal. The maximum variation of the delays or phase shifts of the data signal or clock signal can be more than the delay or phase shift of a delay element of the data or clock signal between different ICs or at different times in an IC. The number of data or clock signals with different phases of the identical circuits on different ICs is also variable, or the number of different data or clock signals of the identical circuits on one IC is variable over time. This variation can be in the order of magnitude of factor 2 or more, for example; however, it is limited and not arbitrarily large. The effect of this variation on the selection of a phase bit stream undisturbed by the jitter is compensated for by the evaluation unit and selectors provided in preferred configurations. In contrast to known circuit arrangements, the phase shift and the transit time of corresponding phase signals are not assumed to be constant, and the number of phase signals with a defined phase shift per clock period is also not assumed to be constant. There are also no VCO or PLL structures, which set the phases or runtimes by means of a control.

According to the invention, the value of the phase shift of data and / or clock signals is variable, in particular during operation. The number of different phase positions or the number of phases per clock period is also variable. In the case of known circuit arrangements, on the other hand, a control is provided which sets a delay independent of the sample, the variation of which is smaller than the delay itself. Furthermore, known circuit arrangements use controlled delays which are set via a control signal. Without control, the delay would generally not have the delay time provided for the switching, so that not all of the phase signals necessary for the evaluation unit would be available with the intended values for the phase shift; the circuits would not work reliably.

Preferred configurations of the evaluation unit are specified in claims 8 to 10 and 15. According to the invention, at least two adjacent phase bit streams are preferably evaluated in order to determine a data sequence therefrom which matches the data of the received serial data signal as closely as possible. Correlation properties of the phase bit streams are evaluated in order to find a phase bit stream with a large correlation measure.

Preferably, according to claim 9, at least one corresponding selection unit is also provided in the evaluation unit, which selects a phase bit stream that best matches the data of the received data signal based on correlation properties of the phase bit streams. With this selection, several phase bit streams can also be selected using several selection units. If several selection units are provided, these are coordinated with one another by an evaluation control unit. Either a selected phase bit stream is used to determine the data sequence, or the data sequence is determined jointly, for example by majority vote, from a plurality of phase bit streams.

Advantageous further developments of the aforementioned selection unit are specified in claims 11 to 14. For the selection of the phase bit stream, at least one difference signal is preferably formed between at least two phase bit streams in order to check whether and to what extent the phase bit streams differ from one another or to determine the correlation of two phase bit streams. The correlations between adjacent phase bit streams are preferably determined and evaluated. If it is found that the phase bit streams do not differ from one another or have a high degree of correlation, it is assumed that the phase bit stream correctly reproduces the data sequence contained in the input data signal.

In a further embodiment, it is provided that the at least one selection unit additionally has a detection unit in order to observe and, if necessary, to accumulate correlation differences between the phase bit streams ascertained by means of the difference formation unit. It is preferred for each dif- reference signal generates a corresponding detection signal. Instead of selecting the best possible phase bit stream directly from the difference signals, the detection signals are then used in a further embodiment to select the best possible phase bit stream, which may simplify implementation due to simpler timing conditions and which may reduce the tolerance to short-term disturbances of the data signal and can improve short-term variations in the delay times of the delay elements.

The selection of the best possible phase bit stream by the at least one selection unit is fundamentally variable in time and is constantly adapted. This means that a single phase bit stream is not selected at the start of the data transmission, but rather is checked at regular intervals whether the selected phase bit stream is also the best choice.

According to claim 15, the evaluation control unit preferably selects at least one of the phase bit streams selected by the selection units in order to output this data as a received data sequence. By evaluating several selected phase bit streams, several data bits of the input signal can be extracted within a receiver clock period. Furthermore, when the selection is changed by the evaluation control unit, it is ensured that the data is extracted without gaps and that no data bit is evaluated multiple times.

The circuit according to the invention can be generated in accordance with the configurations according to claims 16 and 17 in that a synthesis tool generates a gate network list using a standard cell library, starting from a hardware description language (eg VHL, Verilog, SystemC). This grid list consists of cells from a standard cell library, which are placed and wired in a semicustom design flow using tools. According to the embodiment according to claim 18, by manually supporting the placement algorithms of the corresponding tool, the transit time of the signals on the timing-critical paths, such as between the delay elements, can be reduced or adjusted. The invention is explained in more detail below with reference to the drawings. Show it:

FIG. 1 possible areas of application of the invention,

FIG. 2 shows a block diagram to illustrate timing problems in synchronous data transmission,

FIG. 3 shows a time diagram to explain jitter,

FIG. 4 time diagrams for explaining Skew,

FIG. 5 shows an eye diagram to explain the scanning in a known solution,

FIG. 6 shows a block diagram of a known circuit arrangement,

FIG. 7 shows an eye diagram to explain the scanning in a further known solution,

FIG. 8 shows a block diagram of a further known circuit arrangement,

FIG. 9 shows an eye diagram to explain the scanning in the circuit arrangement according to the invention,

FIG. 10 shows a block diagram of an embodiment of the circuit arrangement according to the invention,

FIG. 11 shows a block diagram of a further embodiment of the circuit arrangement according to the invention,

FIG. 12 shows a simplified block diagram of the basic design of the circuit arrangement according to the invention,

FIG. 13 shows a first embodiment of a scanning unit,

FIG. 14 signal curves of the signals occurring in the scanning unit according to FIG. 13,

FIG. 15 shows a further embodiment of a scanning unit, FIG. 16 shows a block diagram to illustrate the signal curves in the circuit arrangement according to the invention,

FIG. 17 shows a delay chain in a concrete implementation of the scanning unit,

FIG. 18 waveforms of the signals occurring in the delay chain according to FIG. 17,

FIG. 19 shows a chain of flip-flops in a specific implementation,

FIG. 20 waveforms of the signals occurring in the circuit according to FIG. 19,

FIG. 21 shows a block diagram of an embodiment of the evaluation unit according to the invention,

FIG. 22 shows an embodiment of a difference formation unit,

FIG. 23 signal profiles of the signals occurring in the difference formation unit according to FIG. 22,

FIG. 24 shows an embodiment of a zero trap,

FIG. 25 shows the state diagram of a zero trap according to FIG. 24,

FIG. 26 signal curves of the detection signals generated by the zero trap according to FIG. 24 over a longer period of time,

FIG. 27 signal curves of the detection signals generated by the zero trap over a shorter period of time,

FIG. 28 shows a state diagram to explain the switchover between different phase bit streams,

FIG. 29 shows a section of the signal curves according to FIG. 26 to explain the temporal adaptation of the selection of the phase bit stream,

FIG. 30 shows an alternative embodiment for implementing the scanning unit by means of delay elements arranged in parallel, FIG. 31 shows a further embodiment for implementing the scanning unit by combining delay elements and arranged in parallel and in series

FIG. 32 shows a block diagram of a further embodiment of the evaluation unit according to the invention.

FIGS. 1a and 1b roughly show the areas of application of the present invention, namely interchip communication between chips IC1, IC2 (FIG. 1a) connected, for example, via PCB, plug or cable or intrachip communication within ICs (FIG. 1b ), for example between different clock areas CD1, CD2 (CD = Clock Domain).

If data is transferred between different ICs at high data rates (more than 500Mbit / s), timing problems arise due to differences in runtime between clock and data. Runtime differences arise due to the dependency of the running times on the IC on voltage, temperature and manufacturing tolerances and outside the IC through the dependency of the running times on package and board manufacturing tolerances. These runtime differences can therefore change during the operation of the circuits and are therefore time-dependent. The reason for the timing problems at high data rates is that runtime differences can be of the order of the clock period and there is no guarantee that the data will reach the receiving circuit within the correct clock period, as should normally be the case with synchronous circuit concepts. This problem is clear in Figure 2.

In the example shown, time-varying differences in transit time of ± 0.5 ns occur between transmitter 1 and receiver 2 both on the data line 3 and on the clock line 4. For example, the specified transit time of the clock line TD _k and the data line TD _dat . The mean transit time difference | TD _dat - TD _dk | can be statically compensated, but with a small time-dependent relative shift of the two signals, synchronous transmission is not possible, since 1ns already corresponds to an entire clock cycle.

The disturbances occurring during data transmission cause disturbing effects which can be observed on the received data signal and which are referred to as jitter and wander. the. These are illustrated in Figures 3 and 4. The jitter is a change in the bit duration of the data signal which is random from clock period to clock period and limited in amount. The physical cause of such jitter is, for example, very brief voltage drops on the supply lines of an IC. These arise, among other things, from the short-term very high current requirements when reloading gate capacities during switching operations due to data changes, for example flip-flops, at the time of a clock edge. Crosstalk and reflection can also lead to jitter.

Skew is used here to denote the time-dependent difference in transit time between two signals A and B. The change in the transit time difference between two signals A and B is called a wander. The hike is time-dependent and is subject to a slow dynamic change. It arises, for example, from temperature and voltage fluctuations and different properties of the cables for signals A and B.

There are known proposals for solving this data transmission problem, which can be divided into two different concepts. In a clock / data recovery architecture (CDR), as outlined in FIG. 6, the frequency and the phase position of the sampling clock signal are set to the data stream on the basis of the signal change of the data signal in such a way that the data are taken over at a point in time at which they are stable. This can be seen in the eye diagram shown in FIG. 5. The sampling clock is tuned by synchronization with the edges of the data signal.

Both the data and the data clock are obtained from the input signal. Clock recovery circuits 5 are widely used as phase-locked loops (PLL) or delay-locked loops (DLL). Because of the feedback loop within such a PLL / DLL, this architecture is also referred to in FIG. 6 as the feedback architecture. The timing-critical paths are marked in the circuit diagram.

In the following, paths are called critical if the signal delay times (eg layout-influenced) or the skew between the signals of a bus must lie within a tolerance window, which is generally much smaller than the highest clock period of the circuit. If the signal transit time or the skew between the signals lies outside the tolerance window, the functionality of the circuit is jeopardized. In the circuit architecture shown, the timing paths and the modules with timing paths are designed in a fill custom design flow. Independently of each other, such a rather complex circuit is required for each data input. The integration of such a circuit is complex, in particular because of the required power supply and voltage stability.

The other circuit concept established in the literature only requires one clock generator for several identical serial data inputs. It is a feed-forward architecture in which only the data and not the clock signal are extracted from the data input signal data_i. This data recovery architecture is shown in FIG. 8. The data signal data_i is oversampled asynchronously with many precisely coordinated phases of the same clock signal clk_ref, preferably at exactly equidistant times, as can be seen in the eye diagram shown in FIG. The data are extracted from the transmitted data signal data_o by means of a majority decision or another suitable method. To implement such an architecture with a plurality of serial receivers 2, only one PLL / DLL 5 is required to generate the clock phases, but many clock phases clk_k must be generated, and the distribution of these many global signals to the individual receiver modules 2 is timing-critical ,

A PLIJDLL 5 is used in both architectures in order to precisely match the phases generated from the clock signal. However, the design of a PLL / DLL is correspondingly complex since it is a circuit with analog components. Since the distribution and transport of the different clock phases clk_k is also timing-critical, exact manual placement of the lines and gates is required. In general, a decisive disadvantage of the circuit architecture shown in FIG. 8 is that the timing paths have to be routed from one source to all receiver circuits 2. Such high-speed receiver circuits are therefore implemented using a filling custom design flow. This also applies to the circuit shown in FIG. 6, the subcircuits or modules of which are largely timing-critical.

Only with this design method, in which the individual transistors are dimensioned and lines or cells are placed, is it possible to design the analog circuit parts in such a way that the PLIJDLL 5 generates correspondingly exact clock signals and these timing-critical signals are precisely distributed. The effort that this approach arises, but is very high. Implementation is technology dependent and requires manual circuit design. A time-consuming analog simulation is necessary to verify the design. This design method is therefore very expensive.

A semicustom design flow is simpler and therefore mostly used in industry to implement less problematic circuits. This design process is heavily computer-aided and largely automated. Here the function of the circuit is described in a hardware modeling language. The most widely used are the hardware modeling languages VHDL, Verilog and SystemC. Synthesis tools translate the source code into a gate network list using elementary standard cells that are made available by semiconductor manufacturers in libraries. It is said that the circuit can be synthesized. This automated method for circuit design enables large circuits to be created and the target technology to be changed easily by exchanging the cell libraries.

Cost minimization in the development of ICs can be achieved by implementing subcircuits that were previously based on a fill custom design flow in a semicustom design flow. The circuit arrangement according to the invention can be implemented in a semicustom design flow. The main advantage of the circuit presented is a simplification and reduction of the circuit area and the design effort.

The concept of the circuit according to the invention is shown in FIG. 10. This has a sampling unit 6 for each data signal of the data signal bus data_i (0..M), in each of which a plurality of phase bit streams SAMPLE which are synchronous with the data clock clk_f_i (often also referred to as the receiver clock) are generated. These are each fed to a separate evaluation unit 7, in which the data sequence which best matches the data of the received data signals data_i (0..M) is determined by correlation properties of the generated synchronous phase bit streams SAMPLE. These are then output as the output signal bus data_ (0..M).

The number of timing paths are minimized and reduced to local areas. The distribution of the receiver clock clk_f_i is not critical to the timing, since the phase position of the clock signal clk_f_i is none for the correct functionality of the circuit Role play. In principle, no PLL or DLL is required to operate the circuit. This represents a considerable simplification. As is shown in the eye diagram in FIG. 9, the sampling can take place at times at which the distance is not known and is within a large tolerance range.

In some applications, however, a PLL will still be present on the IC, since a divided clock clk_ref is taken over externally as a reference clock with a lower clock frequency on the IC, as shown in FIG. 11. The high-frequency clock signal clk_f_i is then recovered from the divided clock signal clkjef with a PLL / DLL 5. In these cases, however, the number of PLL / DLLs can often be reduced when using several such receivers with the circuit architecture presented here, since the clock distribution itself is not critical in terms of timing. However, more complex PLLs with many clock phases, as in the feed-forward architectures shown in FIGS. 6 and 8 with complex distribution of the individual clock phases, are in no case necessary.

Two alternative architecture variants of the new concept are proposed, which are explained further below. Both receiver architectures are feed forward architectures. This means that the clock signal is not adapted to the data signal. In this approach, the coordination of different clock phases is also dispensed with, so that no regulation of the scanning signals is carried out. This means that the largely manual Fill Custom Design Flow can be dispensed with. This arrangement is therefore particularly suitable for the use of a semi-custom design flow.

In the receiver shown in FIG. 12, after a sampling of the data signal dataj by a sampling unit 6, which, as will be explained in more detail below, preferably has a cascade of N flip-flops, either with N phase-shifted clock signals or with a clock signal clk_f_i and N -data-delayed data signals, N so-called phase bit streams SAMPLE. If the clock phases or data delays are adequately resolved, there is at least one phase bit stream with a stable and approximately the same receiver data rate and clock frequency, which samples the data without errors and without violating the setup hold times of the flip-flops. An algorithm carries out the evaluation in an evaluation unit 7, which is preferably a selection of this phase bit stream. The evaluation unit 7 accordingly controls a multi tiplexer 8, via which the selected phase bit stream is output to the data output as a data output signal data_o.

The only difference between the two architectures is the generation of the phase bit streams SAMPLE. In both variants, an unregulated delay chain is used. In the first architecture, a plurality of different phases of the data signal are derived from the data signal dataj, and in the second architecture a plurality of different phases of the clock signal are derived from the clock signal clk j, with which the phase bit streams are then obtained in each case. The phase position and frequency with which the receiving circuit operates are unregulated in relation to the data signal, so that data errors caused by jitter and wander have an effect on the phase bit streams. The evaluation unit 7 in FIG. 6 now only analyzes the phase bit streams in order to select a phase bit stream SAMPLE which corresponds to the data of the original, unsampled data signal dataj at the input of the circuit.

In principle, various algorithms are conceivable for the evaluation mechanism. An example implementation based on two finite state machines, so-called finite state machines, and the autocorrelation of the data signal or the correlation of the generated phase bit streams is explained in more detail below. Alternatively, an algorithm with additional redundancy and coding of the input data stream can recognize the correct phase bit stream during a decoding process. A variety of possible alternative algorithms are also conceivable.

FIG. 13 shows a block diagram of a first architecture of the scanning unit 6, in which several data signal phases are scanned with a common clock. The data signal dataj of the high-speed data input is generated by a chain of N delay elements 10 with a delay time of ΔT, «T _C | _k _ _f , ie {0, ..., N-1} and scanned between the individual delay elements 10 with a common clock. The signals thus derived from the original data signal dataj are referred to as phase bit streams SAMPLE. A subsequent circuit analyzes these phase bit streams and selects a phase bit stream that is as identical as possible to the data sequence of the input data stream dataj. This selection is dynamically adjusted with time variations of run times due to voltage changes or temperature changes. FIG. 13 shows an example of a delay chain which is built up from a sequence of buffers 10 with a delay time of Δη, ie {0 ... N-1}. Of course, other elements that have a delay time can also be used here (other gates, subcircuits, line sections). The delay times of the individual elements do not have to be known exactly, it is sufficient that all are approximately the same size. The exact delay time is variable within certain limits due to the semicustom design flow, the placement options, the process and production fluctuations, the supply voltage and the ambient temperature.

By manually placing the delay elements, the delay times of the line sections between the delay elements can be reduced. This can improve the quality of the implementation and also harmonize the delay times. Such manual support of the placement and wiring tools is generally possible in a modern semicustom design flow. In this case, depending on the result of the automatically running placement and wiring algorithms, this procedure can make a decisive contribution to the quality of the implementation in a semicustom design flow. Such a manual placement is not carried out for the classic application of a semicustom design flow, in which the design steps should run automatically as far as possible.

The delay elements should all have a delay time that is as comparable as possible, so that Δ «Δ applies to all i, j e {0 N-1}. The signals present between the delay elements 10 are referred to here as RAW (0) to RAW (N-1). As indicated in FIG. 13, these RAW signals are simultaneously sampled with the clock signal clk_f_i by means of storage elements 11 such as flip-flops or latches. The sampled signals are then designated SAMPLE (O) to SAMPLE (N-I) and are called phase bit streams. Due to the delay chain, the setup hold time violations and the signal disturbances such as jitter and wander, the phase bit streams are not identical, but are corrected with each other and with the data signal. Some are shifted by one or more bits against each other, others carry incorrect data.

For an example with N = 20, the RAW and SAMPLE signals are shown in FIG. 14 for a short period of time. SAMPLE (3) and SAMPLE (13) represent incorrect ones Phase bit streams, while correct data are present in SAMPLE (O) to SAMPLE (2), SAMPLE (4) to SAMPLE (12) and SAMPLE (14) to SAMPLE (19). The phase bit streams on which correct data are present can be divided into three groups, in which the data are identical in each case. Each of these groups represents a so-called data bit stream. The assignment of the phase bit streams to the data bit streams changes due to jitter and phase shift of the data signal. This observation is relevant for the evaluation or selection algorithms.

FIG. 15 shows a block diagram of a second architecture of the scanning unit 6, in which the data signal is oversampled by several phases of the clock signal. The central feature of an implementation according to this concept is the delay chain consisting of any delay elements 10, through which different phases of the clock signal clk_f_i are generated in an uncontrolled manner. The clock signal is passed through the delay chain. The clock signals picked up between the delay elements 10 are called clock phases CKP (0) to CKP (N-1). The data signal dataj is sampled with the various clock phases in order to generate the phase bit streams SAMPLE. In principle, these phase bit streams correspond to those of the first architecture shown in FIG. In order to achieve optimal extraction results, since the phase bit streams are obtained differently and therefore have different properties, slightly modified algorithms may also be used.

The implementation of the circuit architecture shown in FIG. 12 is explained in more detail below by way of example. FIG. 16 shows the architecture of the receiver circuit with the individual functional blocks. The serial bit stream of the received data is present as signal dataj. This data signal is passed through the scanning unit 6 with a chain of delay elements. By simultaneously scanning the signals between the individual delay elements, a (discrete) image of the temporal course of the data signal is created at fixed periodic times. The transmitted data sequence is extracted from the data signal on the basis of this illustration.

This extraction for a implemented implementation will now be explained in detail. The implementation consists of the modules shown in FIG. 16. The function of each individual module is specifically dealt with. The input signal is passed through the delay elements 10 and tapped in front of a delay element 10. A delay element 10 is implemented here as a simple buffer with a delay time of ΔT = i00ps of the standard cell library. In this example, these are active delay elements that contribute to signal processing. The circuit is shown in Figure 17. N = 20 buffers 10 are selected as delay elements. For example, the signal RAW (1) has passed exactly one delay element 10 more than the signal RAW (O), and the signal RAW (10) has, for example, gone through ten delay elements 10 more than the signal RAW (O). The course of these individual signals is shown in FIG. 18.

In this example, the bit sequence '101' is present at the data input for a period of approx. 818ns - approx. 820ns. At time 820ns there is a high voltage level at the input dataj, the signals RAW (4) to RAW (13) have a low voltage level and reflect the time-delayed '0'. The signals RAW (14) to RAW (19) again have a high signal level which represents the first T. The transmitted bit sequence '101' is thus visible through the delay chain in the data of the RAW signals at the same time. In this example, the total delay of the delay chain corresponds approximately to twice the period of the data clock signal.

The RAW data signals are all sampled at the same time. This happens for example at the frequency 1 GHz with the clock signal clk_f_i. The corresponding circuit is shown in Figure 19. Asynchronous sampling by flip-flops 11 takes place. The waveforms before and after the sampling are shown in FIG. The data signals SAMPLE which are synchronous with the clock signal clk_f_i are each referred to as a phase bit stream. The correct bit sequence '101' mentioned above can now be found in the signals SAMPLE (O) to SAMPLE (2), SAMPLE (4) to SAMPLE (12) and SAMPLE (14) to SAMPLE (19). Due to setup hold time violations, the phase bit streams SAMPLE (3) and SAMPLE (13) are faulty.

In this case, three consecutive bits of the data signal can be assigned to the phase bit streams. This results in three groups, each of which represents a so-called data bit stream. The boundaries between these three groups are shifted by fluctuations in the phase or frequency of the data signal or reference clock and by jitter. The membership of the phase bit streams to the groups therefore changes dynamically, and faulty phase bit streams occur. Faulty phase bit streams are phase bit streams whose data are faulty compared to the input data. Two adjacent data bit streams are thus shifted from each other by 1 bit or one clock period, but are otherwise identical, and contain exactly the data to be extracted. The correct data is now determined by switching between different phase bit streams, if the wander or jitter behavior changes, and thus following the data bit stream.

An evaluation circuit 7 for evaluating the phase bit streams and for determining a phase bit stream that best matches the input data sequence or has a maximum correlation measure is shown in FIG. This has a difference formation unit 12 for forming the difference between at least two phase bit streams, a detection unit 13 for determining the correlation measure and two selectors 15, 16 controlled by a control unit 14 for synchronizing each data bit stream. The individual units will be explained in more detail below.

By checking two adjacent phase bit streams for equality, it is determined between which phase bit streams a data change takes place on the input signal. The difference formation unit 12 in FIG. 22 and the signals in FIG. 23 show this comparison. To detect data changes or edges of the data signal, difference formation modules 120, e.g. simple logic gates, difference signals DI FF of the clocked phase bit streams SAMPLE are formed. Two adjacent phase bit streams are checked for equality. For example, DIFF (3) indicates whether SAMPLE (3) and SAMPLE (4) are identical. If SAMPLE (i) ≠ SAMPLE (i + 1) applies to any two adjacent phase bit streams SAMPLE (i), SAMPLE (i + 1), then DIFF (i) = 0 follows.

The circuit for implementing the algorithm for phase and data bit stream selection, which in this example is implemented as a state machine, is to be operated at a lower clock rate clk_s_s than the receiver clock rate clk_f_i (eg 1 GHz) (f = fast, s = slow). This means that all paths within this state machine are timing-uncritical. The clock signal clk_s_s can be generated from the signal clk_f_i by a simple clock divider. This clock divider is designated as module DivClock 9 in FIG. In order to evaluate the difference signals with this lower clock clk_s_s, signals must be derived therefrom which also change at a lower rate. For this purpose, a circuit is proposed as an example, which is referred to below as a zero trap. A zero trap is a memory circuit that remembers over a longer observation period (here clock period of clk_s_s) whether a difference between two neighboring phase bit streams has occurred. For this purpose, the data signal changes detected by the difference signals DIFF, which occur during a period of the clock clk_s_s, are accumulated. In this implementation example, the information collected in this way is available for each individual difference signal on each positive edge of the clock clk_s_s.

FIG. 24 shows an embodiment of such a zero trap 13. The function is shown in FIG. 25 in the form of a finite automaton. According to FIG. 24, the flip-flop 130, which is initially set to the value '1' synchronously by means of the reset signal res_trap, is reset within the observation period if the signal DIFF indicates a difference between two phase bit streams by the value '0'. The circuit thus notes the occurrence of one or more '0' of the difference signal as a sign that two adjacent phase bit streams are different. Since this behavior corresponds to the capture of a '0', the name Nullfalle was chosen to designate the circuit. Such a zero trap is used for each signal DIFF (i). The output signals of the zero traps with the lower data rate are referred to below as TRAP (i).

Alternatively, a 'trap' instead of a 'zero trap' could be defined and used, which notes the occurrence of one or more '1' of the difference signal as a sign that two adjacent phase bit streams are different if the signal DIFF by the value '1' indicates a difference between two phase bit streams.

A circuit for selecting the phase bit stream based on the TRAP signals will now be explained. For the simulation, two types of interference are taken into account for the input data signal, which are referred to here as jitter and wander. These disturbances are generated by the variations already described during the operation of the circuit, for example of temperature and voltage. Increasing jitter has an effect on the phase bit streams and TRAP signals in such a way that areas with temporarily faulty phase bit streams arise between the data bit streams and the TRAP signals temporarily have the signal level '0'. Such areas with changing signal levels of the TRAP signals due to the jitter can be seen in FIG.

Furthermore, longer-lasting disturbances can be expected, which can be caused by slow temperature fluctuations or slow voltage changes. In the simulations described, this was modeled so that the bit duration increased over several clock periods. Then it has decreased again. This shifts the boundaries between data bit streams. This limit can be seen in FIG. 26 through the jitter region. The increase and decrease in the bit duration over several clock periods results in the sinusoidal course of the jitter region in FIG. 26, since the change in the bit duration is assumed to be sinusoidal.

The task of the circuit unit for the selection of the phase bit stream is now to search for a path (a so-called trajectory) between these jitter areas and always to find a phase bit stream that supplies correct data with respect to the input data (data bit stream). This path is shown in Figure 26 as a solid line.

If, for example, the maximum phase difference between the receiver clock and the data signal is greater than the total delay time of the delay elements, an architecture consisting of two selectors 15, 16 makes sense, as shown in FIG. Each selector is implemented as a finite state machine and starts with the position of any phase bit stream. After a correct phase bit stream has been found, this choice is adjusted, if necessary, and the corresponding data bit stream is thus followed. The automaton then synchronized itself to this data bit stream. If the first selector 15 can no longer follow the data bit stream, the second selector 16 takes over.

The two selectors are named SelectorA and SelectorB. FIG. 27 shows a scenario in which the two selectors A and B adapt their selection of a phase bit stream to the data bit streams. The TRAP signals can be seen here, that is to say the difference signals of two adjacent phase bit streams accumulated over a clock period by means of zero traps. The jitter area of the data signal is therefore noticeable by the low signal levels on these TRAP signals. While the jitter range is quite large in FIG. 26, it claims a smaller one in FIG Area. Two different data signals are therefore considered. In both cases, the jitter range is not restricted to specific phase bit streams. By shifting the phase position of the data signal relative to the reference clock (wander), the position of the jitter area is shifted within the phase bit streams. This also shifts the positions of the data bit streams. This shift is recognized by the selectors, which adapt their selection of a phase bit stream accordingly. A selector synchronizes itself to a data bit stream and selects a phase bit stream.

In the example in FIG. 26, the amplitude of the wander is low, so that the selector whose selection is marked can follow the phase bit stream. If the frequencies of the two signals are slightly different (large wander), as is the case in the example in FIG. 27, a selector cannot follow the data bit stream to which it is synchronized for any length of time. The phase difference of the two signals becomes greater than the total delay time of the delay chain, and the data bit stream is no longer represented by phase bit streams, i.e. the data bit stream leaves the area represented by the phase bit streams. In order to be able to extract the data safely in this case, too, two identical selectors are implemented, which are synchronized to directly adjacent data bit streams. If the data bit stream of one of the selectors falls outside the range, the other takes over the data selection. Which selector makes the decision is shown in FIG. 27 in the signal cur_read_s.

If a selector is no longer synchronized to a data bit stream, it searches for a new data bit stream that is directly adjacent to the data bit stream to which the other selector has synchronized. Both selectors are implemented as identical synchronous finite automata. The state diagram of a selector is shown in FIG. 28. A state is defined as a pair z = (s; p) of control state (s) and control position (p). It applies

s e {SEEKNEXTUP; SEEKNEXTDOWN; SEEKUP; SEEKDOWN; SYNC; LOST}

and, since N = 20

p e {2 ... 17}.

The TRAP signals of the phase bit streams are available as input data. The machine starts with any control position in the control state s = SEEKUP. In each clock cycle, both the control position (hereinafter also simply referred to as position) and the control state are adapted. At the beginning, the position is increased until the condition for reliably finding a data bit stream is fulfilled. For these, the data of the four phase bit streams closest to the currently selected phase bit stream p were identical during the last period. This property is shown when the corresponding difference signals do not indicate a difference, that is to say that all four zero traps do not detect any 'O'-signal level of the difference signals. Under this condition, the automaton changes to the SYNC state and the data of the selected phase bit stream p are assumed to be correct. The condition that the four phase bit streams next to the current position p are identical is referred to below as (1; 1; 1; 1) _p . For a given control position p, the properties of the next four phase bit streams are recorded by the following 4-tuple by evaluating the difference signals:

(TRAP (p - 1); TRAP (p); TRAP (p + 1); TRAP (p + 2)) _p

The tuple (1; 1; 1; 1) _p, for example, means that the phase bit streams SAMPLE (p- 2), SAMPLE (pl), SAMPLE (p), SAMPLE (p + 1) and SAMPLE (p + 2) all during the last period of clk_s_i had identical data. The tuple (0; 1; 1; 1) _p indicates that different values have occurred in the phase bit streams SAMPLE (p-2) and SAMPLE (pl), ie they are in the jitter range.

Under the condition (1; 1; 1; 1) _p the machine is in the control state s = SYNC and the position remains constant. This condition is no longer necessarily fulfilled due to wandering or changes in jitter behavior. For example, if (0; 1; 1; 1) _p applies, the position is adjusted because the selected phase bit stream p is quite close to a potentially faulty phase bit stream and could get into the jitter range. In this situation, the automat remains in the state s = SYNC, but adjusts its position (p → p + 1). The selector evades the faulty phase bit streams, so to speak. This is shown in a detail in FIG. 29.

Using a correlation measure, the correlation vector (ml _p , mr _p ) of the selected phase bit stream p is calculated from the current values of this 4-tuple as follows: m / _p = ((TRAP (p) + (TRAP (p) ^* TRAP (p-1)) / 2

mr _p - ((TRAP (p + 1) + (TRAP (p + 1) ^* TRAP (p + 2)) / 2

This results in the following cases:

(1; 1; 1; 1) => m / _p = 1 and mr _p = 1

(1; 1; 1; 0) => m / _p = 1 and mr _p = 0.5

(1; 1; 0; x) => m / _p = 1 and mr _p = 0

(0; 1; 1; 1) => ml _p = 0.5 and mr _p = 1

(x; 0; 1; 1) => m / _p = 0 and mr _p = 1

(0; 1; 1; 0) => ml _p = 0.5 and mr _p = 0.5

(x; 0; 0; y) => ml _p = 0 and mr _p = 0

where x and y stand for any values 0 or 1.

The selection of a phase bit stream is adapted in accordance with this correlation vector. If ml _p <mr _p, the position is adjusted to the right (p → p + 1), if ml _p > mr _p , the position is adjusted to the left (p → p-1).

In this way, the selected phase bit stream is always kept in a safe area. The selector has synchronized to a data bit stream and is following it. But this only works if the jitter area and the wander are not too large.

This synchronization can be lost in three situations. This is the case if the wander is too strong, the jitter has too much of the bit time, or if the data bit stream to which the selector is synchronized runs out of the area represented by the phase bit streams. In each of these cases, the machine goes into the control state s = LOST and is reset by the logic that coordinates the two selectors (module coordSelectors 14 in FIG. 21). If the data bit stream runs out of the area represented by the phase bit streams, then it is guaranteed that the neighboring data bit stream is selected by the other selector becomes. In the other two cases, the data signal has become significantly worse, so that both selectors may have changed to the state s = LOST. In this case, bit errors occur and the entire interface is reset, since both selectors synchronize to a new data bit stream.

The two selectors are matched to one another, since they are always synchronized to directly adjacent data bit streams. Many variants are conceivable to achieve this state. In this example, the associated machines have the two states SEEKNEXTUP and SEEKNEXTDOWN. If one machine is synchronized to a data bit stream and the other machine is reset, it finds the directly adjacent data bit stream, which is represented, for example, by phase bit streams with a higher index by starting in the control state s = SEEKNEXTUP and taking over the control position of the synchronized machine. The control state is now increased with each clock until it is in the jitter area for the next data bit stream. This is determined by the condition (x ^ 0; 0; x ₂ ) _p , where Xx. and x _{2 represents} an arbitrary value ('0' or '1'), since here the correlation vector has the value (0.0). If this condition is met, the jitter area for the next data bit stream is recognized and the machine goes into the control state SEEKUP. The next phase bit stream that fulfills the condition (1; 1; 1; 1) _p is sought so that the selector can synchronize with the directly adjacent data bit stream and the automaton changes to the state s = SYNC. The state SEEKNEXTDOWN is required accordingly if the neighboring data bit stream, which is represented by phase bit streams with a lower index, is sought.

The task of the evaluation unit described above is to obtain the correct data stream from the phase bit streams. The data transmitted by the sender are considered correct. Since these are obviously not known, since they would otherwise not have to be transmitted, they are to be determined on the basis of other ^' characteristics. The interpretation of the received data signal and thus also of the phase bit streams determines the bit error rate (BER) in relation to the transmitted data. In the following, the described implementation of the evaluation unit is presented in a more general manner.

The evaluation unit is divided into two cycle areas. A first cycle with period T1 and synchronously with it a second cycle with T2 = n T1 are used. The factor n is selectable. First, phase bit streams that are in the jitter range must be recognized.

A mutual comparison of the phase bit streams determines which phase bit streams belong to which data bit streams. The phase bit streams near a transition between two adjacent data bit streams are in the jitter range. By comparing at least two selected phase bit streams, the boundaries between the data bit streams are recognized when a data signal change occurs, that is to say '10' or '01' is transmitted. For example, the comparison can be carried out with all pairs of directly adjacent phase bit streams. Adjacent phase bit streams whose values are different are in the jitter range. In each case two adjacent phase bit streams a and b are NXOR, linked together and thus determined whether their values are identical. A difference signal c is calculated in each case. Exactly when NXOR (a, b) = c = 0, a and b have different values, both phase bit streams a and b are in the jitter range.

Now the information from the previous step is accumulated with the aim of being able to make more reliable statements about the individual phase bit streams and to transmit the information into the clock area of the second clock. This step is optional, but is desirable in many cases. The results of the comparison from the first step are observed over time and weighted if necessary. In synchronism with the second clock, statements are made about the association of phase bit streams with data bit streams and phase bit streams in the jitter range. All phase bit streams that were assigned to the jitter area in a certain past time period of the previous step are assigned to the jitter area, all other phase bit streams each to the corresponding data bit streams. The data bit streams are limited by jitter areas. These assignments are made synchronously with the second bar. Each difference signal c from the previous step is observed with the help of a so-called zero trap over a clock period of the second clock. If c = 0 occurs during this time, the zero trap changes from the initial state '1' to the state '0'. All zero traps are evaluated and reset in synchronism with the second cycle. Phase bit streams that have an influence on a zero trap, which is in state '0' when evaluated, are assigned to the jitter range. The selection and adaptation of the selection of one or more phase bit streams then takes place on the basis of the information from the second step within the clock range of the second clock. In accordance with the statements from the second step, the phase bit stream with the lowest probability of error is selected and its data accepted as correct data received. A mechanism synchronizes itself to a data bit stream by using the information from the second step. The data of this data bit stream are assumed to be correct. If the data bit stream can no longer be followed, the mechanism synchronizes itself to another data bit stream, the data of which are now assumed to be correct. A finite state machine synchronizes itself to a data bit stream by recognizing the jitter areas and keeping its selection of a phase bit stream within this data bit stream at a sufficient distance from these jitter areas. For this purpose, the 2 n difference signals from the second step closest to the currently selected phase bit stream are considered, n on each side. If a jitter area is detected on one side, the automaton dodges its selection to the other side. If the selection can no longer be adjusted because, for example, there is no longer any phase bit stream available in the corresponding direction, the machine searches for a different data bit stream to which it synchronizes. So that no data is lost in the period of time that the automaton needs to find another data bit stream, there is a second identical automaton that is synchronized to another data bit stream and can take over the phase bit stream selection.

FIG. 30 shows an alternative embodiment for implementing the scanning unit. While in the embodiment shown in FIGS. 13, 15 and 17 the delay elements 10 are arranged in series and have essentially the same delay time, in this embodiment the delay elements 10 'are arranged in parallel and have different delay times. However, these delay times are all shorter than the clock period of the receiver clock signal dataj and each correspond to a multiple of the smallest delay time of one of the delay elements 10. This configuration can be used both in the constellation shown in FIG. 1) from the receiver clock signal clk_fj, or in the constellation shown in FIG. 15, that is to say to generate a plurality of phase-shifted data signal phases RAW (0..N-1) from the input data signal dataj. FIG. 31 shows a further embodiment for implementing the scanning unit by combining delay elements 10 ′ arranged in parallel with different delay times and delay elements 10 arranged in series with identical delay times. This allows the delay chain to be kept short while still covering a wide phase range. The combination of the parallel connection of the delay elements 10 'with the serially arranged delay elements 10 can be dynamically adapted if necessary. Such an adaptation, as indicated in FIG. 31, can be determined, for example, in the evaluation unit 7 by properties of the phase bit streams. This configuration can also be used to generate a plurality of receiver clock phases or data signal phases, but still avoids the problem of timing-critical paths. In addition to this example, delay elements arranged in series and in parallel can be combined in a wide variety of ways in order to generate the signals by means of which the phase bit streams are obtained.

FIG. 32 shows a block diagram of a further embodiment of the evaluation unit according to the invention, already shown in FIG. 21, details regarding the simultaneous extraction of several bits from the data signal being recognizable. A plurality of selection units (selectors) 15 'are provided in the evaluation unit, the selectors 15' being controlled by the evaluation control unit 14 '. Each selector 15 'then again has a trajectory shown in FIGS. 26 and 27. Depending on the data rate and receiver clock, several data bits can be extracted simultaneously per period of the receiver clock signal, thereby increasing the transmission rate or reducing the receiver clock rate.

The circuit arrangement according to the invention can be used as a subcircuit in an integrated circuit for the transmission of digital data (e.g. with a clock rate of over 500 MHz). The main idea is based on multi-phase oversampling of the data into different phase bit streams and subsequent evaluation, in particular by selecting the correct phase bit stream. This circuit proposal represents another solution to the known data transmission problem at high data rates. The advantage of this circuit proposal is a simpler implementation on the IC, since a semi-custom design flow can be used if desired.

Claims

Expectations

1. Circuit arrangement for extracting data from a serial data signal for high bit rate transmission of data between or within integrated circuits

- An evaluation unit for determining a data sequence that best matches the data of the data signal by evaluating correlation properties of the generated synchronous phase bit streams and for outputting the data sequence.

2. Circuit arrangement according to claim 1, characterized in that the sampling unit is designed for multiple sampling of the data signal by means of a single receiver clock signal supplied to the sampling unit.

3. Circuit arrangement according to claim 1, characterized in that the sampling unit is designed for multiple parallel sampling of different phases of the data signal within a clock period of the receiver clock signal for generating the phase bit streams.

4. Circuit arrangement according to claim 3, characterized in that the scanning unit has a plurality of delay elements arranged in series with an essentially identical delay time which is less than the clock period of the receiver clock signal, and / or a plurality of delay elements arranged in parallel with different delay times which are less than the clock period of the receiver clock signal for generating a plurality of phase-shifted data signal phases between the delay elements from the received data signal and means for parallel sampling of the phase-shifted data signals with the receiver clock.

5. Circuit arrangement according to claim 1, characterized in that the sampling unit is designed for multiple phase-shifted sampling of the data signal within a clock period of the receiver clock signal for generating the phase bit streams.

6. Circuit arrangement according to claim 5, characterized in that the scanning unit has a plurality of delay elements arranged in series with an essentially identical delay time which is less than the clock period of the receiver clock signal, and / or a plurality of delay elements arranged in parallel with different delay times which are less than the clock period of the receiver clock signal, for generating a plurality of phase-shifted clock phases between the delay elements from the receiver clock signal and means for phase-shifted sampling of the received data signal with the clock phases.

7. Circuit arrangement according to claim 4 or 6, characterized in that the delay elements are unregulated, in particular without means for setting the delay time, are designed.

,

8. Circuit arrangement according to one of the preceding claims, characterized in that the evaluation unit is designed to determine the data sequence from at least two phase bit streams, in particular two adjacent phase bit streams.

9. Circuit arrangement according to claim 8, characterized in that the evaluation unit has at least one selection unit for selecting a phase bit stream which best matches the data of the received data signal by evaluating the correlation properties, in particular by comparing the generated phase bit streams.

10. The circuit arrangement as claimed in claim 9, characterized in that the evaluation unit has a plurality of selection units and an evaluation control unit for coordinating the selection units and for determining the extracted data sequence from the phase bit streams.

1 1. Circuit arrangement according to one of claims 7 to 10, characterized in that the at least one selection unit has a difference formation unit for forming at least one difference signal between at least two phase bit streams for checking the correlation of the phase bit streams.

12. Circuit arrangement according to claim 11, characterized in that the difference formation unit is designed to form difference signals between two adjacent phase bit streams.

13. Circuit arrangement according to one of the preceding claims, characterized in that the at least one selection unit has a detection unit for determining the correlation properties over a predetermined period of time and for generating a correlation signal.

14. Circuit arrangement according to one of claims 11 to 13, characterized in that the at least one selection unit is designed to adapt the selection of a phase bit stream by evaluating the correlation signals or the correlation properties at regular time intervals.

15. Circuit arrangement according to claim 10, characterized in that the evaluation control unit is designed to coordinate the selection units and to seamlessly extract the data sequence by evaluating at least one phase bit stream selected by a selection unit.

16. Circuit arrangement according to one of the preceding claims, characterized in that the circuit arrangement is designed by means of cells from a standard cell library of a semicustom design flow.

17. Circuit arrangement according to one of the preceding claims, characterized in that the circuit arrangement is implemented by means of a semicustom design flow.

18. Circuit arrangement according to claim 16, characterized in that the placement of cells of the standard cell library, preferably elements of the scanning unit, in particular delay elements, is designed by manual influencing.

19. Circuit arrangement according to claim 7, characterized in that the number of delay elements and / or the delay times of the delay elements is selected such that the sum of the delay times of all delay elements is at least as large as the clock period of the data signal.

20. A method for extracting data from a serial data signal for high-bit-rate transmission of data between or within integrated circuits, comprising the steps:

multiple unregulated sampling of the data signal within one clock period of a receiver clock signal to generate a plurality of phase bit streams synchronous with the receiver clock,

- Determination of a data sequence that best matches the data of the data signal by evaluating correlation properties of the generated synchronous phase bit streams and

- Output of the data sequence.