WO2004044733A3 - State engine for data processor - Google Patents

State engine for data processor Download PDF

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Publication number
WO2004044733A3
WO2004044733A3 PCT/GB2003/004867 GB0304867W WO2004044733A3 WO 2004044733 A3 WO2004044733 A3 WO 2004044733A3 GB 0304867 W GB0304867 W GB 0304867W WO 2004044733 A3 WO2004044733 A3 WO 2004044733A3
Authority
WO
WIPO (PCT)
Prior art keywords
state
operations
command
cycles
local memory
Prior art date
Application number
PCT/GB2003/004867
Other languages
French (fr)
Other versions
WO2004044733A2 (en
Inventor
Anthony Spencer
Original Assignee
Clearspeed Technology Plc
Anthony Spencer
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Clearspeed Technology Plc, Anthony Spencer filed Critical Clearspeed Technology Plc
Priority to AU2003283545A priority Critical patent/AU2003283545A1/en
Priority to GB0509997A priority patent/GB2411271B/en
Priority to US10/534,430 priority patent/US7882312B2/en
Publication of WO2004044733A2 publication Critical patent/WO2004044733A2/en
Publication of WO2004044733A3 publication Critical patent/WO2004044733A3/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/32—Flow control; Congestion control by discarding or delaying data units, e.g. packets or frames
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/466—Transaction processing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/24—Traffic characterised by specific attributes, e.g. priority or QoS
    • H04L47/2441—Traffic characterised by specific attributes, e.g. priority or QoS relying on flow classification, e.g. using integrated services [IntServ]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/50—Queue scheduling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/50—Queue scheduling
    • H04L47/56—Queue scheduling implementing delay-aware scheduling
    • H04L47/562—Attaching a time tag to queues
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/50—Queue scheduling
    • H04L47/60—Queue scheduling implementing hierarchical scheduling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/50—Queue scheduling
    • H04L47/62—Queue scheduling characterised by scheduling criteria
    • H04L47/6215—Individual queue per QOS, rate or priority
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/50—Queue scheduling
    • H04L47/62—Queue scheduling characterised by scheduling criteria
    • H04L47/624—Altering the ordering of packets in an individual queue
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9042—Separate storage for different parts of the packet, e.g. header and payload

Abstract

Coherent accesses and updates to state shared by parallel processors, such as SIMD array processors, is made possible by the use of state elements having local memory storing the state and permitting serialisation of accesses. Operations on single or multiple items of state are perfumed by a fixed/hardwired set of operations but they can be programmable by sending command and data to control operations. Individual state elements comprise the local memory, an arithmetic unit, and command and control logic. Multiple state elements are pipelined in state cells which can, in turn, be organised into state arrays and state engines effecting complete control over shared state access. A read/modify/write operation can be performed in only two cycles and a complete command in only three to five cycles.
PCT/GB2003/004867 2002-11-11 2003-11-11 State engine for data processor WO2004044733A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
AU2003283545A AU2003283545A1 (en) 2002-11-11 2003-11-11 State engine for data processor
GB0509997A GB2411271B (en) 2002-11-11 2003-11-11 State engine for data processor
US10/534,430 US7882312B2 (en) 2002-11-11 2003-11-11 State engine for data processor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GBGB0226249.1A GB0226249D0 (en) 2002-11-11 2002-11-11 Traffic handling system
GB0226249.1 2002-11-11

Publications (2)

Publication Number Publication Date
WO2004044733A2 WO2004044733A2 (en) 2004-05-27
WO2004044733A3 true WO2004044733A3 (en) 2005-03-31

Family

ID=9947583

Family Applications (4)

Application Number Title Priority Date Filing Date
PCT/GB2003/004854 WO2004045160A2 (en) 2002-11-11 2003-11-11 Data packet handling in computer or communication systems
PCT/GB2003/004867 WO2004044733A2 (en) 2002-11-11 2003-11-11 State engine for data processor
PCT/GB2003/004866 WO2004045161A1 (en) 2002-11-11 2003-11-11 Packet storage system for traffic handling
PCT/GB2003/004893 WO2004045162A2 (en) 2002-11-11 2003-11-11 Traffic management architecture

Family Applications Before (1)

Application Number Title Priority Date Filing Date
PCT/GB2003/004854 WO2004045160A2 (en) 2002-11-11 2003-11-11 Data packet handling in computer or communication systems

Family Applications After (2)

Application Number Title Priority Date Filing Date
PCT/GB2003/004866 WO2004045161A1 (en) 2002-11-11 2003-11-11 Packet storage system for traffic handling
PCT/GB2003/004893 WO2004045162A2 (en) 2002-11-11 2003-11-11 Traffic management architecture

Country Status (5)

Country Link
US (5) US7843951B2 (en)
CN (4) CN100557594C (en)
AU (4) AU2003283544A1 (en)
GB (5) GB0226249D0 (en)
WO (4) WO2004045160A2 (en)

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Publication number Publication date
CN1736069A (en) 2006-02-15
GB2412537B (en) 2006-02-01
WO2004045161A1 (en) 2004-05-27
AU2003283545A1 (en) 2004-06-03
GB2412035B (en) 2006-12-20
AU2003283559A1 (en) 2004-06-03
CN1736068A (en) 2006-02-15
AU2003283545A8 (en) 2004-06-03
WO2004045162A3 (en) 2004-09-16
US8472457B2 (en) 2013-06-25
US7882312B2 (en) 2011-02-01
WO2004044733A2 (en) 2004-05-27
GB2411271B (en) 2006-07-26
GB2411271A (en) 2005-08-24
US20050246452A1 (en) 2005-11-03
US20110069716A1 (en) 2011-03-24
WO2004045160A8 (en) 2005-04-14
WO2004045160A2 (en) 2004-05-27
GB2413031A (en) 2005-10-12
US7843951B2 (en) 2010-11-30
CN1736069B (en) 2012-07-04
AU2003283544A1 (en) 2004-06-03
CN100557594C (en) 2009-11-04
GB2412035A (en) 2005-09-14
GB2413031B (en) 2006-03-15
WO2004045162A2 (en) 2004-05-27
GB0511588D0 (en) 2005-07-13
US20050265368A1 (en) 2005-12-01
GB2412537A (en) 2005-09-28
US7522605B2 (en) 2009-04-21
WO2004045160A3 (en) 2004-12-02
CN1736068B (en) 2012-02-29
GB0509997D0 (en) 2005-06-22
GB0226249D0 (en) 2002-12-18
CN1736066B (en) 2011-10-05
CN1736066A (en) 2006-02-15
AU2003283539A1 (en) 2004-06-03
US20050257025A1 (en) 2005-11-17
US20050243829A1 (en) 2005-11-03
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