WO2004057757A1 - オーディオアンプ - Google Patents
オーディオアンプ Download PDFInfo
- Publication number
- WO2004057757A1 WO2004057757A1 PCT/JP2003/015916 JP0315916W WO2004057757A1 WO 2004057757 A1 WO2004057757 A1 WO 2004057757A1 JP 0315916 W JP0315916 W JP 0315916W WO 2004057757 A1 WO2004057757 A1 WO 2004057757A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- signal
- circuit
- digital audio
- muting
- supplied
- Prior art date
Links
- 230000005236 sound signal Effects 0.000 claims abstract description 30
- 238000005070 sampling Methods 0.000 claims abstract description 24
- 238000001514 detection method Methods 0.000 claims description 19
- 230000001360 synchronised effect Effects 0.000 claims description 8
- 239000010752 BS 2869 Class D Substances 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000006243 chemical reaction Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 238000013139 quantization Methods 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/217—Class D power amplifiers; Switching amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/217—Class D power amplifiers; Switching amplifiers
- H03F3/2175—Class D power amplifiers; Switching amplifiers using analogue-digital or digital-analogue conversion
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/181—Low frequency amplifiers, e.g. audio preamplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers without distortion of the input signal
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/34—Muting amplifier when no signal is present or when only weak signals are present, or caused by the presence of noise signals, e.g. squelch systems
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M3/324—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement
- H03M3/346—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by suppressing active signals at predetermined times, e.g. muting, using non-overlapping clock phases
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/331—Sigma delta modulation being used in an amplifying circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M3/324—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement
- H03M3/326—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by averaging out the errors
- H03M3/328—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by averaging out the errors using dither
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/50—Digital/analogue converters using delta-sigma modulation as an intermediate step
- H03M3/502—Details of the final digital/analogue conversion following the digital delta-sigma modulation
- H03M3/506—Details of the final digital/analogue conversion following the digital delta-sigma modulation the final digital/analogue converter being constituted by a pulse width modulator
Definitions
- the present invention relates to an audio amplifier.
- FIG. 3 shows an example of such a digital audio amplifier.
- a digital audio signal S 11 is supplied from an input terminal 11 to an oversampling circuit 2, and the digital frequency of the digital audio signal is, for example, eight times that of a sampling frequency of eight.
- the digital signal S12 is oversampled to the signal S12, and the digital signal S12 is supplied to the ⁇ modulation circuit 14 through a variable attent for adjusting the volume and a tenator circuit 13 to reduce the number of bits. It is requantized into a digital signal S14.
- the digital signal S14 is supplied to a PWM modulation circuit 15 and converted into a PWM signal S15, and the PWM signal S15 is supplied to a power amplifier 16 operating in class D.
- This power amplifier 16 is a switching circuit for amplifying power by switching the power supply according to the PWM signal S15, and a smoothing output of the switching circuit. Outputs analog audio signal after DZA conversion and power amplification It consists of a low-nos filter and force. The audio signal power-amplified by the power amplifier 16 is supplied to the speaker 30 via the output terminal 17.
- a volume control signal S VOL is formed, and this signal S VOL is supplied to the variable attenuator circuit 13 as the control signal. Therefore, when the volume adjustment switch is operated, the attenuation level of the variable attenuator circuit 13 changes, and the volume of the reproduced sound output from the speed 30 is changed.
- the ⁇ ⁇ modulation circuit 14 has a quantization error feed-knock loop, and is supplied from the variable attenuator circuit 13 to the ⁇ modulation circuit 14. Even when the content of the digital signal S 12 is zero, the ⁇ modulation circuit 14 outputs a digital signal S 14 having a certain value, and the digital signal S 14 is output at a specific frequency. The sound is output as a noise sound.
- a dither signal forming circuit 18 forms a very small level dither signal SDI, and this dither signal SDI is supplied to a ⁇ modulation circuit 14 and is converted into a digital signal for requantization. Superimposed on S12. Therefore, even when the content of the digital signal S12 output from the variable attenuator circuit 13 is zero, the actual content of the input signal of the ⁇ modulation circuit 15 does not become zero. Output of the noise sound is suppressed.
- the digital signal S 11 supplied to the input terminal 11 is supplied to the asynchronous detection circuit 19, and the disturbance of the synchronization of the digital signal S 11 is detected.
- the detection signal SDET is supplied to the circuits 12 to 14 as a muting signal, and when the synchronization of the digital signal S11 is disturbed, the signals S12 and S14 are output. Is set to zero, and as a result, the reproduced sound output from the speaker 30 is muted.
- the above is an example of an audio amplifier in which the final-stage power amplifier 17 is constituted by a class D amplifier (for example, see Japanese Patent Application Laid-Open No. 2002-158543).
- the ⁇ modulation circuit 14 At the same time as the digital signal S12 is muted, the dither signal SDI is also muted. Therefore, during muting, the dither signal SDI is suddenly cut off, and a noise signal is generated due to the sudden cutoff, which is a noise sound from the speaker 30. Will be output.
- the dither signal SDI is at a very low level, but the presence or absence of the dither signal SDI can be perceived as a difference in noise and level. For this reason, when muting is applied, the dither signal SDI is muted and the noise level changes. However, when the content of the input digital signal S11 is zero (or minute level). In such a case, the change in the noise level is perceived, causing a sense of incongruity. This invention seeks to solve such a problem. Disclosure of the invention
- the first digital audio signal is synchronized with the second clock by a first clock synchronized with the first digital audio signal and a second clock having a preset frequency.
- a ⁇ modulation circuit for requantizing the second digital audio signal into a third digital audio signal having a smaller number of bits
- a PWM modulation circuit for converting the third digital audio signal into a PWM signal
- a class D power amplifier to which the PWM signal output from the PWM modulation circuit is supplied;
- a a dither signal forming circuit that supplies a dither signal to the modulation circuit and superimposes the dither signal on the third digital audio signal
- the dither signal is continuously supplied to the ⁇ modulation circuit, and the digital audio signal having this dither signal is converted into a PWM signal to be a class D signal. Supplied to one amplifier.
- FIG. 1 is a system diagram showing one embodiment of the present invention.
- FIG. 2 is a diagram for explaining the present invention.
- FIG. 3 is a system diagram for explaining the present invention. BEST MODE FOR CARRYING OUT THE INVENTION
- FIG. 1 shows an example of a digital audio amplifier 10 according to the present invention.
- a digital audio signal S 11 is supplied from an input terminal 11 to an oversampling circuit 12. Further, the digital signal S 11 of the input terminal 11 is supplied to the PLL 21 to be synchronized with the digital signal S 11, and that the clock S PLL having a frequency n times the sampling frequency is used. It is formed and supplied to the oversampling circuit 12 as a clock for the oversampling.
- the oversampling magnification n is set to, for example, a value as shown in FIG. 2 corresponding to the sampling frequency of the digital signal S11.
- the digital signal S 11 supplied thereto is synchronized with the signal S 11, and has a digital signal S 12 of n times the sampling frequency. Oversampled.
- the digital signal S12 is supplied to the sample converter circuit 23 as a conversion input. Further, the clock SPLL power S from the PLL 21 is supplied to the conversion rate converter 23 as a pin on the conversion input side.
- the converted digital signal S23 is supplied to a variable attenuator circuit 13 for adjusting the volume, and a control signal SVOL from a system controller (not shown) is supplied.
- the digital signal S12 whose level has been controlled is supplied to the ⁇ modulation circuit 14 and requantized into a digital signal S14 having a reduced number of bits.
- a dither signal S DI of a very small level is formed in the dither signal forming circuit 18.
- the dither signal SDI is supplied to the digital signal S supplied to the ⁇ modulation circuit 14. Superimposed on 23.
- the digital signal S14 requantized by the ⁇ modulation circuit 14 is supplied to a PWM modulation circuit 15 and converted into a PWM signal S15, and the PWM signal S15 is converted. 15 is supplied to the power amplifier 16 of class D operation and power amplified, and the amplified output is supplied to the speaker 30 through the output terminal 17.
- the clock SGEN from the forming circuit 22 and the GEN force S are supplied to the circuits 13 to 15 and 18 as those clocks. I Therefore, the output side circuits 13 to 15 and 18 of the sample converter circuit 23 are operating in synchronization with the clock SGEN.
- the digital signal S11 supplied to the input terminal 11 is supplied to the asynchronous detection circuit 19, and the sampling frequency of the input digital signal S11 is equal to the sampling frequency of the input digital signal S11 from the PLL 21.
- a synchronized clock is taken out, and this clock is supplied to the asynchronous detection circuit 19, and the synchronous disturbance of the digital signal S11 supplied to the input terminal 11 is detected.
- the detection signal S DET is supplied as a muting signal to the input side of the oversampling circuit 12, the input side of the sampling converter circuit 23, and the variable attenuator circuit 13, and is supplied as a digital signal.
- the content of the signal S12 is set to zero, and the operation of the input side of the sampling converter circuit 23 is stopped.
- the digital audio signal S11 supplied to the input terminal 11 has a sampling frequency of 384k by the sampling converter circuit 23 regardless of the sampling frequency.
- the sample signal is converted into a digital signal of 1 Hz, then converted into a PWM signal S 15, amplified in power, and supplied to the speaker 30.
- the synchronization of the digital signal S11 is temporarily stopped.
- this disturbance of synchronization is detected by the asynchronous detection circuit 19, and the over-sampling circuit 12 and the sampling circuit are detected by the detection signal SDET.
- the operation of the input side of the ring converter circuit 23 is stopped. Therefore, during the period of the detection signal SDET, the digital signal S12 is cut off.
- the output side is still supplied with the clock S GEN power S Since the operation is continued, the digital signal S23 is continuously output from the sampling converter circuit 23. However, at this time, the operation of the input side of the sample converter circuit 23 is stopped, and the detection signal S DET is also supplied to the variable attenuator circuit 13. The content of the digital signal S23 output from the attenuator circuit 13 is zero.
- the ⁇ modulation circuit 14 Since such a digital signal S23 is supplied to the ⁇ modulation circuit 14 and the detection signal S DET is not supplied to the ⁇ modulation circuit 14, During the period of the detection signal S DET, the ⁇ ⁇ modulation circuit 14 outputs a digital signal S 14 having zero content, and the digital signal S 14 is supplied to the PWM modulation circuit 15. Therefore, during the period of the detection signal S DET, the input audio signal S 11 is muted. That is, the period of the detection signal SDET is a matching period.
- the muting is performed in the digital audio amplifier shown in FIG. 1, but also during the muting period, the dither signal SDI is supplied to the ⁇ modulation circuit 14. Therefore, even if the content of the digital signal S23 supplied thereto is zero, the signal component that becomes a noise sound of a specific frequency can be output from the ⁇ modulation circuit 14. Absent. Also, the dither signal SDI is supplied to the ⁇ modulation circuit 14 also during the muting period, so that when muting is not applied and when it is applied, the muting is performed. And the noise level. Therefore, when the content of the input digital signal S11 is zero (or very small level), even if muting is applied, a change in the noise level is perceived, causing a sense of incongruity. There is nothing.
- the dither signal SDI is maintained when the muting is started when the muting is not performed, and when the muting is released from the muted state. Therefore, no noise signal is generated, and no noise is output from the speaker 30.
- the noise level change is perceived to cause a sense of incongruity even if the muting is applied. Absent. Also, when muting is applied from a state where muting is not applied, and when muting is released from the muting state, no noise signal is generated. Also, there is no noise output from the speed.
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP03778853.6A EP1575162B1 (en) | 2002-12-20 | 2003-12-12 | Audio amplifier |
US10/536,999 US7209002B2 (en) | 2002-12-20 | 2003-12-12 | Audio amplifier |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002-369703 | 2002-12-20 | ||
JP2002369703A JP4078543B2 (ja) | 2002-12-20 | 2002-12-20 | オーディオアンプ |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2004057757A1 true WO2004057757A1 (ja) | 2004-07-08 |
Family
ID=32677148
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2003/015916 WO2004057757A1 (ja) | 2002-12-20 | 2003-12-12 | オーディオアンプ |
Country Status (6)
Country | Link |
---|---|
US (1) | US7209002B2 (ja) |
EP (1) | EP1575162B1 (ja) |
JP (1) | JP4078543B2 (ja) |
KR (1) | KR101015724B1 (ja) |
CN (1) | CN100459423C (ja) |
WO (1) | WO2004057757A1 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1622258A3 (en) * | 2004-07-30 | 2006-03-22 | Sony Corporation | Power amplifier apparatus and dc component removing method |
CN100417017C (zh) * | 2005-02-17 | 2008-09-03 | 普诚科技股份有限公司 | D类音频放大器的异步式桥接负载 |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2006054545A (ja) * | 2004-08-10 | 2006-02-23 | Matsushita Electric Ind Co Ltd | ディジタルゲイン制御装置とそれを用いたオーディオ信号電力増幅装置、並びにそれらの方法 |
JP4704887B2 (ja) * | 2005-10-28 | 2011-06-22 | Okiセミコンダクタ株式会社 | 増幅回路 |
JP4513021B2 (ja) * | 2005-12-28 | 2010-07-28 | ソニー株式会社 | ディジタルアンプ装置及びディジタルアンプ装置のミュート方法 |
JP4513022B2 (ja) * | 2005-12-28 | 2010-07-28 | ソニー株式会社 | ディジタルアンプ装置及びディジタルアンプ装置のリセット方法 |
JP4311437B2 (ja) * | 2006-11-15 | 2009-08-12 | ヤマハ株式会社 | D級増幅装置 |
TWI329983B (en) * | 2006-11-27 | 2010-09-01 | Realtek Semiconductor Corp | Methods for controlling power stage of power amplifier and related apparatuses |
JP2008187375A (ja) * | 2007-01-29 | 2008-08-14 | Rohm Co Ltd | アナログデジタル変換器およびそれを用いた電子機器 |
US8160309B1 (en) | 2007-12-21 | 2012-04-17 | Csr Technology Inc. | Method, apparatus, and system for object recognition and classification |
CN101527547B (zh) * | 2008-03-07 | 2015-03-04 | 瑞昱半导体股份有限公司 | 控制功率放大器的功率输出级的方法及相关装置 |
JP2010045726A (ja) * | 2008-08-18 | 2010-02-25 | Sharp Corp | 信号増幅装置及び信号処理方法 |
KR101069234B1 (ko) | 2008-10-14 | 2011-10-04 | (주)제이디에이테크놀로지 | 무 필터 d 급 오디오 증폭기 |
KR101573343B1 (ko) | 2009-06-16 | 2015-12-02 | 삼성전자주식회사 | 플립플롭 회로 및 이를 구비하는 컴퓨터 시스템 |
US8306106B2 (en) | 2010-04-27 | 2012-11-06 | Equiphon, Inc. | Multi-edge pulse width modulator with non-stationary residue assignment |
JP5017428B2 (ja) * | 2010-06-30 | 2012-09-05 | 株式会社東芝 | 変調信号処理装置及び変調信号処理方法 |
CN104168524A (zh) * | 2013-05-17 | 2014-11-26 | 无锡华润矽科微电子有限公司 | 数字功放设备的控制电路及其控制方法 |
CN103763591A (zh) * | 2014-01-10 | 2014-04-30 | 广东雷洋电子科技有限公司 | 一种大功率视频播放器 |
CN104104342B (zh) * | 2014-06-27 | 2017-05-24 | 同济大学 | 一种二次量化器、采用其的d类放大器以及音频设备 |
CN109756193B (zh) * | 2017-11-01 | 2023-04-28 | 华润微集成电路(无锡)有限公司 | 使用扩谱调制进行pwm波调制的d类数字音频功放系统 |
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JPH04115722A (ja) * | 1990-09-05 | 1992-04-16 | Yamaha Corp | Da変換装置 |
JP2001237708A (ja) * | 2000-02-24 | 2001-08-31 | Alpine Electronics Inc | データ処理方式 |
JP2002158550A (ja) * | 2000-11-17 | 2002-05-31 | Sony Corp | デジタルパワーアンプ |
JP2002158543A (ja) * | 2000-11-17 | 2002-05-31 | Sony Corp | デジタルパワーアンプ |
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US5672998A (en) * | 1995-08-09 | 1997-09-30 | Harris Corporation | Class D amplifier and method |
JP3304750B2 (ja) * | 1996-03-27 | 2002-07-22 | 松下電器産業株式会社 | ロスレス符号装置とロスレス記録媒体とロスレス復号装置とロスレス符号復号装置 |
US5777512A (en) | 1996-06-20 | 1998-07-07 | Tripath Technology, Inc. | Method and apparatus for oversampled, noise-shaping, mixed-signal processing |
US6014055A (en) | 1998-02-06 | 2000-01-11 | Intersil Corporation | Class D amplifier with reduced clock requirement and related methods |
DE69931637T2 (de) * | 1998-07-24 | 2007-05-16 | Texas Instruments Denmark A/S | Verfahren zur reduzierung von nulldurchgangsverzerrungen und rauschen in einem verstärker, verstärker sowie anwendung dieses verfahrens und verstärkers |
WO2000070752A1 (en) * | 1999-05-18 | 2000-11-23 | Lucent Technologies Inc. | Digital amplifier |
JP2002158549A (ja) * | 2000-11-17 | 2002-05-31 | Sony Corp | デジタルパワーアンプ装置 |
JP4115722B2 (ja) * | 2002-03-15 | 2008-07-09 | Hoya株式会社 | 情報記録媒体用ガラス基板の製造方法 |
EP1469594A1 (en) * | 2003-04-17 | 2004-10-20 | Dialog Semiconductor GmbH | Multi level Class-D amplifier by means of 2 physical layers |
-
2002
- 2002-12-20 JP JP2002369703A patent/JP4078543B2/ja not_active Expired - Fee Related
-
2003
- 2003-12-12 WO PCT/JP2003/015916 patent/WO2004057757A1/ja active Application Filing
- 2003-12-12 US US10/536,999 patent/US7209002B2/en not_active Expired - Lifetime
- 2003-12-12 KR KR1020057011200A patent/KR101015724B1/ko not_active IP Right Cessation
- 2003-12-12 CN CNB2003801057153A patent/CN100459423C/zh not_active Expired - Fee Related
- 2003-12-12 EP EP03778853.6A patent/EP1575162B1/en not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04115722A (ja) * | 1990-09-05 | 1992-04-16 | Yamaha Corp | Da変換装置 |
JP2001237708A (ja) * | 2000-02-24 | 2001-08-31 | Alpine Electronics Inc | データ処理方式 |
JP2002158550A (ja) * | 2000-11-17 | 2002-05-31 | Sony Corp | デジタルパワーアンプ |
JP2002158543A (ja) * | 2000-11-17 | 2002-05-31 | Sony Corp | デジタルパワーアンプ |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1622258A3 (en) * | 2004-07-30 | 2006-03-22 | Sony Corporation | Power amplifier apparatus and dc component removing method |
US7315209B2 (en) | 2004-07-30 | 2008-01-01 | Sony Corporation | Power amplifier apparatus and DC component removing method |
CN100417017C (zh) * | 2005-02-17 | 2008-09-03 | 普诚科技股份有限公司 | D类音频放大器的异步式桥接负载 |
Also Published As
Publication number | Publication date |
---|---|
KR20050089158A (ko) | 2005-09-07 |
EP1575162A4 (en) | 2006-09-06 |
CN1723616A (zh) | 2006-01-18 |
US20050285670A1 (en) | 2005-12-29 |
EP1575162A1 (en) | 2005-09-14 |
KR101015724B1 (ko) | 2011-02-22 |
EP1575162B1 (en) | 2018-07-11 |
US7209002B2 (en) | 2007-04-24 |
JP4078543B2 (ja) | 2008-04-23 |
JP2004201185A (ja) | 2004-07-15 |
CN100459423C (zh) | 2009-02-04 |
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