WO2004059737B1 - Multi-level memory cell with lateral floating spacers - Google Patents

Multi-level memory cell with lateral floating spacers

Info

Publication number
WO2004059737B1
WO2004059737B1 PCT/US2003/040205 US0340205W WO2004059737B1 WO 2004059737 B1 WO2004059737 B1 WO 2004059737B1 US 0340205 W US0340205 W US 0340205W WO 2004059737 B1 WO2004059737 B1 WO 2004059737B1
Authority
WO
WIPO (PCT)
Prior art keywords
spacers
source
drain regions
polysilicon gate
insulative layer
Prior art date
Application number
PCT/US2003/040205
Other languages
French (fr)
Other versions
WO2004059737A1 (en
Inventor
Bohumil Lojek
Original Assignee
Atmel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corp filed Critical Atmel Corp
Priority to CA002508810A priority Critical patent/CA2508810A1/en
Priority to AU2003300994A priority patent/AU2003300994A1/en
Priority to EP03814101A priority patent/EP1576668A4/en
Priority to JP2004563670A priority patent/JP2006511940A/en
Publication of WO2004059737A1 publication Critical patent/WO2004059737A1/en
Publication of WO2004059737B1 publication Critical patent/WO2004059737B1/en
Priority to NO20053531A priority patent/NO20053531L/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42332—Gate electrodes for transistors with a floating gate with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7887—Programmable transistors with more than two possible different levels of programmation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

A multi-level non-volatile memory transistor (33) is formed in a semiconductor substrate (57). A conductive polysilicon control gate (51; 62) having opposed sidewalls is insulatively spaced (56) just above the substrate. Conductive polysilicon spacers (53, 55;91, 93) are separated from the opposed sidewalls by thin tunnel oxide (59; 74). Source and drain implants (61, 63; 101, 103) are beneath or slightly outboard of the spacers. Insulative material (104, 109) is placed over the structure with a hole (125) cut above the control gate for contact by a gate electrode (127) connected to, or part of, a conductive word line. Auxiliary low voltage transistors (23-26) which may be made at the same time as the formation of the memory transistor apply opposite phase clock pulses((~1, p2) to source and drain electrodes so that first one side of the memory transistor may be written to, or read, then t he other side.

Claims

AMENDED CLAIMS[Received by the International Bureau on 29 June 2004 (29.06.04) ; original claims 1, 3 and 4 amended ; claims 2 and 5 cancelled ; remaining claims unchanged]
1. A multi-level non-volatile memory transistor with lateral charge storage areas, comprising: a semiconductor substrate having an active region with spaced apart source and drain regions in the active region; a first insulative layer disposed over the substrate between the source and drain regions; a polysilicon gate disposed over the first insulative layer and having opposed sidewalls; a pair of polysilicon upright spacers located on opposite sides of the polysilicon gate adjacent to the sidewalls but separated therefrom and from the substrate by tunnel oxide, each of the source and drain regions in ' the substrate being in charge tunneling communication with one of the respective spacers via the tunnel oxide under control of the polysilicon gate; a second insulative layer covering the polysilicon gate and spacers such that the spacers are electrically floating structures acting as charge storage areas ; and a conductive gate electrode layer disposed over the second insulative layer and contacting the polysilicon gate through an opening in the second insulative layer, and timing means for providing voltage levels to one of the source and drain regions and then the other effective for controlling writing and reading of charge on the spacers, with the voltage levels applied relative to the conductive gate contacting the polysilicon gate. 16
[Cancelled . ]
3. A memory transistor as in claim 1 which is located in an array of identical memory transistors, with the conductive gate electrode layer defining word lines of the array, and with the source and drain regions connected to bit lines of the array.
4. A method of making a multi-level non-volatile memory transistor with lateral charge storage areas, comprising: defining a polysilicon gate having opposed sidewalls and separated from a semiconductor substrate by a first insulative layer; defining a pair of polysilicon upright spacers ad acent opposite sidewalls of the polysilicon gate and separated therefrom and from the substrate by a tunnel oxide; defining source and drain regions in the substrate, each of the source and drain regions adjacent to one of the pair of spacers in charge tunneling communication therewith; covering the polysilicon gate and spacers with a second insulative layer such- that the spacers form electrically floating structures that act as charge storage areas ; defining a conductive gate electrode layer over the second insulative layer and contacting the polysilicon gate through an opening in the second insulative layer; and storing charge independently in each of the upright spacers by providing voltage levels to one of the source and drain regions and then the other relative to the conductive gate. 17
[Cancelled. ]
6. A method as in claim 4, further defined by forming gates of low voltage MOS transistors at the same time as defining the conductive gate electrode layer of the memory transistor.
7. A method as in claim 4, further defined by forming an array of such memory transistors in a stripe geometry, wherein active regions for the memory transistors are formed in pairs of parallel stripes extending in a first direction, and all insulative and conductive structures of the memory transistors are formed in parallel stripes extending in a second direction perpendicular to the first direction.
PCT/US2003/040205 2002-12-20 2003-12-18 Multi-level memory cell with lateral floating spacers WO2004059737A1 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
CA002508810A CA2508810A1 (en) 2002-12-20 2003-12-18 Multi-level memory cell with lateral floating spacers
AU2003300994A AU2003300994A1 (en) 2002-12-20 2003-12-18 Multi-level memory cell with lateral floating spacers
EP03814101A EP1576668A4 (en) 2002-12-20 2003-12-18 Multi-level memory cell with lateral floating spacers
JP2004563670A JP2006511940A (en) 2002-12-20 2003-12-18 Multi-level memory cell with lateral floating spacer
NO20053531A NO20053531L (en) 2002-12-20 2005-07-19 Multi-level memory cell with lateral floating undoped intermediate layer structures

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/327,336 US6831325B2 (en) 2002-12-20 2002-12-20 Multi-level memory cell with lateral floating spacers
US10/327,336 2002-12-20

Publications (2)

Publication Number Publication Date
WO2004059737A1 WO2004059737A1 (en) 2004-07-15
WO2004059737B1 true WO2004059737B1 (en) 2004-09-02

Family

ID=32594228

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/040205 WO2004059737A1 (en) 2002-12-20 2003-12-18 Multi-level memory cell with lateral floating spacers

Country Status (10)

Country Link
US (3) US6831325B2 (en)
EP (1) EP1576668A4 (en)
JP (1) JP2006511940A (en)
KR (1) KR20050084343A (en)
CN (1) CN100364098C (en)
AU (1) AU2003300994A1 (en)
CA (1) CA2508810A1 (en)
NO (1) NO20053531L (en)
TW (1) TW200427066A (en)
WO (1) WO2004059737A1 (en)

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TW594944B (en) * 2003-06-05 2004-06-21 Taiwan Semiconductor Mfg Method of forming an embedded flash memory device
US7457154B2 (en) * 2004-03-15 2008-11-25 Applied Intellectual Properties Co., Ltd. High density memory array system
US7072210B2 (en) * 2004-04-26 2006-07-04 Applied Intellectual Properties Co., Ltd. Memory array
US8099783B2 (en) * 2005-05-06 2012-01-17 Atmel Corporation Security method for data protection
US7622349B2 (en) * 2005-12-14 2009-11-24 Freescale Semiconductor, Inc. Floating gate non-volatile memory and method thereof
KR100660284B1 (en) * 2005-12-28 2006-12-20 동부일렉트로닉스 주식회사 Non-volatile memory device having split gate structure, and manufacturing method thereof
US7439567B2 (en) * 2006-08-09 2008-10-21 Atmel Corporation Contactless nonvolatile memory array
KR100748003B1 (en) * 2006-08-31 2007-08-08 동부일렉트로닉스 주식회사 Embedded eeprom and method for fabricating the same
US7714376B2 (en) 2006-12-19 2010-05-11 Taiwan Semiconductor Manufacturing Co., Ltd. Non-volatile memory device with polysilicon spacer and method of forming the same
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CN111540739B (en) * 2020-05-13 2022-08-19 复旦大学 Semi-floating gate memory based on double tunneling transistors and preparation method thereof

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Also Published As

Publication number Publication date
US20040119112A1 (en) 2004-06-24
EP1576668A1 (en) 2005-09-21
EP1576668A4 (en) 2008-03-26
KR20050084343A (en) 2005-08-26
US20050062092A1 (en) 2005-03-24
AU2003300994A1 (en) 2004-07-22
US20070134875A1 (en) 2007-06-14
CA2508810A1 (en) 2004-07-15
CN100364098C (en) 2008-01-23
CN1729573A (en) 2006-02-01
TW200427066A (en) 2004-12-01
US6831325B2 (en) 2004-12-14
WO2004059737A1 (en) 2004-07-15
NO20053531L (en) 2005-07-19
US7180126B2 (en) 2007-02-20
JP2006511940A (en) 2006-04-06

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