WO2004061725A1 - Integrated circuit diagnosing method, system, and program product - Google Patents
Integrated circuit diagnosing method, system, and program product Download PDFInfo
- Publication number
- WO2004061725A1 WO2004061725A1 PCT/US2002/040429 US0240429W WO2004061725A1 WO 2004061725 A1 WO2004061725 A1 WO 2004061725A1 US 0240429 W US0240429 W US 0240429W WO 2004061725 A1 WO2004061725 A1 WO 2004061725A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- netlist
- component
- circuit
- information
- logic
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T7/00—Image analysis
- G06T7/97—Determining parameters from multiple pictures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
- G06V30/00—Character recognition; Recognising digital ink; Document-oriented image-based pattern recognition
- G06V30/40—Document-oriented image-based pattern recognition
- G06V30/42—Document-oriented image-based pattern recognition based on the type of document
- G06V30/422—Technical drawings; Geographical maps
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T2207/00—Indexing scheme for image analysis or image enhancement
- G06T2207/30—Subject of image; Context of image processing
- G06T2207/30108—Industrial image inspection
- G06T2207/30148—Semiconductor; IC; Wafer
Definitions
- the invention generally relates to diagnosing an integrated circuit.
- a schematic is a visual representation of a circuit
- a netlist is a textual representation of all the elements and various pin connections of a circuit.
- the invention provides methods, a system, and program product for diagnosing an integrated circuit.
- the invention captures one or more images for each relevant circuit layer of the integrated circuit. Based on the image(s), a component netlist is generated. Further, a logic netlist is generated by applying hierarchical composition rules to the component netlist. The component netlist or logic netlist can be compared to a reference netlist to diagnose the integrated circuit.
- the invention can further generate a schematic based on the component netlist or logic netlist in which components are arranged according to port, power, and/or component pin connection information determined from the netlist. Further, the schematic can be displayed in a manner that wiring connections are selectively displayed to assist a user in intelligently arranging the circuit components.
- the illustrative aspects of the invention are designed to solve the problems herein described and other problems not discussed, which are discoverable by a skilled artisan.
- FIG. 1 depicts an illustrative system for implementing various embodiments of the invention.
- FIG. '2 depicts a method according to one embodiment of the invention.
- FIG. 3 depicts an illustrative method of generating a netlist according to another embodiment of the invention.
- FIG. 4 depicts an alternative method of generating a netlist according to yet another embodiment of the invention.
- FIG. 5 depicts an illustrative schematic display.
- the invention provides a system, program product and methods of diagnosing an integrated circuit ("IC").
- the invention generates a "component netlist” and/or a "logic netlist” based on one or more images of each circuit layer of the integrated circuit.
- component netlist includes circuit components used in the integrated circuit (i.e., transistors, capacitors, resistors, ports, power rails, resistors, diodes, chips, etc.) and their interconnections.
- a "logic netlist” comprises a list in which one or more collections of circuit components in the component netlist are replaced with one or more symbols representing the function(s) implemented by each collection of circuit components (i.e., AND gate, NAND operation, Adder, etc.).
- FIG. 1 depicts an integrated circuit diagnosing system 12 according to one embodiment of the invention.
- System 12 may include a central processing unit (CPU) 14, memory 16, input/output (I/O) interface 18, bus 20 and an optional database 24.
- CPU central processing unit
- I/O input/output
- System 12 may be any type of general purpose/specific-use computerized system (e.g., a server, a desktop computer, etc.).
- User 30 may be an individual using system 12 or may include any type of computerized system (e.g., a mobile phone, a handheld computer, a personal digital assistant, a portable (laptop) computer, a desktop computer, a workstation, a mainframe computer, etc.) that can be used to access system 12, for example, by a network.
- communications between user 30 and system 12 may be any now known or later developed mechanisms for such purposes, e.g., one or more direct hardwired connections (e.g., serial port), or via an addressable connection in a client-server (or server-server) environment which may utilize any combination of wireline and/or wireless transmission methods.
- the server and client may be connected via the Internet, a wide area network (WAN), a local area network (LAN), a virtual private network (VPN), or other private network.
- the server and client may utilize conventional network connectivity, such as Token Ring, Ethernet, WiFi or other conventional communications standards.
- connectivity could be provided by conventional TCP/IP sockets-based protocol.
- the client would utilize an Internet service provider to establish connectivity to the server.
- System 12 can comprise any general purpose or specific-use system utilizing standard operating system software, which is designed to drive the operation of the particular hardware and which is compatible with other system components and I/O controllers.
- CPU central processing unit
- Memory 14 may comprise a single processing unit, multiple processing units capable of parallel operation, or be distributed across one or more processing units in one or more locations, e.g., on a client and server.
- Memory 16 may comprise any known type of data storage and/or transmission media, including magnetic media, optical media, random access memory (RAM), read-only memory (ROM), a data cache, a data object, etc. Moreover, similar to
- I/O interface 18 may comprise any system for exchanging information with user 30 including, for example, an I/O port (serial, parallel, ethernet, keyboard, mouse, etc.), a universal serial bus (USB) port, expansion bus, integrated drive electronics (IDE), a network system, a modem, speakers, a monitor (cathode-ray tube (CRT), liquid-crystal display (LCD), etc.), hand-held device, keyboard, mouse, voice recognition system, speech output system, scanner, printer, facsimile, pager, storage devices, etc.
- I/O port serial, parallel, ethernet, keyboard, mouse, etc.
- USB universal serial bus
- IDE integrated drive electronics
- IDE integrated drive electronics
- network system a modem
- speakers speakers
- monitor cathode-ray tube (CRT), liquid-crystal display (LCD), etc.
- hand-held device keyboard, mouse, voice recognition system, speech output system, scanner, printer, facsimile, pager, storage devices, etc.
- Bus 20 provides a communication link between each of the components in computer system 12 and likewise may comprise any known type of transmission link, including electrical, optical, wireless, etc.
- additional components such as cache memory, communication systems, system software, etc., may be incorporated into system 12.
- Database 24 may provide storage for information necessary to carry out the invention as described below.
- database 24 may include one or more storage devices, such as a magnetic disk drive or an optical disk drive. Further, database 24 can include data distributed across, for example, a LAN, WAN or a storage area network (SAN) (not shown). Database 24 may also be configured in such a way that one of ordinary skill in the art may interpret it to include one or more storage devices.
- System 12 includes integrated circuit diagnosing program 32 stored in memory 16 as computer program code. Integrated circuit diagnosing program 32 implements the various methods discussed further below.
- Capture system 34 captures one or more images of an integrated circuit and can assign coordinate information to each image.
- Component system 36 generates a component netlist based on the one or more captured images.
- Logic system 38 generates a logic netlist based on the component netlist (described further below).
- Integrated circuit diagnosing program 32 is also shown including: a compare system 40 that compares a logic and/or component netlist with one or more reference logic and/or component netlists
- reference netlists (collectively referred to as "reference netlists”) generated from a reference circuit, a schematic system 42 that generates a schematic based on the logic and/or component netlist, and a display system 44 that selectively displays wiring information in a schematic.
- reference netlists generated from a reference circuit
- schematic system 42 that generates a schematic based on the logic and/or component netlist
- display system 44 that selectively displays wiring information in a schematic.
- FIG. 2 depicts an illustrative method of diagnosing an integrated circuit according to one embodiment of the invention.
- Integrated circuits include at least one layer, and generally include more than one layer which are relevant in performing a diagnosis.
- step SI when more than one circuit layer is relevant, each relevant circuit layer of the integrated circuit is delayered (i.e., exposed) using any technique now known or later developed.
- step S2 one or more images of each circuit layer is captured as discussed in more detail below by capture system 34 (FIG. 1).
- a component netlist is generated from the image(s).
- the invention provides two alternatives for generating the component netlist from the images using component system 36 (FIG. 1) that are discussed in more detail below.
- the image(s) are transformed to a layout from which information for the component netlist is extracted.
- the information for the component netlist may be obtained directly from an inspection of the images.
- a logic netlist is generated based on the component netlist by logic system 38 (FIG. 1).
- the logic netlist is generated by applying hierarchical composition rules to the component netlist to replace one or more circuit elements with the one or more logic functions that they implement.
- an integrated circuit can include circuit elements that make up one or more input and/or output "ports" (signals).
- a "port” is any type of circuitry that provides an interface to additional circuitry (i.e., a pad, a wire connected to a non-analyzed portion of the circuit, etc).
- Integrated circuits also often include one or more circuit elements that are connected to an internal power source (V dd ), ground (V ss ), or other power source.
- V dd internal power source
- V ss ground
- the invention provides for the inclusion of port and power information in the netlists.
- the component netlist or logic netlist can be used in various applications. For example, the logic netlist or component netlist can be compared using compare system 40 (FIG. 1) to a comparable reference netlist based on a reference circuit.
- a logic netlist can be compared with another logic netlist (i.e., a "reference logic netlist”) based on a reference circuit.
- the component netlist generated from the integrated circuit can be compared to a component netlist (i.e., a "reference component netlist”) used to create the integrated circuit to determine if an error in manufacturing occurred. Similarities and differences between the two circuits (netlists) can be determined and displayed by display system 44 (FIG. 1). Further, a schematic can be created using schematic system 42 (FIG. 1) in which circuit components are arranged based on port information, power information, and/or component pin connection information.
- input port circuit elements can be located on the left of a schematic
- output port circuit elements can be located on the right
- V dd can be located on the top
- V ss can be located on the bottom.
- Wiring in the schematic can be selectively displayed using display system 44 (FIG. 1) to assist a user in further arranging the circuit components.
- step S2 one or more images of each relevant circuit layer are captured and can be stored in memory, e.g., database 24 (FIG. 1). It is understood that the number of images required for each layer depends on the required circuit resolution, the size of the circuit layer, etc. Any means for capturing images can be used including, for example, a scanning electron microscope (SEM), a specialized electron beam tool (such as electron beam induced current (EBIC) techniques), optical microscopy, digital imaging, etc. When multiple images for each circuit layer are used, a coordinate system can be used to locate the images.
- SEM scanning electron microscope
- EBIC electron beam induced current
- the upper left corner of each image can be assigned a coordinate value.
- the image that includes the upper left corner of the circuit layer would have a coordinate reference of (0, 0). Coordinates can be determined for example, based on the number of pixels present in the image and/or the physical area encompassed in the image, etc.
- Images can be captured so that an image partially overlaps one or more adjacent images. An overlap helps ensure that the images obtain complete coverage of the circuit layer, and assists in identifying situations when a circuit element is found in two adjacent images.
- the assigned coordinate reference of the images should account for the overlap. For example, when the coordinates are based on a number of pixels, the number of pixels that overlap should be subtracted from the total pixels to obtain the coordinate reference of an offset image. Alternatively, when sufficient accuracy in locating the images can be obtained, images can be captured so that no overlap is present.
- a component netlist is generated based on the image(s) of the integrated circuit.
- two alternatives can be chosen to generate the component netlist.
- the first alternative provides several improvements to existing technology in order to generate a component netlist, while the second alternative provides a more direct approach.
- FIG. 3 depicts an illustrative method of generating a component netlist. In step
- component system 36 may mclude software such as CHIPSCANNERTM by Raith USA Inc. to convert the image(s) into a layout.
- the layout is an electronic representation of the physical design of the integrated circuit. Common layout description file formats include GL1 and GDS. A layout can be read to present a visual depiction of each circuit element at its particular location within the integrated circuit. [0031] Frequently, while the layout generated from the image(s) includes wiring and physical layout information, it lacks other information. For example, port(s) and power rail(s) definitions of the integrated circuit are frequently missing.
- the layout may be edited using component system 36 (FIG. 1) to include definitions of some or all of the missing information. For example, differences in the threshold voltages between devices are typically marked with implant masks. The implant masks could be included in the layout data as a new level.
- port and power information may be added to the layout. This information assists in generating a schematic using the component netlist, comparing the component netlist with another component netlist, and/or converting the component netlist to a logic netlist, each of which is discussed further below.
- step S303 component information (transistors, resistors, chips, ports, power rails, etc.) is extracted from the layout.
- step S304 the net connectivity (i.e., wiring information such as pin-to-pin connections) is extracted from the layout.
- step S305 the component information and net connectivity are used to generate a component netlist.
- An extraction engine can be provided as part of component system 36 (FIG. 1) to implement steps S303, S304, and S305.
- the extraction engine can be built from one or more tools that generate a layout from a component netlist. These tools can be modified to extract a component netlist from a layout. For example, ERIETM by International Business
- ERIE is modified to accept data that defines layer interactions.
- component information and net connectivity are extracted.
- the extracted information is then combined and formatted into a textual representation of the layout components and their connections (i.e., a component netlist).
- FIG. 4 depicts an alternative method of generating a component netlist based on one or more circuit images.
- layer information may include circuit elements that are relevant to diagnosing the integrated circuit, including the ports, circuit components, component pins, wires, and power rails (collectively referred to as "circuit elements"). Identifying the layer information can be performed by a computer program (i.e., part of component system 36 (FIG. 1) capable of identifying and distinguishing the various circuit elements in an image, and/or by a user identifying the various circuit elements.
- a computer program i.e., part of component system 36 (FIG. 1) capable of identifying and distinguishing the various circuit elements in an image, and/or by a user identifying the various circuit elements.
- a user can be presented with each circuit image in turn. While viewing a circuit image, the user can identify a circuit element. The user could then define an area by outlining a region over the circuit element in the image using an interface of component system 36 (FIG. 1). Once the region is defined, it is given a unique identifier, and tagged with the type of circuit element. The element characteristics (i.e., identifier, level, type, location, and area information) are stored in a database. This process can continue until all relevant circuit elements have been identified.
- Ports can be identified and stored for the circuit layer that best represents the external interface to the circuit, and the various components (i.e., transistor, resistor, etc.) can be identified and stored either manually or using software. Subsequently, for each component, pins can be identified and stored along with information such as the type of pin (i.e., for a field effect transistor, source, drain or gate). Finally, the wiring can be identified and stored. [0038] Alternatively, a collection of pins can be used to identify a component without separately identifying the component. Further, a group of elements can be identified as a single element. For example, a group of vias or wires that carry the same signal can be identified as a single component.
- an image offset may be added to the location on the image when multiple images are used for a circuit layer.
- the region can remain displayed over the image to assist the user in remembering that the element has been identified. This process can be repeated for each desired circuit element, and each image until all relevant circuit elements within all relevant images have been identified.
- circuit elements that provide connections between two or more layers can be identified and stored as intermediate layer information either manually or using software.
- Intermediate layer information includes identification of all circuit elements that provide connectivity between layers, including vias and contacts.
- a computer program part of component system 36 (FIG. 1) and/or a user can define the shape characteristics that represent an intermediate circuit element that are then stored in database 24 (FIG.
- step S313 the layer information and intermediate layer information are individually reduced after being identified either manually or using software.
- the circuit elements are combined into net groups.
- a "net group” comprises a set of circuit elements that are determined to overlap. As a result, each net group indicates a collection of circuit elements that have electrical continuity. Initially, the location and region characteristics for the circuit elements are compared using component system 36 (FIG.
- a variance can be used to determine whether an overlap is present.
- a "variance" is an area added to a defined region to account for potential errors. For example, a variance equal to or less than one half the groundrule pitch for the circuit level can be added to a region before determining if it overlaps with one or more other regions. For an integrated circuit having 0.5 micron minimum line widths, a variance less than or equal to 0.25 microns can be used.
- the groundrule pitch may be specified by a user in a particular measurement unit (i.e., microns) and converted to coordinates (i.e., pixels) based on the image resolution used to image the circuit layer.
- step S314 the layer information for adjacent layers is combined using the intermediate layer information either manually or using software.
- a similar method as used with the layer information can be incorporated to determine overlapping elements between layers (i.e., adding a variance and comparing regions). However only particular circuit elements are searched for overlaps. In this case, when a match is found, the two net groups are combined into a single net group. The process is continued until all layers have been processed. For example, to combine the information for a layer 1 and a layer 2, the intermediate layer information obtained from the two layers can be sequentially selected and analyzed. As discussed above, a via may be stored as an intermediate circuit element and selected for analysis. A variance can be added to the defined shape of the via.
- the modified shape is compared to the layer information of layer 1 and then layer 2.
- the location of a wire on layer 1 connected to the via would at least partially overlap with the modified shape.
- the via is added to the net group for the wire on layer 1.
- a similar wire may be found on layer 2.
- the net groups for the layer 2 wire and layer 1 wire are combined and stored as a single net group.
- each net group represents a complete wiring combination.
- each net group should include connections from a component pin, port, and/or power rail to at least one other component pin, port, and/or power rail.
- the net groups can be used to generate a component netlist either manually or using software. Each net group is selected and all of the wiring connections defined by the net group are added to a component netlist. Once all net groups have been processed, a complete component netlist has been generated.
- step S4 includes generating a logic netlist based on the component netlist using logic system 38 (FIG. 1).
- hierarchical composition rules are applied to the component netlist to replace one or more circuit elements with an equivalent logical component.
- a "hierarchical composition rule" defines a logical component based on one or more circuit components and their connectivity. Inclusion of the port and power information allows the hierarchical composition rules to use the component function and net connectivity of the various component pins that are included in the component netlist to determine the function of portions of the circuit. For example, two transistors can be connected to implement a logical NOT of an input port.
- a pin of one transistor is tied to V dd while a pin of the other transistor is tied to V ss .
- a hierarchical composition rule is applied that recognizes the function of each transistor and the connections of the various pins of each transistor. Since power information is incorporated into the component netlist, the appropriate pin connections can be determined. The input port can be selected and the various comiections to component pins traced. Once a circuit implementing a logical NOT is found, the two transistors are replaced by a NOT gate. Because some logical circuits may include one or more simpler logical components in the circuitry, the process can continue until the most complex logical component is selected to replace portions of the component netlist.
- a database that includes common component netlist information for various logical components can be used to determine elements that implement a logical component in the circuit.
- the pin states can be dynamically analyzed to determine a logical component implemented in the circuitry.
- Several passes can be performed in which combinations of basic logical components are combined into a single, more complex logic component (i.e., an Adder can replace several logical components).
- A. NETLIST COMPARISON [0047]
- the component netlist or the logic netlist can be compared by compare system 40 (FIG. 1) to one or more reference netlists based on a reference circuit to determine similarities/differences between the integrated circuit and a reference circuit.
- An example of when this may be desired is when an integrated circuit does not function as expected.
- a component netlist can be generated from the integrated circuit and compared to a reference component netlist (i.e., the component netlist used to create the integrated circuit). Any difference between the two circuits would potentially indicate an error in manufacturing the integrated circuit.
- the logic netlist can be compared to one or more reference logic netlists to determine whether the two circuits are similar. This may be useful, for example, to determine whether intellectual property held in at least a portion of an integrated circuit has been violated.
- the reference logic netlist(s) can be based on a reference circuit for which patent protection has been obtained.
- the logic netlist can be compared with the reference logic netlist to determine whether there is any similarity between the reference circuit(s) and the integrated circuit.
- the logic netlist can be compared to a reference logic netlist by selecting a common input/output port and following the circuit paths. A threshold similarity can be specified after which a match is detected. Portions of the circuits that match ' can be displayed by a name provided for the reference logic netlist, by displaying the netlist entries, and/or by displaying a schematic based on the matched circuits.
- circuit components are placed in such a manner that the connections create a nearly incomprehensible web of crossing lines.
- location information for the integrated circuit may be of limited use, requiring substantial manual editing by a user to rearrange the circuit components into a meaningful schematic representing the integrated circuit.
- circuit components may be placed based on port information, power information, and/or component pin connection information. This information is included in the component/logic netlist generated from the edited layout or layer information.
- components are placed in the schematic, port, power, and/or component pin connection information are referenced in an organized fashion.
- components tied to input ports may be placed on the left side of the schematic with components tied to the power rail on the top of the schematic, etc.
- components can be gradually located from top to bottom and left to right as the component pin connections are followed from previously placed components.
- the relative voltage potential of a component pin can be dynamically determined, and the component placed on the schematic based on the relative potential. This further assists in reducing crossing lines and generating a conventional schematic with reduced user interface.
- the schematic when a schematic is initially displayed, the lines representing connections between circuit components may cross one another, adding confusion to the displayed circuit.
- the schematic can be displayed without the connecting wires.
- a user can then selectively display the wiring information by specifying a component (upon which all wiring connections for the component are displayed) or by specifying a pin on a component (upon which the wiring connections for the selected pin are displayed).
- a stub can be displayed at the end of each component pin/port.
- a user can select a stub, and the wiring for the selected stub can be displayed. In this manner, the user can relocate the circuit components based on the limited wiring information displayed until a desired arrangement is obtained.
- a toggle setting can alternately display all the wiring connections or no/limited wiring connections so that progress can easily be determined.
- FIG. 5 depicts an illustrative schematic display 50 according to an embodiment of the invention.
- Schematic display 50 includes controls 70 that allow a user to select how the wiring information of the circuit is displayed. For example, a user can select control 72 to display all wiring information, control 74 to display only wiring information of a selected component, or control 76 to display only wiring information of a selected pin. Control 74 is displayed in bold to indicate that it is the currently selected option.
- the circuit includes a pair of input ports 52, 54 and an output port 56.
- a transistor pair 58, 60 are configured to invert the signal provided at input port 52 (perform a logical NOT).
- NOR component 62 Various circuit elements have been replaced with their logical equivalent, NOR component 62.
- NOR component 62 performs a logical NOR operation on the output of transistor pair 58, 60 and input port 54.
- the output of NOR component 62 is provided to output port 56.
- Transistor 58 is shown in bold to indicate that it is the selected component. Consequently, only the wiring information for its pins is displayed. The remaining wiring information is shown in dashed lines, but would not be displayed based on the current selections.
- Each pin is shown as a stub 68. Consequently, should a user desire to display wiring information for a pin, the user would select the stub 68 that represents the pin. [0054] As described in the previous section, the various components have been arranged according to port and power information when the schematic was generated.
- V ss 64 is shown at the top of the schematic, and V dd 66 is located at the bottom, while input ports 52, 54 are located on the left, and output port 56 is located on the right.
- transistors 58, 60 have been located from top to bottom according to their respective connections to V ss 64 and V dd 66.
- transistors 58, 60 and NOR component 62 have been located left to right according to their respective connections to input ports 52, 54 and output port 56.
- schematic display 50 is only illustrative of the capability described herein. Schematic display 50 is not intended to completely depict a schematic display or all the operations that can be performed by a user. Further, it is understood that various alternative user interfaces for indicating selections and making selections are possible, and are covered by the invention.
- the invention can be realized in hardware, software, or a combination of hardware and software. Any kind of computer/server system(s) - or other apparatus adapted for carrying out the methods described herein - is suited.
- a typical combination of hardware and software could be a general purpose computer system with a computer program that, when loaded and executed, controls system 12, and/or a user 30 system such that they carry out the respective methods described herein.
- a specific use computer containing specialized hardware for carrying out one or more of the functional tasks of the invention, could be utilized.
- the invention can also be embedded in a computer program product, which comprises all the respective features enabling the implementation of the methods described herein, and which - when loaded in a computer system - is able to carry out these methods.
- Computer program, software program, program, or software in the present context mean any expression, in any language, code or notation, of a set of instructions intended to cause a system having an information processing capability to perform a particular function either directly or after either or both of the following: (a) conversion to another language, code or notation; and/or (b) reproduction in a different material form.
- the invention is useful for diagnosing integrated circuits, and more particularly for generating a netlist and/or schematic based on an integrated circuit.
Abstract
Description
Claims
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004564618A JP4528134B2 (en) | 2002-12-17 | 2002-12-17 | Integrated circuit diagnostic method and program thereof |
PCT/US2002/040429 WO2004061725A1 (en) | 2002-12-17 | 2002-12-17 | Integrated circuit diagnosing method, system, and program product |
CNB028300424A CN100392660C (en) | 2002-12-17 | 2002-12-17 | Integrated circuit diagnosing method, system, and program product |
AU2002357881A AU2002357881A1 (en) | 2002-12-17 | 2002-12-17 | Integrated circuit diagnosing method, system, and program product |
US11/160,266 US7503021B2 (en) | 2002-12-17 | 2005-06-16 | Integrated circuit diagnosing method, system, and program product |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/US2002/040429 WO2004061725A1 (en) | 2002-12-17 | 2002-12-17 | Integrated circuit diagnosing method, system, and program product |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/160,266 Continuation US7503021B2 (en) | 2002-12-17 | 2005-06-16 | Integrated circuit diagnosing method, system, and program product |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2004061725A1 true WO2004061725A1 (en) | 2004-07-22 |
Family
ID=32710249
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2002/040429 WO2004061725A1 (en) | 2002-12-17 | 2002-12-17 | Integrated circuit diagnosing method, system, and program product |
Country Status (4)
Country | Link |
---|---|
JP (1) | JP4528134B2 (en) |
CN (1) | CN100392660C (en) |
AU (1) | AU2002357881A1 (en) |
WO (1) | WO2004061725A1 (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2007002799A1 (en) * | 2005-06-29 | 2007-01-04 | Lightspeed Logic, Inc. | Methods and systems for placement |
WO2007014451A1 (en) * | 2005-08-04 | 2007-02-08 | Chipworks Inc. | Method and system for vertically aligning tile images of an area of interest of an integrated circuit |
US7752588B2 (en) | 2005-06-29 | 2010-07-06 | Subhasis Bose | Timing driven force directed placement flow |
US7840927B1 (en) | 2006-12-08 | 2010-11-23 | Harold Wallace Dozier | Mutable cells for use in integrated circuits |
US8332793B2 (en) | 2006-05-18 | 2012-12-11 | Otrsotech, Llc | Methods and systems for placement and routing |
US10180402B2 (en) | 2012-12-14 | 2019-01-15 | Sri International | Method and apparatus for conducting automated integrated circuit analysis |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8390269B2 (en) * | 2010-10-07 | 2013-03-05 | Raytheon Company | Non-destructive determination of functionality of an unknown semiconductor device |
US8990675B2 (en) | 2011-10-04 | 2015-03-24 | Microsoft Technology Licensing, Llc | Automatic relationship detection for spreadsheet data items |
US9069748B2 (en) * | 2011-10-04 | 2015-06-30 | Microsoft Technology Licensing, Llc | Selective generation and display of data items associated with a spreadsheet |
CN103576040B (en) * | 2012-07-24 | 2016-03-30 | 施耐德电器工业公司 | The wiring error diagnosis and removal system and method for on-the-spot electronic product |
KR102595789B1 (en) * | 2021-11-11 | 2023-10-27 | 금오공과대학교 산학협력단 | Automatic recognition of electronic circuit diagram image and netlist conversion method |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5694481A (en) * | 1995-04-12 | 1997-12-02 | Semiconductor Insights Inc. | Automated design analysis system for generating circuit schematics from high magnification images of an integrated circuit |
US6236746B1 (en) * | 1996-10-01 | 2001-05-22 | Semiconductor Insights, Inc. | Method to extract circuit information |
US6289116B1 (en) * | 1996-09-27 | 2001-09-11 | Semiconductor Insights, Inc. | Computer-assisted design analysis method for extracting device and interconnect information |
US6536018B1 (en) * | 2000-06-05 | 2003-03-18 | The University Of Chicago | Reverse engineering of integrated circuits |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63291169A (en) * | 1987-05-22 | 1988-11-29 | Matsushita Electric Ind Co Ltd | Circuit diagram output method |
US5513118A (en) * | 1993-08-25 | 1996-04-30 | Nec Usa, Inc. | High level synthesis for partial scan testing |
JP3426919B2 (en) * | 1997-07-28 | 2003-07-14 | シャープ株式会社 | Figure creation device |
JP2000266706A (en) * | 1999-03-18 | 2000-09-29 | Toshiba Corp | Detecting device and its method |
JP2002032427A (en) * | 2000-07-19 | 2002-01-31 | Nec Microsystems Ltd | Device and method for connection verification of lsi and medium with connection verifying program recorded thereon |
-
2002
- 2002-12-17 JP JP2004564618A patent/JP4528134B2/en not_active Expired - Fee Related
- 2002-12-17 AU AU2002357881A patent/AU2002357881A1/en not_active Abandoned
- 2002-12-17 CN CNB028300424A patent/CN100392660C/en not_active Expired - Fee Related
- 2002-12-17 WO PCT/US2002/040429 patent/WO2004061725A1/en active Application Filing
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5694481A (en) * | 1995-04-12 | 1997-12-02 | Semiconductor Insights Inc. | Automated design analysis system for generating circuit schematics from high magnification images of an integrated circuit |
US6289116B1 (en) * | 1996-09-27 | 2001-09-11 | Semiconductor Insights, Inc. | Computer-assisted design analysis method for extracting device and interconnect information |
US6236746B1 (en) * | 1996-10-01 | 2001-05-22 | Semiconductor Insights, Inc. | Method to extract circuit information |
US6536018B1 (en) * | 2000-06-05 | 2003-03-18 | The University Of Chicago | Reverse engineering of integrated circuits |
Non-Patent Citations (2)
Title |
---|
BOURBAKIS ET AL.: "A knowledge-based expert system for automatic visual VLSI reverse-engineering: VLSI layout version", IEEE TRANSACTIONS ON SYSTEMS, MAN AND CYBERNETICS, vol. 32, no. 3, May 2002 (2002-05-01), pages 428 - 436, XP002967809 * |
BOURBAKIS ET AL.: "Specifications for the development of an expert tool for the automatic optical understanding of electronic circuits: VLSI reverse engineering", 1991 IEEE VLSI TEST SYMPOSIUM, April 1991 (1991-04-01), pages 98 - 103, XP010034370 * |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2007002799A1 (en) * | 2005-06-29 | 2007-01-04 | Lightspeed Logic, Inc. | Methods and systems for placement |
US7653884B2 (en) | 2005-06-29 | 2010-01-26 | Geoffrey Mark Furnish | Methods and systems for placement |
US7752588B2 (en) | 2005-06-29 | 2010-07-06 | Subhasis Bose | Timing driven force directed placement flow |
US7814451B2 (en) | 2005-06-29 | 2010-10-12 | Geoffrey Mark Furnish | Incremental relative slack timing force model |
US7921392B2 (en) | 2005-06-29 | 2011-04-05 | Otrsotech, Limited Liability Company | Node spreading via artificial density enhancement to reduce routing congestion |
US7921393B2 (en) | 2005-06-29 | 2011-04-05 | Otrsotech, Limited Liability Company | Tunneling as a boundary congestion relief mechanism |
WO2007014451A1 (en) * | 2005-08-04 | 2007-02-08 | Chipworks Inc. | Method and system for vertically aligning tile images of an area of interest of an integrated circuit |
US8332793B2 (en) | 2006-05-18 | 2012-12-11 | Otrsotech, Llc | Methods and systems for placement and routing |
US7840927B1 (en) | 2006-12-08 | 2010-11-23 | Harold Wallace Dozier | Mutable cells for use in integrated circuits |
US10180402B2 (en) | 2012-12-14 | 2019-01-15 | Sri International | Method and apparatus for conducting automated integrated circuit analysis |
Also Published As
Publication number | Publication date |
---|---|
AU2002357881A1 (en) | 2004-07-29 |
CN100392660C (en) | 2008-06-04 |
CN1714355A (en) | 2005-12-28 |
JP4528134B2 (en) | 2010-08-18 |
JP2006513560A (en) | 2006-04-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7503021B2 (en) | Integrated circuit diagnosing method, system, and program product | |
CN1256733C (en) | IC test software system for mapping logical functional data of logic integrated circuits to physical representation | |
CA2517651C (en) | Method of design analysis of existing integrated circuits | |
US6826735B2 (en) | Inspection data analysis program, defect inspection apparatus, defect inspection system and method for semiconductor device | |
US7480878B2 (en) | Method and system for layout versus schematic validation of integrated circuit designs | |
US6289254B1 (en) | Parts selection apparatus and parts selection system with CAD function | |
CN101063987B (en) | Net-list organization tools | |
US7013028B2 (en) | Advanced schematic editor | |
CA2358729C (en) | Computer aided method of circuit extraction | |
CA2573729C (en) | Method and apparatus for locating short circuit faults in an integrated circuit layout | |
US20080066042A1 (en) | Method and system for creating, viewing, editing, and sharing output from a design checking system | |
US8464191B2 (en) | System and method for identifying circuit components of an integrated circuit | |
Delamaro et al. | Using concepts of content‐based image retrieval to implement graphical testing oracles | |
WO2004061725A1 (en) | Integrated circuit diagnosing method, system, and program product | |
JP4082616B2 (en) | Signal propagation path drawing apparatus, drawing method and program thereof | |
US8645896B1 (en) | Method to transfer failure analysis-specific data between design houses and fab's/FA labs | |
US7546565B2 (en) | Method for comparing two designs of electronic circuits | |
JP2003086689A (en) | Cad tool for failure analysis of semiconductor and failure analysis method of semiconductor | |
US9230050B1 (en) | System and method for identifying electrical properties of integrate circuits | |
KR20050094402A (en) | Integrated circuit diagnosing method, system, and program product | |
JP5293488B2 (en) | Design support program, design support apparatus, and design support method | |
US20090007033A1 (en) | Method to transfer failure analysis-specific data between data between design houses and fab's/FA labs | |
Harris et al. | Comparing Circuit Connectivity Between All-Metal GDS Layouts. | |
KR20240028968A (en) | Computer systems, dimensional measurement methods, and semiconductor device manufacturing systems | |
JP2004110627A (en) | Method and device for designing semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ OM PH PL PT RO RU SD SE SG SK SL TJ TM TN TR TT TZ UA UG US UZ VN YU ZA ZM ZW |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR IE IT LU MC NL PT SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
WWE | Wipo information: entry into national phase |
Ref document number: 1020057010340 Country of ref document: KR |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2531/DELNP/2005 Country of ref document: IN |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2004564618 Country of ref document: JP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 11160266 Country of ref document: US Ref document number: 20028300424 Country of ref document: CN |
|
WWP | Wipo information: published in national office |
Ref document number: 1020057010340 Country of ref document: KR |
|
122 | Ep: pct application non-entry in european phase |