METHOD AND SYSTEM FOR OPTIMIZATION OF A DATA PROCESSING CHAIN USING SYNCHRONOUS HANDSHAKE PROTOCOL WITH DATA ASSEMBLY
AND SEGMENTATION
PRIORITY CLAIM
This application claims the benefit of United States Provisional Patent Application No. 60/440,450, filed January 1 6, 2003, entitled "METHOD AND SYSTEM FOR DATA ASSEMBLY AND SEGMENTATION USING SYNCHRONOUS HANDSHAKE PROTOCOL",, and United States Provisional Patent Application No. 60/440,448, filed January 16, 2003, entitled "METHOD AND SYSTEM FOR OPTIMIZATION OF A DATA PROCESSING CHAIN USING SYNCHRONOUS HANDSHAKE PROTOCOL BY OPERATING FREQUENCY AND FORMAT ADAPTATION", both of which are incorporated herein by reference.
FIELD OF THE INVENTION
The present invention relates to the optimization of a data processing chain using synchronous handshake protocol by operating frequency and format adaptation, including data assembly and segmentation.
BACKGROUND OF THE INVENTION
In a signal processing chain using a synchronous handshake protocol to exchange data between blocks, the data processing path is a chain of several blocks. Each block performs a specific processing task on input data coming from the preceding or upstream block and provides output data to the next or downstream block. The transfer of data between the upstream and downstream blocks is controlled by a handshake protocol that is based on two signals: Ready to Send (RTS) signal sent from the upstream block to the downstream block to indicate that the upstream block is ready to transfer data to the downstream block, and - Ready To Receive (RTR) signal sent from the downstream block to the upstream block to indicate that the downstream block is ready to accept data from the upstream block. The data is moved from the upstream block to the downstream block when both signals are true. FIG. 1 (Prior Art) is a block diagram of an exemplary conventional synchronous Ready To Send and Ready To Receive ("RTS/RTR") handshake scheme 10. In the conventional scheme 10, an upstream block 1 2 and a downstream block 14 are coupled by a first handshake channel 16, a second
handshake channel 18 and a data bus 20. The first handshake channel 16 is configured to carry a Ready To Send ("RTS") handshake signal, which is active to indicate that upstream block 1 2 is prepared to send at least one word of data over a data bus 20 to downstream block 14. The second handshake channel 18 is configured to carry a Ready To Receive ("RTR") handshake signal, which is active to indicate that downstream block 14 is prepared to accept at least one word of data from upstream block 12 via the data bus 20. In the handshake protocol, each block has its own control and relies on the RTS/RTR signal to know if data are received/sent. There is no necessity to have a top-level controller. During each clock cycle for which a handshake has occurred, one word of data is transferred from upstream block 12 to downstream block 14 over the data bus 20.
In a data processing chain, using the synchronous handshake protocol, to guarantee the required bandwidth and throughput, each block has a required input minimum bandwidth. In other words, the block must be fed with enough data so that it can process and send the required amount of data to the next block in a certain period of time. To achieve this bandwidth, it may be necessary for a block to receive several elementary data words at the same time. Alternatively, it may be necessary for a block to segment a concatenated data word made of several words into elementary data words.
The present invention provides a method and system that allows the blocks in a data stream to use the synchronous handshake interface without requiring the blocks to have the same data formats.
SUMMARY OF THE INVENTION
The format adaptation method and apparatus according to the present invention optimizes a data processing chain using synchronous handshake protocol by adapting the data format between an upstream block having a upstream data format of one data word length and a downstream data format of another data word length. The present invention allows easy adaptation of the data format by either combining several data of size W together and make it a single data of size N*W, where N is an integer number greater than or equal to 2; or segmenting a data word of size N*W into N successive data words of size W; and in either case respecting the handshake protocol of the upstream and downstream blocks.
The method optimizes a data processing chain using synchronous handshake protocol by adapting the data format between an upstream block, having an upstream data format and generating an upstream RTS signal, and a
downstream block (54), having a downstream data format and generating a downstream RTR signal, the upstream data format being different from the downstream data format. Using a data pipeline, the method includes the steps of: receiving the upstream RTS signal and the downstream RTR signal; counting the number of data words in the data pipeline; generating an upstream adaptation RTR signal when the data pipeline is ready to receive data from the upstream block based on the number of data words in the data pipeline; generating an input handshake signal (IN HS) when both the upstream RTS signal and the upstream adaptation RTR signal are active; receiving data into the data pipeline in the upstream format from the upstream block when the IN HS signal is active; transforming the data from the upstream data format to the downstream data format; generating a downstream adaptation RTS signal when the data pipeline is ready to send data to the downstream block based on the number of data words in the data pipeline; generating an output handshake signal (OUT_HS) when both the downstream RTR signal and the downstream adaptation RTS signal are active; and ending the data from the data pipeline in the downstream data format to the downstream block when the OUT_HS signal is active.
In the case, the upstream block has a upstream data format of length W and generates an upstream RTS signal, and the downstream block has a downstream data format of length N *W, N being an integer greater than 2, and generates a downstream RTR signal, the format adaptation apparatus includes a shift register that receives data words from the upstream block in the upstream data format and sends data words to the downstream block in the downstream data format; a counter that generates a COUNT signal indicating the number of data words in the shift register; a RTR assembly that receives the COUNT signal and generates an upstream adaptation RTR signal when the shift register is ready to receive data from the upstream block; a RTS assembly that receives the COUNT signal and generates a downstream adaptation RTS signal when the shift register is ready to send data to the downstream block; an upstream handshake assembly that generates an input handshake signal (IN_HS) when both the upstream RTS signal and the upstream adaptation RTR signal are active; and a downstream handshake assembly that generates an output handshake signal (OUT_HS) when both the downstream RTR signal and the downstream adaptation RTS signal are active. The data word is received by the shift register when the IN_HS signal is generated, and the data word is sent by the shift register when the OUT_HS signal is generated.
In the case, the upstream block has an upstream data format of length N *W and generates an upstream RTS signal, and the downstream block has a downstream data format of length W, N being an integer greater than 2, and generates a downstream RTR signal, the format adaptation apparatus includes a data pipeline that receives data words from the upstream block in the upstream data format and sends data words to the downstream block in the downstream data format; a counter that generates a COUNT signal indicating the number of data words sent from the data pipeline; a RTR assembly that receive the COUNT signal and generates an upstream adaptation RTR signal when the data pipeline is ready to receive data from the upstream block; a RTS assembly that receive the COUNT signal and generates a downstream adaptation RTS signal when the data pipeline is ready to send data to the downstream block; an upstream handshake assembly that generate an input handshake signal (INJHS) when both the upstream RTS signal and the upstream adaptation RTR signal are active; and a downstream handshake assembly that generates an output handshake signal (OUT_HS) when both the downstream RTR signal and the downstream adaptation RTS signal are active. The data word is received by the data pipeline when the INJHS signal is generated, and the data word is sent by the data pipeline when the OUT_HS signal is generated.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 (Prior Art) is a block diagram of a conventional synchronous Ready To Send and Ready To Receive ("RTS/RTR") handshake scheme;
FIG. 2 is a block diagram of an exemplary RTS/RTR handshake scheme with an adaptation block according to the present invention;
FIG. 3 is a block diagram of an exemplary RTS/RTR handshake scheme with an adaptation block comprising a speed adaptation block followed by a format adaptation block;
FIG. 4 is a block diagram of an exemplary RTS/RTR handshake scheme with an adaptation block comprising a format adaptation block followed by a speed adaptation block;
FIG. 5 is a block diagram of an exemplary RTS/RTR handshake scheme with an adaptation block comprising a speed adaptation block;
FIG . 6 is a block diagram of an exemplary format adaptation block shown in FIGS. 3-5 for use when the upstream data format is shorter than the downstream data format;
FIG. 7 is a waveform diagram for the format adaptation block shown in FIG. 6;
FIG. 8 is a block diagram of an exemplary format adaptation block shown in FIGS. 3-5 for use when the upstream data format is longer than the downstream data format;
FIG. 9 is a waveform diagram for the format adaptation block shown in FIG. 8.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
The characteristics and advantages of the present invention will become more apparent from the following description, given by way of example. FIG. 2 is a block diagram of an exemplary adaptation block handshake scheme 50 according to the present invention. In the adaptation block handshake scheme 50, an upstream block 52 is connected to a downstream block 54 through an intervening adaptation block 56. A first handshake channel 58 is configured to carry an UPSTREAM READY TO SEND ("RTS") handshake signal from the upstream block 52 to the adaptation block 56. The UPSTREAM RTS handshake signal is used to indicate that the upstream block 52 is prepared to send at least one word of data over an upstream data bus 62 to the adaptation block 56. A second handshake channel 64 is configured to carry a DOWNSTREAM RTS signal from the adaptation block 56 to the downstream block 54. The DOWNSTREAM RTS signal is used to indicate that the adaptation block 56 is prepared to send at least one word of data over a downstream data bus 68 to the downstream block 54. A third handshake channel 66 is configured to carry a DOWNSTREAM READY TO RECEIVE ("RTR") handshake signal from the downstream block 54 to the adaptation block 56. The DOWNSTREAM RTR handshake signal is used to indicate that the downstream block 54 is prepared to accept at least one word of data from the adaptation block 56 over the downstream data bus 68. A fourth handshake channel 60 is configured to carry an UPSTREAM RTR signal from the adaptation block 56 to the upstream block 52. The UPSTREAM RTR signal is used to indicate that the adaptation block 56 is prepared to receive at least one word of data over the upstream data bus 62 from the upstream block 52.
FIG. 3 is a top-level block diagram of one embodiment of the adaptation block 56 of FIG. 2. In this embodiment, the adaptation block 56 is implemented by a speed adaptation block 80 followed by a format adaptation block 82. The speed adaptation block 80 is used when the upstream block 52 and the downstream block 54 run at different clock speeds. The speed adaptation block 80 has both an upstream clock input 90 and a downstream clock input 92 and the ratio between the different clock speeds is a parameter of the speed
adaptation block 80. The speed adaptation block 80 transfers data downstream while respecting the handshake protocol of both the upstream block 52 and the downstream block 54. The speed adaptation block 80 acts as a small buffer in passing data from the upstream block 52 to the downstream block 54. The format adaptation block 82 is used when the upstream block 52 and the downstream block 56 have different data word lengths. The ratio between the word lengths is a parameter of the format adaptation block 82. When the data word length of the downstream block 54 is longer than the data word length of the upstream block 52, the format adaptation block 82 combines several successive words of data from the upstream block 52 to form a single word to pass to the downstream block 54. When the data word length of the downstream block 54 is shorter than the data word length of the upstream block 52, the format adaptation block 82 segments one data word from the upstream block 52 into several separate data words to pass to the downstream block 54. The format adaptation block 82 functions in a single clock domain.
The adaptation block 56 can be implemented by the speed adaptation block 80 alone, the format adaptation block 82 alone, or a combination of speed adaptation blocks 80 and format adaptation blocks 82, depending upon the speed and data requirements of the upstream block 52 and the downstream block 54. The speed adaptation block 80 adapts differing clock speeds. The format adaptation block 82 adapts differing data formats. These blocks can be inserted in virtually any order. However, the maximum bandwidth of the chain can be impacted depending on this order. As will be shown below, to maximize bandwidth, it is preferable to put the format adaptation block 82 in the higher frequency clock domain so it can perform format adaptation at the higher clock frequency.
FIG. 3 shows an embodiment of the adaptation block 56 in which the speed adaptation block 80 is upstream of the format adaptation block 82. For clarity, the first handshake channel 58, the second handshake channel 64, the third handshake channel 66, the fourth handshake channel 60, the upstream data bus 62 and the downstream data bus 68 (see FIG. 2) are shown again in FIG. 3. The speed adaptation block 80 and the format adaptation block 82 are coupled by a first adaptation handshake channel 84, a second adaptation handshake channel 86 and a first adaptation data bus 88. The first adaptation handshake channel 84 is configured to carry an ADAPTATION RTS handshake signal that indicates when the speed adaptation block 80 is prepared to send at least one word of data over the first adaptation data bus 88 to the format adaptation block 82. The second adaptation handshake channel 84 is configured
to carry a ADAPTATION RTR signal that indicates when the format adaptation block 82 is prepared to receive at least one word of data over the first adaptation data bus 88 from the speed adaptation block 80. The upstream clock input 90 of the speed adaptation block 80 receives the clock signal of the upstream block 52, and the downstream clock input 92 of the speed adaptation block 80 receives the clock signal of the downstream block 54. The format adaptation block 82 has a single clock input 94 that, since the format adaptation block 82 is on the downstream side of the speed adaptation block 80, receives the clock signal of the downstream block 54. FIG. 4 shows an alternative embodiment of the adaptation block 56 in which the format adaptation block 82 is upstream of the speed adaptation block 80. The format adaptation block 82 and the speed adaptation block 80 are coupled by a third adaptation handshake channel 1 04, a fourth adaptation handshake channel 1 06 and a second adaptation data bus 1 08. The third adaptation handshake channel 1 04 is configured to carry an ADAPTATION RTS handshake signal that indicates when the format adaptation block 82 is prepared to send at least one data word over the second adaptation data bus 1 08 to the speed adaptation block 80. The fourth adaptation handshake channel 1 04 is configured to carry an ADAPTATION RTR signal that indicates when the speed adaptation block 80 is prepared to receive at least one data word over the second adaptation data bus 1 08 from the format adaptation block 82. The speed adaptation block 80 receives the clock inputs of both the upstream block 52 and the downstream block 54 at the upstream clock input 90 and the downstream clock input 92, respectively. Since the format adaptation block 82 is on the upstream side of the speed adaptation block 80, the clock input 94 of the format adaptation block 82 receives the clock signal of the upstream block 52.
The order of the speed adaptation block 80 and the format adaptation block 82 in the adaptation block 56 can impact the maximum bandwidth of the data stream from the upstream block 52 to the downstream block 54. One case where this occurs is when the upstream block 52 runs at a faster clock frequency and has a shorter data word length than the downstream block 54: for example, when the upstream block 52 runs at a F MHz clock speed and the downstream block 54 runs at a slower F/N MHz clock speed, and the upstream block 52 processes length W data words and the downstream block 54 processes length N*W words.
Using the adaptation block 56 shown in Fig, 3 in this case, the upstream block 52 can send a data word of length W on the upstream data bus 62 up to
once every clock cycle of the upstream clock. When the upstream block 52 is ready to send a data word, it sends the UPSTREAM RTS signal on the first handshake channel 58. The speed adaptation block 80 acts as a buffer between the clock domains of the upstream block 52 and the downstream block 54. When the buffer of the speed adaptation block 80 is not full, it sends the UPSTREAM RTR signal on the fourth handshake channel 60. Obeying the handshake protocol, when both the UPSTREAM RTS signal and the UPSTREAM RTR signal are active, a data word of length W will be transferred from the upstream block 52 to the speed adaptation block 80. In this case, the format adaptation block 82 works in the slower clock domain of the downstream block 54. Since there are N clock cycles of the upstream clock (F MHz) for every one clock cycle at the downstream clock (F/N MHz), the format adaptation block 82 can not accept more than one data word every N clock cycles of the upstream clock. Thus, once the buffer of the speed adaptation block 80 is full, the speed adaptation block 80 can not accept more than one data word of size W every N clock cycles of the upstream clock. When both the ADAPTATION RTS and the ADAPTATION RTR signals are active, a handshake occurs and a data word of size W is sent on the adaptation data bus 88 from the speed adaptation block 80 to the format adaptation block 82. The format adaptation block 82 combines N successive data words of size
W received from the speed adaptation block 80 into a single data word of size N*W to pass to the downstream block 54. However, the format adaptation block 82, running at the slower downstream clock speed, needs at least N*N clock cycles of the upstream clock to receive N data words to form one data word of length N*W to pass to the downstream block 54. When the format adaptation block 82 is ready to send out a word of length N*W on the downstream data bus 68, it sends the DOWNSTREAM RTS signal on the second handshake channel 64.
The downstream block 54 can accept up to one data every downstream clock cycle When the downstream block 54 is ready to receive a data word on the downstream data bus 68, it sends a DOWNSTREAM RTR signal on the fourth handshake channel 66. When both the DOWNSTREAM RTS and the DOWNSTREAM RTR signals are active, a handshake occurs and a data word of length N*W is transferred from the format adaptation block 82 to the downstream block 54 via the downstream data bus 68. Therefore, in this case with the adaptation block 56 shown in FIG. 3, the maximum throughput is one data word of length N*W every N"N clock cycles of the faster upstream clock, or a frequency of f/N*N MHz.
Using the adaptation block shown in Fig, 4 under the same conditions, the upstream block 52 can send a data word of length W on the upstream data bus 62 up to once every clock cycle of the upstream clock. When the upstream block 52 is ready to send a data word, it sends the UPSTREAM RTS signal on the first handshake channel 58. In this case, the format adaptation block 82 works in the faster upstream clock domain and combines N successive data words of size W received from the upstream block 52 into a single data word of size N*W to pass downstream. The format adaptation block 82 can accept up to one data word every upstream clock cycle. Obeying the handshake protocol, when the UPSTREAM RTS signal and the UPSTREAM RTR signal are both active, a data word of length W is transferred from the upstream block 52 to the format adaptation block 82. It takes at least N cycles of the upstream clock for the format adaptation block 1 00 to assemble a word of length N *W to send out over the adaptation data bus 1 08. When the format adaptation block 82 is ready to send out a word of length N*W on the adaptation data bus 1 08, it sends the ADAPTATION RTS signal on the third adaptation handshake channel 1 04.
Since there are N clock cycles of the upstream clock (F MHz) for every one clock cycle of the downstream clock (F/N MHz), the downstream block 54 can accept up to one data word of length N*W every N clock cycles of the upstream clock. Thus, the speed adaptation block 80, once its buffer is full, can accept up to one data word of size N*W every N clock cycles of the upstream clock. When the speed adaptation block 80 is ready to receive a data word, it sends the ADAPTATION RTR signal on the fourth adaptation handshake channel 1 06. When both the ADAPTATION RTS and the ADAPTATION RTR signals are active, a handshake occurs and a data word of size N *W is sent on the adaptation data bus 1 08 from the format adaptation block 82 to the speed adaptation block 80.
When the speed adaptation block 80 is ready to send a data word downstream, it sends a DOWNSTREAM RTS signal along the third handshake channel 64 to the downstream block 54. When the downstream block 54 is ready to receive a data word of length N*W on the downstream data bus 68, it sends a DOWNSTREAM RTR signal on the fourth handshake channel 66. When both the DOWNSTREAM RTS and the DOWNSTREAM RTR signals are active, a handshake occurs and a data word of length N*W is transferred from the speed adaptation block 80 to the downstream block 54 via the downstream data bus 1 08. Therefore, in this case with the adaptation block 56 shown in FIG. 4, the maximum throughput is one data word of length N*W every N clock cycles of the faster upstream clock, or at a frequency of f/N MHz.
Therefore, for the case where the upstream block 52 runs at F MHz and the downstream block 54 runs at F/N MHz; and the upstream block 52 processes words of length W and the downstream block 54 processes words of length N*W: the embodiment shown in Fig. 3 can support a bandwidth of up to one data word of length N*W at a frequency of f/(N*N) MHz, while the embodiment shown in Fig. 4 can support a bandwidth up to N times faster of one word of length N*W at a frequency of f/N MHz,.
Another case in which the order of the speed adaptation block 80 and the format adaptation block 82 in the adaptation block 56 impacts the maximum data bandwidth is when the upstream block 52 runs at a slower clock frequency and has a longer data word length than the downstream block 54: for example, the upstream block 52 runs at a clock speed of F/N MHz and the downstream block 54 runs at a faster clock speed of F MHz; and the upstream block 52 processes data words of length N*W and the downstream block 54 processes data words of length W.
Using the adaptation block shown in Fig, 3 under these conditions, the upstream block 52 can send up to one data word of length N*W to the speed adaptation block 80 at up to once every clock cycle of the upstream clock, and the speed adaptation block 80 can send up to one data word of length N*W to the format adaptation block 82 at up to once every clock cycle of the upstream clock.
In this case, the format adaptation block 82 operates in the faster clock domain of the downstream block 54, and segments one data word of length N*W received from the speed adaptation block 80 into N data words of length W to send to the downstream block 54. The downstream block 54 can accept up to one data word of length N each clock cycle of the faster downstream clock. Thus, the format adaptation block 82 can segment a data word of length N*W received from the speed adaptation block 80 and send the resulting N data words of length W to the downstream block 54 at up to once every N clock cycles of the faster downstream clock which corresponds to one clock cycle of the upstream clock. Therefore, in this case with the adaptation block 56 shown in FIG. 3, the maximum throughput is one data word of length N*W every N clock cycles of the faster downstream clock, or at a frequency of f/N MHz.
Using the adaptation block shown in Fig, 4 under the same conditions, the upstream block 52 can send up to one data word of length N*W to the format adaptation block 82 each upstream clock cycle. In this case, the format adaptation block 82 operates in the slower upstream clock domain, and segments one data word of length N*W into N data words of size W to pass
downstream. Thus, the format adaptation block 82 can send up to one data word of length W on the adaptation data bus 108 every clock cycle of the slower upstream clock.
The downstream block 54 can accept up to one data word of length W each clock cycle of the faster downstream clock, thus the speed adaptation block 80 can accept up to one data word of length W every clock cycle of the faster downstream clock. However, the speed adaptation block 80 can only receive one data word of length W from the format adaptation block 82 once every clock cycle of the slower upstream clock. Therefore, in this case with the adaptation block'56 shown in FIG. 4, the maximum throughput is one data word of length W every clock cycle of the slower upstream clock, or one data word of length N*W every N clock cycles of the slower upstream clock.
Therefore, in the case where the upstream block 52 runs at F/N MHz and the downstream block 54 runs at F MHz; and the upstream block 52 processes data words of length N*W and the downstream block 54 processes words of length W: the embodiment of the adaptation block 56 shown in Fig. 3 supports a data bandwidth of up to one data word of length N*W at a frequency of f/N MHz, while the embodiment shown in Fig. 4 only supports a bandwidth N times slower of one word of length N*W at a frequency of f/(N*N) MHz. FIG. 5 shows an alternative embodiment of the adaptation block 56 implemented by only the format adaptation block 82, the format adaptation block 82 respecting the handshake protocol of both the upstream block 52 and the downstream block 54.
FIG. 6 is a block diagram of the exemplary format adaptation block 82 shown in FIGS. 3-5 for use when the upstream block 52 has a shorter data word length, length W, and the downstream block 54 has a longer data word length, length N*W, the ratio between the word lengths, N, is an integer positive number greater than or equal to 2. The format adaptation block 82 receives N successive words of length W from the upstream block 52, forms one concatenated word of length N*W, and sends the single concatenated word to the downstream block 54. The format adaptation block 82 respects the handshake protocol with both the upstream block 52 and the downstream block 54. In the exemplary embodiment, the format adaptation block 82 is implemented by synchronous digital logic circuitry and logic blocks as discussed herein. However, it is noted that in alternative embodiments the speed adaptation block 80 may be implemented by any other suitable hardware, software, or combination thereof. FIG. 7 shows waveform signals discussed
below to further illustrate the behavior of this embodiment of the format adaptation block 82.
The format adaptation block 82 shown in FIG . 6 for connecting a shorter data word length upstream block 52 to a longer data word length downstream block (54) includes a shift register 200 that can hold N data words of size W, a counter 220, an upstream AND gate 230, a downstream AND gate 240, a RTR assembly 250 and a RTS assembly 320.
The upstream AND gate 230 has an input 232 coupled to the first handshake channel 58 that carries the UPSTREAM RTS signal sent by the upstream block 52, an input 234 coupled to the fourth handshake channel 60 that carries the UPSTREAM RTR signal generated in the format adaptation block 82, and an output 236 that carries the input handshake (IN_HS) signal. When both the UPSTREAM RTS and the UPSTREAM RTR signals are active the INJHS signal is active, otherwise the INJHS signal is not active. The INJHS signal indicates when data is received on the upstream data bus 62.
The downstream AND gate 240 has an input 242 coupled to the second handshake channel 64 that carries the DOWNSTREAM RTS signal generated in the format adaptation block 80, an input 244 coupled to the third handshake channel 66 that carries the DOWNSTREAM RTR signal sent by the downstream block 54, and an output 246 that carries the output handshake (OUT HS) signal. When both the DOWNSTREAM RTS and the DOWNSTREAM RTR signals are active the OUT_HS signal is active, otherwise the OUT_HS signal is not active. The OUT_HS signal represents when data is sent on the downstream data bus 68. The shift register 200 has an input 202 coupled to the upstream data bus
62 for receiving words of length W from the upstream block 52, an enable input 204 coupled to the output of the upstream AND gate 230 carrying the INJHS signal, a clock input 206 coupled to the clock signal, and an output 204 coupled to the downstream data bus 68 for sending words of length N *W to the downstream block 54. The shift register 200 is of size N words of length W. When an INJHS signal occurs, the data in the shift register 200 is shifted and the data word received at the input 202 from the upstream data bus 62 is added to the shift register 200. Once N words have been loaded in the shift register 200, the output 204 of the shift register 200 is ready to send a N*W length data word over the downstream data bus 68.
The counter 220 keeps track of the number of data words stored in the shift register 200. The counter 220 counts between "0" and "N-1 ". The counter 220 has an input 222 coupled to the INJHS signal generated by the
upstream AND gate 230, a clock input 224 coupled to the clock signal 94, an input 226 coupled to the reset input 98, and an output 228 that contains the counter value (COUNT) signal. The INJHS signal received at input 222 increments the counter value by 1 . The RTS assembly 320 and the RTR assembly 250 generate the adaptation RTS and RTR signals of the format adaptation block 82, respectively.
In general, the signals and data flow operate as follows. The adaptation RTR signal is held high as long as the shift register 200 is not full. When the COUNT value at the counter output 228 equals "N-1 ", on the next INJHS signal, the COUNT value at the counter output 228 goes back to a "0" value. At this time, N words have been loaded in the shift register 200 and the adaptation block 82 is ready to pass one data word of length N *W to the downstream block 54 on the downstream data bus 68. The adaptation RTS signal goes high, and the adaptation RTR goes low and is held low until an OUTJHS signal occurs. When the OUTJHS signal occurs, the N*W length data word is passed to the downstream block 54, the adaptation RTS signal goes low again, and the adaptation RTR signal goes high to indicate that the shift register 200 can be loaded again.
The RTS assembly 320 includes a RTS logic block 290 and a flip-flop 300. The logic block 290 includes an input 292 coupled to the output of the AND gate 240 that carries the OUT HS signal, an input 294 coupled to the output of the AND gate 230 that carries the INJHS signal, an input 296 coupled to the counter output 228 carrying the COUNT signal, and an output 298 carrying the RTS signal coupled to an input 302 of the flip-flop 300. The flip-flop 300 includes the input 302 coupled to the output of the RTS logic block 290, a clock input 304 coupled to the clock input 94, a reset input 306 coupled to the reset input 98, and an output 308 coupled to the second handshake channel 64 that carries the DOWNSTREAM RTS signal.
The RTS logic block 290 of the RTS assembly 320 implements the following function which defines the RTS signal at the output 298:
IF [ (COUNT = "N-1 " ) AND (INJHS = "1 ") ] THEN RTS = "1 " ELSE IF [ OUTJHS = "1 " ] THEN RTS = "0" ELSE RTS keeps the same value. The flip-flop 300 operates as follows. When the reset signal at the reset input 306 is active, the output 308 is held to a "0" value. When the reset signal is not active, the value at the output 308 is set on the rising edge of the clock signal received at the clock input 304 to the value of the adaptation RTS signal received at input 302 from the RTS logic block 290. The value at the output
308 is the DOWNSTREAM RTS signal generated and used by the format adaptation block 82 and sent to the downstream block 54.
The RTR assembly 250 includes a RTR logic block 260 and a flip-flop 290. The RTR logic assembly 260 includes an input 262 coupled to the AND gate 240 that carries the OUTJHS signal, an input 264 coupled to the output 236 of the AND gate 230 that carries the INJHS signal, an input 266 coupled to the counter output 228 carrying the COUNT signal, an input 268 coupled to the output 308 of the RTS flip-flop 300 carrying the adaptation RTS signal, an input 270 coupled to the second handshake channel 64 that carries the DOWNSTREAM RTS signal, and an output 278 carrying the RTR signal coupled to an input 282 of the flip-flop 280. The flip-flop 280 includes the input 282 coupled to the output of the logic block 260, a clock input 284 coupled to the clock input 94, a reset input 286 coupled to the reset input 98, and an output 288 coupled to the fourth handshake channel 60 that carries the UPSTREAM RTR signal.
The RTR logic block 260 of the RTR assembly 250 implements the following function which defines the RTR signal at the output 288: IF [ (COUNT = "N-1 " ) AND ( INJHS = "1 " ) ] OR
[ (COUNT = "0" ) AND (RTS = "1 ") AND (DOWNSTREAM RTR = "0") ]
THEN RTR = "0" ELSE RTR = "1 " The flip-flop 280 operates as follows. When the reset signal at the reset input 286 is active, the output 288 is held to a "0" value. When the reset signal is not active, the value at the output 288 is set on the rising edge of the clock signal received at the clock input 284 to the value of the RTR signal received at input 282 from the RTR logic block 260. The value at the output 288 is the UPSTREAM RTR signal generated and used by the format adaptation block 82 and sent to the upstream block 52. FIG. 8 is a block diagram of the exemplary format adaptation block 82 shown in FIGS. 3-5 for use when the upstream block 52 has a longer data word length, length N*W, and the downstream block 54 has a shorter data word length, length W, the ratio between the word lengths, N, is an integer positive number greater than or equal to 2. The format adaptation block 82 receives a word of length N *W from the upstream block 52 and segments it into N successive words of length W to be sent to the downstream block 54. The format adaptation block 82 respects the handshake protocol with both the upstream block 52 and the downstream block 54. In the exemplary
embodiment, the format adaptation block 82 is implemented by synchronous digital logic circuitry and logic blocks as discussed herein. However, it is noted that in alternative embodiments the speed adaptation block 80 may be implemented by any other suitable hardware, software, or combination thereof. FIG. 9 shows waveform signals discussed below to further illustrate the behavior of this embodiment of the format adaptation block 82.
The format adaptation block 82 shown in FIG. 8 for segmenting a longer data word from the upstream block 52 into a shorter data word for the downstream block (54) includes an data pipeline 400, a counter 450, an upstream AND gate 430, a downstream AND gate 440, a RTS assembly 540 and a RTR assembly 520.
The upstream AND gate 430 has an input 432 coupled to the first handshake channel 58 that carries the UPSTREAM RTS signal sent by the upstream block 52, an input 434 coupled to the fourth handshake channel 60 that carries the UPSTREAM RTR signal generated in the format adaptation block 82, and an output 436 that carries the input handshake (INJHS) signal. When both the UPSTREAM RTS and the UPSTREAM RTR signals are active the IN HS signal is active, otherwise the IN_HS signal is not active. The IN_HS signal indicates when data is received on the upstream data bus 62. The downstream AND gate 440 has an input 442 coupled to the second handshake channel 64 that carries the DOWNSTREAM RTS signal generated in the format adaptation block 82, an input 444 coupled to the third handshake channel 66 that carries the DOWNSTREAM RTR signal sent by the downstream block 54, and an output 446 that carries the output handshake (OUTJHS) signal. When both the DOWNSTREAM RTS and the DOWNSTREAM RTR signals are active the OUTJHS signal is active, otherwise the OUTJHS signal is not active. The OUT_HS signal represents when data is sent on the downstream data bus 68.
The counter 450 keeps track of the number of data words of length W sent to the downstream block 54. The counter 450 counts between "0" and "N-1 ". The counter 450 has an input 452 coupled to the OUTJHS signal generated by the downstream AND gate 440, a clock input 454 coupled to the clock signal 94, an input 456 coupled to the reset input 98, and an output 458 that contains the counter value (COUNT) signal. The OUTJHS signal received at input 452 increments the counter value by 1 .
The data pipeline 400 includes an input storage block 41 0 coupled to the upstream data bus 62 for receiving words of length N*W from the upstream block 52, and a multiplexer 420 coupled to the downstream data bus 68 for
sending words of length W to the downstream block 54. The input storage block 410 includes an input 412 coupled to the upstream data bus 62, an enable input 414 coupled to the output of the upstream AND gate 430 carrying the INJHS signal, a clock input 416, and a series of outputs 418 coupled to a series of inputs 422 of the multiplexer 420 for transferring data words of length W. The multiplexer 420 includes the series of inputs 422 connected the series of output 418 of the input storage block 410, a selector input 424 coupled to the counter output 458 carrying the COUNT signal, and an output 428 coupled to the downstream data bus 68 for sending words of length N to the downstream block 54. When an IN_HS signal occurs, a data word of length N*W received at input 412 is stored in the input storage block 410. The multiplexer 420 then selects which one of the N words of length W will be transferred from the series of multiplexer inputs 422 to the multiplexer output 428 based on the COUNT signal received at the selector input 424. The RTS assembly 540 and the RTR assembly 520 generate the adaptation RTS and RTR signals of the format adaptation block 82, respectively. In general, the signals and data flow operate as follows. The RTR signal is held high until an IN_HS occurs. When the IN_HS occurs, a data word of length N*W received on the upstream data bus 62 is loaded in the input storage block 410 and the RTS signal goes high. The COUNT signal output by the counter 450 is then incremented by "1 " every time an OUTJHS occurs which indicates that one of the N successive words of length W is sent by the multiplexer 420 on the downstream data bus 68. When the COUNT value at the counter output 458 equals "N-1 ", on the next OUTJHS signal, the COUNT value at the counter output 458 goes back to a "0" value. At this time, N words have been sent through the multiplexer 420, the adaptation RTS signal goes low, the adaptation RTR signal goes back to high and stays high until the next INJHS occurs indicating that a data word of length N*W is loaded in the input storage block 410, and the process repeats. The RTS assembly 540 includes a RTS logic block 490 and a flip-flop 500.
The RTS logic block 490 includes an input 492 coupled to the output of the upstream AND gate 430 that carries the INJHS signal, an input 494 coupled to the counter output 458 carrying the COUNT signal, an input 496 coupled to the output of the downstream AND gate440 that carries the OUTJHS signal, and an output 498 carrying the RTS signal coupled to an input 502 of the flip-flop 500. The flip-flop 500 includes the input 502 coupled to the output of the RTS logic block 490, a clock input 504 coupled to the clock input 94, a reset input 506
coupled to the reset input 98, and an output 508 coupled to the second handshake channel 64 that carries the DOWNSTREAM RTS signal.
The RTS logic block 490 implements the following function which defines the RTS signal at the output 498: IF ( IN_HS = "1 " ) THEN RTS = "1 "
ELSE IF [ ( COUNT = "N-1 ") AND ( OUTJHS = "1 " ) ] THEN RTS = "O"
ELSE RTS keeps the same value. The flip-flop 500 operates as follows. When the reset signal at the reset input 506 is active, the output 508 is held to a "0" value. When the reset signal is not active, the value at the output 508 is set on the rising edge of the clock signal received at the clock input 504 to the value of the adaptation RTS signal received at input 502 from the RTS logic block 490. The value at the output 508 is the DOWNSTREAM RTS signal generated and used by the format adaptation block 82 and sent to the downstream block 54.
The RTR assembly 520 includes a RTR logic block 460 and a flip-flop 480. The RTR logic assembly 460 includes an input 462 coupled to the output 436 of the upstream AND gate 430 that carries the INJHS signal, an input 464 coupled to the counter output 458 carrying the COUNT signal, an input 466 coupled to the downstream AND gate 440 that carries the OUTJHS signal, an input 468 coupled to the output 508 of the RTS flip-flop 500 carrying the RTS signal, and an output 478 carrying the RTR signal coupled to an input 482 of the flip-flop 480. The flip-flop 480 includes the input 482 coupled to the output of the logic block 460, a clock input 484 coupled to the clock input 94, a reset input 486 coupled to the reset input 98, and an output 488 coupled to the fourth handshake channel 60 that carries the UPSTREAM RTR signal.
The RTR logic block 460 implements the following function which defines the RTR signal at the output 488:
IF [ (COUNT = "N-1 " ) AND ( OUTJHS = "1 " ) ] OR [ (COUNT = "0" ) AND (INJHS = "0") AND ( RTS = "0") ]
THEN RTR = "1 " ELSE RTR = "0" The flip-flop 480 operates as follows. When the reset signal at the reset input 486 is active, the output 488 is held to a "0" value. When the reset signal is not active, the value at the output 488 is set on the rising edge of the clock signal received at the clock input 484 to the value of the RTR signal received at input 482 from the RTR logic block 460. The value at the output 488 is the
UPSTREAM RTR signal generated and used by the format adaptation block 82 and sent to the upstream block 52.
While the present invention has been described with reference to the preferred embodiment, it is apparent that various changes may be made in the embodiment without departing from the spirit and the scope of the invention, as defined by the appended claims.