WO2004068578A3 - Verfahren zum herstellen von bitleitungen für ucp-flash-speicher - Google Patents

Verfahren zum herstellen von bitleitungen für ucp-flash-speicher Download PDF

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Publication number
WO2004068578A3
WO2004068578A3 PCT/DE2004/000042 DE2004000042W WO2004068578A3 WO 2004068578 A3 WO2004068578 A3 WO 2004068578A3 DE 2004000042 W DE2004000042 W DE 2004000042W WO 2004068578 A3 WO2004068578 A3 WO 2004068578A3
Authority
WO
WIPO (PCT)
Prior art keywords
floating gate
bit lines
substrate
insulation
etching
Prior art date
Application number
PCT/DE2004/000042
Other languages
English (en)
French (fr)
Other versions
WO2004068578A2 (de
Inventor
Achim Gratz
Veronika Polei
Original Assignee
Infineon Technologies Ag
Achim Gratz
Veronika Polei
Roehrich Mayk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Achim Gratz, Veronika Polei, Roehrich Mayk filed Critical Infineon Technologies Ag
Priority to CN200480003230.8A priority Critical patent/CN1745473B/zh
Priority to EP04702285A priority patent/EP1588417A2/de
Publication of WO2004068578A2 publication Critical patent/WO2004068578A2/de
Publication of WO2004068578A3 publication Critical patent/WO2004068578A3/de
Priority to US11/194,059 priority patent/US7485542B2/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region

Abstract

Die Erfindung betrifft ein Verfahren zum Herstellen von Bitleitungen für UCP Flash Speicher mit einem auf einem Substrat angeordneten Floating-Gate Anordnung und einer Isolation im Substrat unter der Floating-Gate Anordnung, wobei zunächst das Floating-Gate nach vorhergehender Photolithographie durch Ätzen einer auf dem Substrat befindliche ganzflächig abgeschiedenen Poly-Silizium-Schicht hergestellt wird. Der Erfindung liegt die Aufgabe zugrunde, ein Verfahren zu schaffen, mit dem eine Verringerung der Zellengröße erreicht wird, die Herstellungskosten unwesentlich beeinflusst werden und die Bitleitung das Temperaturbudget der Folgeprozesse ohne Schaden übersteht. Erreicht wird das dadurch, dass die Bitleitung (13) als vergrabene Bitleitung aus einem temperaturbeständigen Material in einem Silizium Substrat (2) bzw. innerhalb der Isolation (3) der aktiven Gebiete unter dem Floating Gate (1) selbstjustiert zu diesem angeordnet ist. Dabei wird unter Verwendung des bereits strukturierten Floating Gates (1) als Ätzmaske ein Graben (6) in die Isolation (3) geätzt, der anschließend mit einem niederohmigen Material verfüllt wird.
PCT/DE2004/000042 2003-01-30 2004-01-15 Verfahren zum herstellen von bitleitungen für ucp-flash-speicher WO2004068578A2 (de)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN200480003230.8A CN1745473B (zh) 2003-01-30 2004-01-15 统一信道程序闪存位线制造方法
EP04702285A EP1588417A2 (de) 2003-01-30 2004-01-15 Verfahren zum herstellen von bitleitungen für ucp-flash-speicher
US11/194,059 US7485542B2 (en) 2003-01-30 2005-07-29 Method for producing bit lines for UCP flash memories

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10303847 2003-01-30
DE10303847.7 2003-01-30

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11/194,059 Continuation US7485542B2 (en) 2003-01-30 2005-07-29 Method for producing bit lines for UCP flash memories

Publications (2)

Publication Number Publication Date
WO2004068578A2 WO2004068578A2 (de) 2004-08-12
WO2004068578A3 true WO2004068578A3 (de) 2004-10-28

Family

ID=32797297

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2004/000042 WO2004068578A2 (de) 2003-01-30 2004-01-15 Verfahren zum herstellen von bitleitungen für ucp-flash-speicher

Country Status (4)

Country Link
US (1) US7485542B2 (de)
EP (1) EP1588417A2 (de)
CN (1) CN1745473B (de)
WO (1) WO2004068578A2 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160211250A1 (en) * 2015-01-15 2016-07-21 Infineon Technologies Ag Semiconductor substrate arrangement, a semiconductor device, and a method for processing a semiconductor substrate

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5570314A (en) * 1994-12-28 1996-10-29 National Semiconductor Corporation EEPROM devices with smaller cell size
US5661057A (en) * 1992-03-18 1997-08-26 Fujitsu Limited Method of making flash memory
US6001687A (en) * 1999-04-01 1999-12-14 Taiwan Semiconductor Manufacturing Company, Ltd. Process for forming self-aligned source in flash cell using SiN spacer as hard mask
WO2001017022A1 (en) * 1999-08-27 2001-03-08 Infineon Technologies North America Corp. Semiconductor device with buried bitlines
US6214741B1 (en) * 1999-11-05 2001-04-10 United Silicon Incorporated Method of fabricating a bit line of flash memory
US20010018249A1 (en) * 2000-02-29 2001-08-30 Takao Tanaka Semiconductor device with low resistivity film embedded and manufacturing method for the same
US20020038897A1 (en) * 2000-08-15 2002-04-04 Tuan Hsing Ti Nonvolatile memory structures and fabrication methods
US20020045304A1 (en) * 1999-12-30 2002-04-18 Chien-Hsing Lee Fabrication method and structure of flash memory device

Family Cites Families (8)

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Publication number Priority date Publication date Assignee Title
US4855800A (en) 1986-03-27 1989-08-08 Texas Instruments Incorporated EPROM with increased floating gate/control gate coupling
DE69228082T2 (de) * 1991-03-12 1999-08-19 Kuraray Co Spiroorthocarbonat-Verbindung und daraus erhaltene Polymere
US5278438A (en) 1991-12-19 1994-01-11 North American Philips Corporation Electrically erasable and programmable read-only memory with source and drain regions along sidewalls of a trench structure
FR2686837B1 (fr) 1992-01-31 1995-05-24 Valeo Thermique Habitacle Dispositif de chauffage-ventilation de l'habitacle d'un vehicule automobile a moteur a faibles rejets thermiques.
US20040111159A1 (en) * 2000-01-30 2004-06-10 Diamicron, Inc. Modular bearing surfaces in prosthetic joints
JP2001168306A (ja) * 1999-12-09 2001-06-22 Toshiba Corp 不揮発性半導体記憶装置及びその製造方法
DE10122364B4 (de) * 2001-05-09 2006-10-19 Infineon Technologies Ag Kompensationsbauelement, Schaltungsanordnung und Verfahren
JP2003023113A (ja) 2001-07-05 2003-01-24 Mitsubishi Electric Corp 半導体装置およびその製造方法

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5661057A (en) * 1992-03-18 1997-08-26 Fujitsu Limited Method of making flash memory
US5570314A (en) * 1994-12-28 1996-10-29 National Semiconductor Corporation EEPROM devices with smaller cell size
US6001687A (en) * 1999-04-01 1999-12-14 Taiwan Semiconductor Manufacturing Company, Ltd. Process for forming self-aligned source in flash cell using SiN spacer as hard mask
WO2001017022A1 (en) * 1999-08-27 2001-03-08 Infineon Technologies North America Corp. Semiconductor device with buried bitlines
US6214741B1 (en) * 1999-11-05 2001-04-10 United Silicon Incorporated Method of fabricating a bit line of flash memory
US20020045304A1 (en) * 1999-12-30 2002-04-18 Chien-Hsing Lee Fabrication method and structure of flash memory device
US20010018249A1 (en) * 2000-02-29 2001-08-30 Takao Tanaka Semiconductor device with low resistivity film embedded and manufacturing method for the same
US20020038897A1 (en) * 2000-08-15 2002-04-04 Tuan Hsing Ti Nonvolatile memory structures and fabrication methods

Also Published As

Publication number Publication date
US20060024889A1 (en) 2006-02-02
CN1745473B (zh) 2010-04-14
US7485542B2 (en) 2009-02-03
WO2004068578A2 (de) 2004-08-12
CN1745473A (zh) 2006-03-08
EP1588417A2 (de) 2005-10-26

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