WO2004075403A2 - Electronic circuit with array of programmable logic cells - Google Patents
Electronic circuit with array of programmable logic cells Download PDFInfo
- Publication number
- WO2004075403A2 WO2004075403A2 PCT/IB2004/050108 IB2004050108W WO2004075403A2 WO 2004075403 A2 WO2004075403 A2 WO 2004075403A2 IB 2004050108 W IB2004050108 W IB 2004050108W WO 2004075403 A2 WO2004075403 A2 WO 2004075403A2
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- WO
- WIPO (PCT)
- Prior art keywords
- programmable logic
- output
- input
- carry
- circuit
- Prior art date
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
- G06F7/503—Half or full adders, i.e. basic adder cells for one denomination using carry switching, i.e. the incoming carry being connected directly, or only via an inverter, to the carry output under control of a carry propagate signal
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1733—Controllable logic circuits
- H03K19/1737—Controllable logic circuits using multiplexers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17724—Structural details of logic blocks
- H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/527—Multiplying only in serial-parallel fashion, i.e. one operand being entered serially and the other in parallel
- G06F7/5272—Multiplying only in serial-parallel fashion, i.e. one operand being entered serially and the other in parallel with row wise addition of partial products
Definitions
- the invention relates to an electronic circuit with an array of programmable logic cells.
- Programmable logic cells enable circuit designers to adapt the logic function of individual instances of electronic circuits that have been mass-produced, such as integrated circuits. This reduces the time interval from design to production of a working circuit and it reduces manufacturing cost for production of small batches of products and for prototyping.
- a programmable cell contains a memory that is addressed by the input signal of the cell, the memory storing pre-programmed output signals for each combination of input signal values at the respective addresses that are addressed by these values.
- the memory is said to have a LUT (Look-Up Table) function, for looking up the output signals that are produced in response to various input signals.
- Any logic function can be implemented with a LUT, provided that it contains sufficient memory space.
- LUTs In practice, however, only logic functions that require a limited number of inputs, typically no more than four, are implemented with LUTs in circuits with programmable logic cells. Such a LUT requires 16 memory locations. This permits the programming of random logic functions of four input bits. In many cases circuits with such cells with four input bit functions suffice.
- designers are implementing logic functions for which a part of the array of programmable logic cells is used to implement signal-processing operations such as additions. Many signal processing operations have the property that many bits of a wider input operand each can influence many bits in an output result, through carry effects. However, very inefficient implementations are obtained when such a wide dependency is implemented using 4 bit input LUTs.
- XilinxTM has addressed this problem in its VirtexTM family of programmable logic devices by adding a carry chain to an array of 4 bit input LUT cells.
- Fig. 1 shows a programmable logic cell of such a device.
- the cell contains a four input lookup table 10 that performs the LUT function and a carry circuit 12 with a carry input and a carry output.
- the output of memory 10 is coupled to the carry circuit 12, which combines the carry input signal with the output signal of the LUT to form the carry output signal.
- An exclusive OR gate 14 is used to form the output signal of the cell from the carry input signal and output signal of the LUT.
- the carry input and carry output of the cell are coupled to the carry output and the carry input of adjacent cells in the array (not shown) to form a carry chain.
- the carry chain performs the carry function from the output of one 4 bit input LUT to another.
- no LUTs need to be allocated to implement carry functions. This saves a considerable number of LUTs when the circuit is used to implement logic functions that include some signal processing operations.
- the implementation of signal processing functions in such a more general purpose circuit that is also capable of implementing random logic functions is still far less efficient. It would be desirable if this efficiency could be improved.
- the electronic circuit according to the invention is set forth in Claim 1.
- the electronic circuit contains a programmable logic cell with a plurality of programmable logic units that are coupled in parallel.
- the programmable logic units comprise a configurable look-up table circuit, having inputs coupled to receive the logic input signals from the input circuit and having an output, the configurable look-up table providing an input output function in accordance with a predetermined number of configuration bits.
- the programmable logic units also comprise a controllable inverter/non-inverter circuit, having an input connected to the output of the look-up table circuit and having an output, the inverter/non-inverter being controllable by an input carry signal.
- the predetermined number of configuration bits control the look-up tables of two or more programmable logic units in the programmable logic cell. This has the advantage of reducing the number of configuration bits required by the logic cell, and hence the size of memory required.
- the programmable logic units further comprise an auxiliary multiplexer having inputs coupled to receive the output of the look-up table circuit and the output of the inverter/non-inverter circuit, and providing an output signal from the programmable logic units.
- the programmable logic units further comprise a multiplexer having inputs coupled to receive the logic input signals from the input circuit, and providing a multiplexer output signal under control of a first control signal, when configured to operate in a multiplexer mode.
- the arrangement described in this embodiment has the advantage of providing multiplexing functions in addition to datapath functions.
- Fig. 1 shows a prior art programmable logic cell
- Fig. 2 shows an array of programmable logic units according to the present invention
- Fig. 3 shows further details of a programmable logic unit of Figure 2, adapted to provide multiplexer functions
- Fig. 4 shows an alternative embodiment of the programmable logic unit of Figure 2, adapted to provide multiplexer functions
- Fig. 5 shows a logic cell implementing an array of programmable logic units according to Figure 3;
- Fig. 6 shows a logic cell implementing an array of programmable logic units according to Figure 4.
- Fig. 7 shows a logic cell of the present invention when configured with a programmable logic unit as shown in Figure 3.
- Figure 2 shows a programmable logic cell having a parallel arrangement of programmable logic units 24a-d, and a carry chain 28.
- the logic cell receives input signals Ao- 3 and Bo- 3 .
- Carry chain 28 has a carry input Cin and a carry output Cout, and is coupled to the programmable logic units at a series of positions along the chain.
- Each programmable logic unit 24a-d comprises selection logic 403, for example a 4:1 multiplexer, which forms part of a look-up table 400 which is configured to provide an output signal O in response to a given set of input signals A n B n .
- the output of each programmable logic unit is determined by configuration bits stored in a configuration memory 404.
- the configuration memory 404 is shared by a plurality of programmable logic units 24a-d, thereby permitting the logic cell to be optimized for the mapping of datapath functions. By programming the configuration bits, the function of the logic cell can be configured.
- the configuration bits determine which output signal values the programmable logic units 24a-d will produce in response to various input signal values.
- each programmable logic unit 24a-d is associated with a different significance level.
- the input circuit 22 is configured to pass signals to each programmable logic unit 24a-d that represent the bits from different operands, each bit corresponding to the significance level that is associated with the programmable logic unit 24a-d.
- Each programmable logic unit 24a-d responds to these signals by computing the bit of the result at the significance level that is associated with the programmable logic unit 24a-d, taking account of a carry input signal Cin that is received from carry chain 28 from a lower significance level and supplying a carry output signal Cout to the carry chain for use at a higher significance level.
- all programmable logic units 24a-d are configured to provide the same relation between their input signals and output signals, due to the sharing of the configuration bits in configuration memory 404.
- the computed bits "O" from each of the programmable logic units 24a-d are passed in parallel as output signals to an output circuit (not shown).
- Carry chain 28 computes carry signals and passes these carry signals from one programmable logic unit 24a-d to another.
- the configuration of carry chain 28 controls whether carry chain 28 uses a carry input signal from carry input Cin to determine the carry signals. If the logic cell processes input signals that are more significant bits of a larger operand, the cell is configured so that such a carry input signal is used to receive a carry output signal of another cell that processes less significant operands.
- Figure 2 also shows additional gates 50 and 52, which enable the programmable logic unit 24 to perform arithmetic subtraction without external complement formation and 1 -bit multiplication-plus-accumulation (e.g. as a step in multi-bit multiplication).
- Implementation of subtraction is facilitated by adding an exclusive OR gate 50 between the LUT unit 400 and one of the signal inputs A n , B n that receives a bit of the operand that must be subtracted.
- a subtraction control signal SUB is supplied to one of the inputs of exclusive OR gate 50 so that the input signal is logically inverted.
- the subtraction control signal is set to zero when addition is required.
- a common subtraction control signal for all of the programmable logic units in the logic cell may be used for this purpose.
- the subtraction signal may be controlled by a configuration bit of the logic cell or by a signal from outside the logic cell. In case of subtraction a logic high carry input signal is applied to the programmable logic unit that is associated with the lowest significance level. Implementation of multiplication plus accumulation is supported by adding an
- AND gate 52 between the LUT unit 400 and one of the signal inputs A, B that receives a bit of the operand that must be multiplied and supplying a factor signal MUL to one of the inputs of this AND gate.
- a common factor signal MUL for all of the programmable logic units in the logic cell may be used for this purpose.
- the factor signal is set to one when addition is required.
- Figure 2 shows AND gate 52 and the exclusive OR gate 50 provided in combination, it will be readily apparent to a person skilled in the art that either may be omitted when no subtraction or multiplication is required. Also, it will be understood that multiplication and subtraction can be implemented in alternative ways, with equivalents of exclusive OR gate 50 at different positions in the circuit and/or a different configuration of LUT unit 400
- FIG 3 shows further detail of the programmable logic unit 24 and a part 42 of the carry chain 28.
- the programmable logic unit 24 comprises a LUT unit 00, which functions as previously described in Figure 2.
- the programmable logic unit 24 also comprises an exclusive OR gate 402.
- the signal inputs A, B of programmable logic unit 24 are coupled to the inputs of LUT unit 400.
- An output of LUT unit 400 is coupled to an input of exclusive-OR gate 402.
- a second input of first exclusive OR-gate 402 is coupled to receive a carry input signal Cin from the carry chain 28, and an output of the exclusive OR gate 402 forms an output signal 01.
- a multiplexer 405 receives the output 01 from the XOR gate 402 and the output 02 from the LUT 400.
- the multiplexer 405 produces an output signal O under control of a configuration bit 407 from configuration memory (not shown).
- LUT unit 400 realizes a configurable input output function using the shared configuration bits, as previously described in Figure 2.
- a datapath output signal 01 is made available at the output O of the programmable logic unit 24.
- the multiplexer 405 selects the direct output 02 of the LUT 400.
- the XOR gate 402 may be implemented in other ways.
- the XOR gate 402 may be replaced by a 2: 1 multiplexer which receives the output of the look-up table at a first input and an inverted version of the output of the look-up table at a second input, with the multiplexer being controlled by the carry input signal Cin.
- FIG 4 shows an alternative embodiment, which is capable of handling multiplexer functions in addition to multi-bit operand processing functions.
- the programmable logic unit comprises a LUT 400, an XOR gate 402 and a multiplexer 405 controlled by a configuration bit 407, having the same functions as the corresponding features of the invention as shown in Figure 3. Additionally, the programmable logic unit comprises a further multiplexer 406 for use in a multiplexing mode of operation.
- the signal inputs A, B of the programmable logic unit 24 are coupled to the inputs of the multiplexer 406, (for example a 2:1 multiplexer for a 2-bit LUT), which is placed in parallel to the LUT unit 400.
- the multiplexer 406 is controlled by a control signal X, which is an auxiliary signal of the logic cell.
- each programmable logic unit 24 receives the same control signal X.
- the programmable logic unit 24 produces a first output signal OD when configured to operate in a multi-bit operand processing mode (i.e. the multiplexer 405 outputting either the signal 01 from the LUT unit 400 or the signal 02 when configured to process wide Boolean functions), and a second output signal OR when configured to function as a multiplexer.
- the output signal OR bypasses the LUT unit 00 and the XOR gate 402.
- the provision of the multiplexer 06 in the programmable logic unit 24 enables the logic cell to be configured for multiplexing operations in addition to datapath or arithmetic functions.
- FIG. 5 shows an implementation of a logic cell 20 having programmable logic units 24a-d as shown in Figure 3.
- Each programmable logic unit 24a-d receives input signals 21, and produces an output signal O according to the configuration bits (not shown) which are shared between all of the programmable logic units 24a-d.
- the output signals O are passed to a switching circuit 268 of the output circuit 26, which produces output signals 27.
- Figure 6 shows an implementation of a logic cell 20 having programmable logic units 24a-d as shown in Figure 4.
- each programmable logic unit 24a-d When configured in the multi-bit operand processing mode, each programmable logic unit 24a-d receives input signals 21, and produces an output signal OD according to configuration bits (not shown) which are shared between all of the programmable logic units 24a-d.
- the output signals OD are passed to a switching circuit 268 of the output circuit 26, which produces output signals 27.
- the plurality of programmable logic units 24a-d produce and output signal OR.
- the output signal OR is one of the input signals 21, selected by the control signal X.
- the output signals OR are passed to the inputs of a first stage of multiplexers 264a,b in the output circuit 26.
- the first stage of multiplexers are controlled by a control signal Y.
- the further multiplexer 266 is connected to receive the output signals from the multiplexers 264a, 264b, and provides a multiplexer output signal to the switching circuit 268 under control of control signal Z.
- the logic cell is configurable to provide both types of multiplexers using up to three auxiliary signals, X, Y and Z, in addition to the eight primary input signals.
- the three auxiliary signals X, Y and Z are used as selection signals for the logic multiplexers mapped onto the logic cell. The three signals are required in order to deal with the maximum case of a 1-bit 8:1 multiplexer. With other multiplexer arrangements fewer auxiliary signals are required.
- control signal X can be shared between the datapath and multiplexer modes.
- control signal X provides the carry input signal Cin to the carry chain 28, while in the multiplexer mode the control signal X is used to control the multiplexers 06 of Figure 4.
- control signals Y and Z of the multiplexer mode can be shared with the control signals MUL and SUB of the multi-bit operand processing mode.
- control signals may be derived from dedicated auxiliary control signals, or taken from the plurality of primary input signals.
- the logic cells shown in Figures 5 and 6 include four processing elements, thereby allowing an implementation of 4-bit datapath functions. Nevertheless, it is noted that the number of processing elements (bit-slices) in the logic cell may be arbitrary. For example, each cell may be made such that it processes a complete word of 32 bits, for example.
- Figure 7 shows an example implementation of a logic cell configured with the programmable logic units of Figure 3, and having XOR gates 50a-d at their inputs to allow subtraction.
- the programmable logic units 24a-d are controlled by configuration bits 404 which are shared between the programmable logic units 24a-d.
- the multiplexers 405 a-d are controlled by a further configuration bit 407.
- the subtraction signal SUB is connected to either a configuration bit or to an external dynamic signal.
- the functionality of Figure 7 can be improved further if the programmable logic units of Figure 4 are incorporated to give additional multiplexer mapping capabilities, or if the AND gates 52a-d of Figure 2 are used to provide multiplier mapping capabilities.
- the invention described above provides a logic cell which is optimized for mapping datapath functions, thereby reducing the size of the configuration memory, making it suitable for use in a reconfigurable Systems-on-a-Chip (SoC) application.
- the logic cell can therefore be used as a basic logic block of a datapath optimized embedded FPGA, or used as a reconfigurable functional unit within a processor core. It can also be applied to the implementation of traditional stand-alone FPGAs. Furthermore, it can also be used for the implementation of parametrisable ALUs, and has the advantage of requiring less configuration memory and being configurable to provide more flexibility, i.e. the additional possibility of mapping multiplexers and subtraction and/or multiplier functions.
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/545,643 US7271617B2 (en) | 2003-02-19 | 2004-02-12 | Electronic circuit with array of programmable logic cells |
EP04710453A EP1597825B1 (en) | 2003-02-19 | 2004-02-12 | Electronic circuit with array of programmable logic cells |
DE602004006841T DE602004006841T2 (en) | 2003-02-19 | 2004-02-12 | ELECTRONIC CIRCUIT WITH A FIELD OF PROGRAMMABLE LOGIC CELLS |
JP2006502586A JP2006518143A (en) | 2003-02-19 | 2004-02-12 | Electronic circuit having an array of programmable logic cells |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP03100383.3 | 2003-02-19 | ||
EP03100383 | 2003-02-19 |
Publications (2)
Publication Number | Publication Date |
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WO2004075403A2 true WO2004075403A2 (en) | 2004-09-02 |
WO2004075403A3 WO2004075403A3 (en) | 2004-11-04 |
Family
ID=32892951
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/IB2004/050108 WO2004075403A2 (en) | 2003-02-19 | 2004-02-12 | Electronic circuit with array of programmable logic cells |
Country Status (9)
Country | Link |
---|---|
US (1) | US7271617B2 (en) |
EP (1) | EP1597825B1 (en) |
JP (1) | JP2006518143A (en) |
KR (1) | KR101067727B1 (en) |
CN (1) | CN100576355C (en) |
AT (1) | ATE364260T1 (en) |
DE (1) | DE602004006841T2 (en) |
TW (1) | TW200505163A (en) |
WO (1) | WO2004075403A2 (en) |
Cited By (2)
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WO2006122746A2 (en) * | 2005-05-16 | 2006-11-23 | Panasonic Europe Ltd. | Loosely-biased heterogeneous reconfigurable arrays |
US7471643B2 (en) | 2002-07-01 | 2008-12-30 | Panasonic Corporation | Loosely-biased heterogeneous reconfigurable arrays |
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EP1854035A1 (en) * | 2006-02-28 | 2007-11-14 | Mentor Graphics Corporation | Memory-based trigger generation scheme in an emulation environment |
US9450585B2 (en) | 2011-04-20 | 2016-09-20 | Microchip Technology Incorporated | Selecting four signals from sixteen inputs |
US20120268162A1 (en) * | 2011-04-21 | 2012-10-25 | Microchip Technology Incorporated | Configurable logic cells |
CN103257842B (en) * | 2012-02-17 | 2016-05-04 | 京微雅格(北京)科技有限公司 | A kind of method and a kind of adder of addition carry information output |
JP6483402B2 (en) * | 2013-11-01 | 2019-03-13 | 株式会社半導体エネルギー研究所 | Storage device and electronic apparatus having storage device |
CN103580678B (en) * | 2013-11-04 | 2016-08-17 | 复旦大学 | A kind of high-performance lut circuits based on FGPA |
JP2015231205A (en) * | 2014-06-06 | 2015-12-21 | 国立大学法人静岡大学 | Field programmable gate array, field programmable gate array development tool, and field programmable gate array development method |
CN105589981B (en) * | 2014-10-22 | 2019-04-09 | 京微雅格(北京)科技有限公司 | The process mapping method of the adder of optimization layout structure based on FPGA |
US9954533B2 (en) * | 2014-12-16 | 2018-04-24 | Samsung Electronics Co., Ltd. | DRAM-based reconfigurable logic |
CN106528920B (en) * | 2016-09-27 | 2019-07-26 | 京微齐力(北京)科技有限公司 | A kind of process mapping method cascading look-up table |
CN107885485B (en) * | 2017-11-08 | 2021-07-06 | 无锡中微亿芯有限公司 | Programmable logic unit structure for realizing rapid addition based on carry look ahead |
CN108182303B (en) * | 2017-12-13 | 2020-08-28 | 京微齐力(北京)科技有限公司 | Programmable device structure based on mixed function memory unit |
KR101986206B1 (en) * | 2018-01-03 | 2019-06-05 | 연세대학교 산학협력단 | Lookup Table Circuit Having Variable Input And Output Structure Using Nonvolatile Memory Element |
US10482209B1 (en) | 2018-08-06 | 2019-11-19 | HLS Logix LLC | Field programmable operation block array |
CN109992255B (en) * | 2019-03-07 | 2022-06-24 | 中科亿海微电子科技(苏州)有限公司 | Dual-output lookup table with carry chain structure and programmable logic unit |
CN114489563B (en) * | 2021-12-13 | 2023-08-29 | 深圳市紫光同创电子有限公司 | Circuit structure |
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- 2004-02-12 WO PCT/IB2004/050108 patent/WO2004075403A2/en active IP Right Grant
- 2004-02-12 CN CN200480004650A patent/CN100576355C/en not_active Expired - Lifetime
- 2004-02-12 JP JP2006502586A patent/JP2006518143A/en not_active Withdrawn
- 2004-02-12 US US10/545,643 patent/US7271617B2/en not_active Expired - Lifetime
- 2004-02-12 EP EP04710453A patent/EP1597825B1/en not_active Expired - Lifetime
- 2004-02-12 KR KR1020057015160A patent/KR101067727B1/en active IP Right Grant
- 2004-02-12 AT AT04710453T patent/ATE364260T1/en not_active IP Right Cessation
- 2004-02-12 DE DE602004006841T patent/DE602004006841T2/en not_active Expired - Lifetime
- 2004-02-16 TW TW093103632A patent/TW200505163A/en unknown
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US7461234B2 (en) | 2002-07-01 | 2008-12-02 | Panasonic Corporation | Loosely-biased heterogeneous reconfigurable arrays |
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DE602004006841D1 (en) | 2007-07-19 |
EP1597825B1 (en) | 2007-06-06 |
JP2006518143A (en) | 2006-08-03 |
WO2004075403A3 (en) | 2004-11-04 |
TW200505163A (en) | 2005-02-01 |
KR20050106014A (en) | 2005-11-08 |
CN1751361A (en) | 2006-03-22 |
US20060158218A1 (en) | 2006-07-20 |
DE602004006841T2 (en) | 2008-02-07 |
US7271617B2 (en) | 2007-09-18 |
KR101067727B1 (en) | 2011-09-28 |
EP1597825A2 (en) | 2005-11-23 |
ATE364260T1 (en) | 2007-06-15 |
CN100576355C (en) | 2009-12-30 |
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