WO2004075403A3 - Electronic circuit with array of programmable logic cells - Google Patents

Electronic circuit with array of programmable logic cells

Info

Publication number
WO2004075403A3
WO2004075403A3 PCT/IB2004/050108 IB2004050108W WO2004075403A3 WO 2004075403 A3 WO2004075403 A3 WO 2004075403A3 IB 2004050108 W IB2004050108 W IB 2004050108W WO 2004075403 A3 WO2004075403 A3 WO 2004075403A3
Authority
WO
WIPO (PCT)
Prior art keywords
programmable logic
logic units
mode
bit operand
electronic circuit
Prior art date
Application number
PCT/IB2004/050108
Other languages
French (fr)
Other versions
WO2004075403A2 (en
Inventor
Katarzyna Leijten-Nowak
Original Assignee
Koninkl Philips Electronics Nv
Katarzyna Leijten-Nowak
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv, Katarzyna Leijten-Nowak filed Critical Koninkl Philips Electronics Nv
Priority to EP04710453A priority Critical patent/EP1597825B1/en
Priority to JP2006502586A priority patent/JP2006518143A/en
Priority to DE602004006841T priority patent/DE602004006841T2/en
Priority to US10/545,643 priority patent/US7271617B2/en
Publication of WO2004075403A2 publication Critical patent/WO2004075403A2/en
Publication of WO2004075403A3 publication Critical patent/WO2004075403A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • G06F7/503—Half or full adders, i.e. basic adder cells for one denomination using carry switching, i.e. the incoming carry being connected directly, or only via an inverter, to the carry output under control of a carry propagate signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1737—Controllable logic circuits using multiplexers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/527—Multiplying only in serial-parallel fashion, i.e. one operand being entered serially and the other in parallel
    • G06F7/5272—Multiplying only in serial-parallel fashion, i.e. one operand being entered serially and the other in parallel with row wise addition of partial products

Abstract

An electronic circuit has a programmable logic cell with a plurality of programmable logic units that are capable of being configured to operate in a multi-bit operand mode and a multiplexing mode. The programmable logic units are coupled in parallel between an input circuit and an output circuit. In a multi-bit operand processing mode the input circuit is configured to supply logic input signals from different ones of the logic inputs to the programmable logic units. The programmable logic units are coupled to successive positions along a carry chain at least in the multi-bit operand mode, so as to process carry signals from the carry chain. An output circuit passes outputs from the programmable logic units in parallel in the multi-bit operand mode. The programmable logic units have look-up tables which share the same configuration bits. The programmable logic units can also have multiplexers for passing one of the received input signals when configured to operate in a multiplexing mode of operation.
PCT/IB2004/050108 2003-02-19 2004-02-12 Electronic circuit with array of programmable logic cells WO2004075403A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP04710453A EP1597825B1 (en) 2003-02-19 2004-02-12 Electronic circuit with array of programmable logic cells
JP2006502586A JP2006518143A (en) 2003-02-19 2004-02-12 Electronic circuit having an array of programmable logic cells
DE602004006841T DE602004006841T2 (en) 2003-02-19 2004-02-12 ELECTRONIC CIRCUIT WITH A FIELD OF PROGRAMMABLE LOGIC CELLS
US10/545,643 US7271617B2 (en) 2003-02-19 2004-02-12 Electronic circuit with array of programmable logic cells

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP03100383.3 2003-02-19
EP03100383 2003-02-19

Publications (2)

Publication Number Publication Date
WO2004075403A2 WO2004075403A2 (en) 2004-09-02
WO2004075403A3 true WO2004075403A3 (en) 2004-11-04

Family

ID=32892951

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2004/050108 WO2004075403A2 (en) 2003-02-19 2004-02-12 Electronic circuit with array of programmable logic cells

Country Status (9)

Country Link
US (1) US7271617B2 (en)
EP (1) EP1597825B1 (en)
JP (1) JP2006518143A (en)
KR (1) KR101067727B1 (en)
CN (1) CN100576355C (en)
AT (1) ATE364260T1 (en)
DE (1) DE602004006841T2 (en)
TW (1) TW200505163A (en)
WO (1) WO2004075403A2 (en)

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US7461234B2 (en) * 2002-07-01 2008-12-02 Panasonic Corporation Loosely-biased heterogeneous reconfigurable arrays
US7471643B2 (en) 2002-07-01 2008-12-30 Panasonic Corporation Loosely-biased heterogeneous reconfigurable arrays
WO2007098804A1 (en) * 2006-02-28 2007-09-07 Mentor Graphics Corp. Memory-based trigger generation scheme in an emulation environment
US9450585B2 (en) 2011-04-20 2016-09-20 Microchip Technology Incorporated Selecting four signals from sixteen inputs
US20120268162A1 (en) * 2011-04-21 2012-10-25 Microchip Technology Incorporated Configurable logic cells
CN103257842B (en) * 2012-02-17 2016-05-04 京微雅格（北京）科技有限公司 A kind of method and a kind of adder of addition carry information output
US9515656B2 (en) * 2013-11-01 2016-12-06 Semiconductor Energy Laboratory Co., Ltd. Reconfigurable circuit, storage device, and electronic device including storage device
CN103580678B (en) * 2013-11-04 2016-08-17 复旦大学 A kind of high-performance lut circuits based on FGPA
JP2015231205A (en) * 2014-06-06 2015-12-21 国立大学法人静岡大学 Field programmable gate array, field programmable gate array development tool, and field programmable gate array development method
CN105589981B (en) * 2014-10-22 2019-04-09 京微雅格（北京）科技有限公司 The process mapping method of the adder of optimization layout structure based on FPGA
US9954533B2 (en) * 2014-12-16 2018-04-24 Samsung Electronics Co., Ltd. DRAM-based reconfigurable logic
CN106528920B (en) * 2016-09-27 2019-07-26 京微齐力(北京)科技有限公司 A kind of process mapping method cascading look-up table
CN107885485B (en) * 2017-11-08 2021-07-06 无锡中微亿芯有限公司 Programmable logic unit structure for realizing rapid addition based on carry look ahead
CN108182303B (en) * 2017-12-13 2020-08-28 京微齐力(北京)科技有限公司 Programmable device structure based on mixed function memory unit
KR101986206B1 (en) * 2018-01-03 2019-06-05 연세대학교 산학협력단 Lookup Table Circuit Having Variable Input And Output Structure Using Nonvolatile Memory Element
US10482209B1 (en) 2018-08-06 2019-11-19 HLS Logix LLC Field programmable operation block array
CN109992255B (en) * 2019-03-07 2022-06-24 中科亿海微电子科技（苏州）有限公司 Dual-output lookup table with carry chain structure and programmable logic unit
CN114489563B (en) * 2021-12-13 2023-08-29 深圳市紫光同创电子有限公司 Circuit structure

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5546018A (en) * 1993-09-02 1996-08-13 Xilinx, Inc. Fast carry structure with synchronous input
US5920202A (en) * 1997-02-26 1999-07-06 Xilinx, Inc. Configurable logic element with ability to evaluate five and six input functions
US6278290B1 (en) * 1999-08-13 2001-08-21 Xilinx, Inc. Method and circuit for operating programmable logic devices during power-up and stand-by modes
US6288570B1 (en) * 1993-09-02 2001-09-11 Xilinx, Inc. Logic structure and circuit for fast carry

Family Cites Families (9)

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US6427156B1 (en) * 1997-01-21 2002-07-30 Xilinx, Inc. Configurable logic block with AND gate for efficient multiplication in FPGAS
US5963050A (en) * 1997-02-26 1999-10-05 Xilinx, Inc. Configurable logic element with fast feedback paths
US5889411A (en) * 1997-02-26 1999-03-30 Xilinx, Inc. FPGA having logic element carry chains capable of generating wide XOR functions
US6157209A (en) * 1998-12-18 2000-12-05 Xilinx, Inc. Loadable up-down counter with asynchronous reset
US6466052B1 (en) * 2001-05-15 2002-10-15 Xilinx, Inc. Implementing wide multiplexers in an FPGA using a horizontal chain structure
US6617876B1 (en) * 2002-02-01 2003-09-09 Xilinx, Inc. Structures and methods for distributing high-fanout signals in FPGAs using carry multiplexers
US6937064B1 (en) * 2002-10-24 2005-08-30 Altera Corporation Versatile logic element and logic array block
US7196541B2 (en) * 2003-02-19 2007-03-27 Koninklijke Philips Electronics N.V. Electronic circuit with array of programmable logic cells
US7193433B1 (en) * 2005-06-14 2007-03-20 Xilinx, Inc. Programmable logic block having lookup table with partial output signal driving carry multiplexer

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5546018A (en) * 1993-09-02 1996-08-13 Xilinx, Inc. Fast carry structure with synchronous input
US6288570B1 (en) * 1993-09-02 2001-09-11 Xilinx, Inc. Logic structure and circuit for fast carry
US5920202A (en) * 1997-02-26 1999-07-06 Xilinx, Inc. Configurable logic element with ability to evaluate five and six input functions
US6278290B1 (en) * 1999-08-13 2001-08-21 Xilinx, Inc. Method and circuit for operating programmable logic devices during power-up and stand-by modes

Also Published As

Publication number Publication date
TW200505163A (en) 2005-02-01
EP1597825A2 (en) 2005-11-23
CN1751361A (en) 2006-03-22
EP1597825B1 (en) 2007-06-06
DE602004006841T2 (en) 2008-02-07
CN100576355C (en) 2009-12-30
US7271617B2 (en) 2007-09-18
KR20050106014A (en) 2005-11-08
JP2006518143A (en) 2006-08-03
DE602004006841D1 (en) 2007-07-19
WO2004075403A2 (en) 2004-09-02
US20060158218A1 (en) 2006-07-20
KR101067727B1 (en) 2011-09-28
ATE364260T1 (en) 2007-06-15

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