WO2004077528A3 - A very small pin count ic tester - Google Patents

A very small pin count ic tester Download PDF

Info

Publication number
WO2004077528A3
WO2004077528A3 PCT/US2004/005716 US2004005716W WO2004077528A3 WO 2004077528 A3 WO2004077528 A3 WO 2004077528A3 US 2004005716 W US2004005716 W US 2004005716W WO 2004077528 A3 WO2004077528 A3 WO 2004077528A3
Authority
WO
WIPO (PCT)
Prior art keywords
tester
dut
test
over
sbs
Prior art date
Application number
PCT/US2004/005716
Other languages
French (fr)
Other versions
WO2004077528A2 (en
Inventor
Burnell G West
Original Assignee
Nptest Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nptest Inc filed Critical Nptest Inc
Publication of WO2004077528A2 publication Critical patent/WO2004077528A2/en
Publication of WO2004077528A3 publication Critical patent/WO2004077528A3/en

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31928—Formatter
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31922—Timing generation or clock distribution
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31924—Voltage or current aspects, e.g. driver, receiver
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31926—Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing

Abstract

The present invention provides a method and system for testing a semiconductor device under test (DUT), such as an IC, with the help of a tester. A clock generator in the tester generates a clock signal that is sent over to the DUT on a clock signal line. Prior to an actual test, transmission and reception of data between the tester and the DUT, is synchronized with the clock signals. The invention utilizes simultaneous bi-directional signaling (SBS) for simultaneously transmitting and receiving test related data between the tester and the DUT over a single transmission line. The DUT replies with response signals corresponding to these test related data over the same transmission line. The use of SBS reduces the time required for the test, the number of pins and hence, overall cost and complexity of the testing process involved with the test.
PCT/US2004/005716 2003-02-27 2004-02-26 A very small pin count ic tester WO2004077528A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/376,025 2003-02-27
US10/376,025 US20040187049A1 (en) 2003-02-27 2003-02-27 Very small pin count IC tester

Publications (2)

Publication Number Publication Date
WO2004077528A2 WO2004077528A2 (en) 2004-09-10
WO2004077528A3 true WO2004077528A3 (en) 2005-02-10

Family

ID=32926281

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/005716 WO2004077528A2 (en) 2003-02-27 2004-02-26 A very small pin count ic tester

Country Status (3)

Country Link
US (1) US20040187049A1 (en)
TW (1) TWI237701B (en)
WO (1) WO2004077528A2 (en)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4197657B2 (en) * 2004-04-01 2008-12-17 株式会社アドバンテスト Test apparatus and setting method
US7355384B2 (en) * 2004-04-08 2008-04-08 International Business Machines Corporation Apparatus, method, and computer program product for monitoring and controlling a microcomputer using a single existing pin
US7336066B2 (en) * 2004-05-21 2008-02-26 Credence Systems Corporation Reduced pin count test method and apparatus
US7818641B2 (en) 2006-10-18 2010-10-19 Texas Instruments Incorporated Interface to full and reduce pin JTAG devices
US7773531B2 (en) * 2008-07-10 2010-08-10 Litepoint Corporation Method for testing data packet transceiver using loop back packet generation
TWI452311B (en) * 2009-08-24 2014-09-11 Hon Hai Prec Ind Co Ltd Testing device for surface mounted memory connector
US8305099B2 (en) * 2010-08-31 2012-11-06 Nxp B.V. High speed full duplex test interface
US9077535B2 (en) 2013-03-15 2015-07-07 Litepoint Corporation System and method for testing a radio frequency multiple-input multiple-output data packet transceiver while forcing fewer data streams
US8885483B2 (en) * 2013-03-15 2014-11-11 Litepoint Corporation System and method for testing a data packet signal transceiver
US9791511B2 (en) 2013-03-15 2017-10-17 Teradyne, Inc. Method and apparatus for low latency communication in an automatic testing system
JP6110191B2 (en) * 2013-04-08 2017-04-05 日置電機株式会社 Inspection device and inspection processing device
US9003253B2 (en) * 2013-08-21 2015-04-07 Litepoint Corporation Method for testing data packet signal transceiver using coordinated transmitted data packet signal power
CN112763888A (en) * 2019-11-04 2021-05-07 中兴通讯股份有限公司 Link detection method and device, electronic equipment and computer readable medium
US20230204662A1 (en) * 2021-12-28 2023-06-29 Advanced Micro Devices Products (China) Co. Ltd., On-chip distribution of test data for multiple dies

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6128754A (en) * 1997-11-24 2000-10-03 Schlumberger Technologies, Inc. Tester having event generation circuit for acquiring waveform by supplying strobe events for waveform acquisition rather than using strobe events specified by the test program
US6157200A (en) * 1996-11-15 2000-12-05 Advantest Corporation Integrated circuit device tester
US6219811B1 (en) * 1993-04-09 2001-04-17 International Business Machines Corporation Test circuit and method for interconnect testing of chips
US6275023B1 (en) * 1999-02-03 2001-08-14 Hitachi Electronics Engineering Co., Ltd. Semiconductor device tester and method for testing semiconductor device
US6462996B2 (en) * 1995-06-21 2002-10-08 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit device having internal synchronizing circuit responsive to test mode signal
US6684362B1 (en) * 1999-02-18 2004-01-27 International Business Machines Corporation Method and apparatus for connecting manufacturing test interface to a global serial bus including an I2 c bus
US6735731B2 (en) * 2001-03-09 2004-05-11 International Business Machines Corporation Architecture for built-in self-test of parallel optical transceivers

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5115437A (en) * 1990-03-02 1992-05-19 General Electric Company Internal test circuitry for integrated circuits using token passing to select testing ports
US5124990A (en) * 1990-05-08 1992-06-23 Caterpillar Inc. Diagnostic hardware for serial datalink
JPH06242181A (en) * 1992-11-23 1994-09-02 Texas Instr Inc <Ti> Equipment and method for testing integrated circuit

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6219811B1 (en) * 1993-04-09 2001-04-17 International Business Machines Corporation Test circuit and method for interconnect testing of chips
US6462996B2 (en) * 1995-06-21 2002-10-08 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit device having internal synchronizing circuit responsive to test mode signal
US6157200A (en) * 1996-11-15 2000-12-05 Advantest Corporation Integrated circuit device tester
US6128754A (en) * 1997-11-24 2000-10-03 Schlumberger Technologies, Inc. Tester having event generation circuit for acquiring waveform by supplying strobe events for waveform acquisition rather than using strobe events specified by the test program
US6275023B1 (en) * 1999-02-03 2001-08-14 Hitachi Electronics Engineering Co., Ltd. Semiconductor device tester and method for testing semiconductor device
US6684362B1 (en) * 1999-02-18 2004-01-27 International Business Machines Corporation Method and apparatus for connecting manufacturing test interface to a global serial bus including an I2 c bus
US6735731B2 (en) * 2001-03-09 2004-05-11 International Business Machines Corporation Architecture for built-in self-test of parallel optical transceivers

Also Published As

Publication number Publication date
WO2004077528A2 (en) 2004-09-10
TW200428002A (en) 2004-12-16
US20040187049A1 (en) 2004-09-23
TWI237701B (en) 2005-08-11

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