WO2004080149A3 - System and method for dymanic ordering in a network processor - Google Patents

System and method for dymanic ordering in a network processor Download PDF

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Publication number
WO2004080149A3
WO2004080149A3 PCT/US2004/005420 US2004005420W WO2004080149A3 WO 2004080149 A3 WO2004080149 A3 WO 2004080149A3 US 2004005420 W US2004005420 W US 2004005420W WO 2004080149 A3 WO2004080149 A3 WO 2004080149A3
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WO
WIPO (PCT)
Prior art keywords
order
threads
packets
thread
processing system
Prior art date
Application number
PCT/US2004/005420
Other languages
French (fr)
Other versions
WO2004080149A2 (en
Inventor
Kenneth H Potter Jr
Original Assignee
Cisco Tech Ind
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cisco Tech Ind filed Critical Cisco Tech Ind
Priority to EP04713797.1A priority Critical patent/EP1602030B1/en
Priority to AU2004220640A priority patent/AU2004220640B2/en
Priority to CA2517156A priority patent/CA2517156C/en
Publication of WO2004080149A2 publication Critical patent/WO2004080149A2/en
Publication of WO2004080149A3 publication Critical patent/WO2004080149A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/45—Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Multi Processors (AREA)

Abstract

A system and method maintains order among a plurality of threads in a multi-threaded processing system. The processing system which may be disposed at an intermediate network device, has a plurality of processors each supporting a plurality of threads. The ordering system includes a dispatcher that assigns work, such as the processing of received packets to free threads, an order manager that keeps track of the relative order of the threads, and a thread client associated with each thread for enforcing the determined order. Packets to be processed by the processing system are assigned to an initial order group by the order manager based on a selected attribute, and those packets sharing the same attribute value are assigned to the same order group. During processing, a thread may request reassignment to other order groups in response to other attributes of the packets. The order manager preferably manages the switching of threads among order groups and ensures that the threads within each order group process their packets in order.
PCT/US2004/005420 2003-03-07 2004-02-23 System and method for dymanic ordering in a network processor WO2004080149A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP04713797.1A EP1602030B1 (en) 2003-03-07 2004-02-23 System and method for dynamic ordering in a network processor
AU2004220640A AU2004220640B2 (en) 2003-03-07 2004-02-23 System and method for dymanic ordering in a network processor
CA2517156A CA2517156C (en) 2003-03-07 2004-02-23 System and method for dynamic ordering in a network processor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/383,901 2003-03-07
US10/383,901 US7039914B2 (en) 2003-03-07 2003-03-07 Message processing in network forwarding engine by tracking order of assigned thread in order group

Publications (2)

Publication Number Publication Date
WO2004080149A2 WO2004080149A2 (en) 2004-09-23
WO2004080149A3 true WO2004080149A3 (en) 2005-07-28

Family

ID=32987276

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/005420 WO2004080149A2 (en) 2003-03-07 2004-02-23 System and method for dymanic ordering in a network processor

Country Status (6)

Country Link
US (2) US7039914B2 (en)
EP (1) EP1602030B1 (en)
CN (1) CN100392602C (en)
AU (1) AU2004220640B2 (en)
CA (1) CA2517156C (en)
WO (1) WO2004080149A2 (en)

Families Citing this family (69)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8037224B2 (en) 2002-10-08 2011-10-11 Netlogic Microsystems, Inc. Delegating network processor operations to star topology serial bus interfaces
US9088474B2 (en) 2002-10-08 2015-07-21 Broadcom Corporation Advanced processor with interfacing messaging network to a CPU
US8176298B2 (en) 2002-10-08 2012-05-08 Netlogic Microsystems, Inc. Multi-core multi-threaded processing systems with instruction reordering in an in-order pipeline
US8478811B2 (en) 2002-10-08 2013-07-02 Netlogic Microsystems, Inc. Advanced processor with credit based scheme for optimal packet flow in a multi-processor system on a chip
US7984268B2 (en) 2002-10-08 2011-07-19 Netlogic Microsystems, Inc. Advanced processor scheduling in a multithreaded system
US7334086B2 (en) 2002-10-08 2008-02-19 Rmi Corporation Advanced processor with system on a chip interconnect technology
US7924828B2 (en) 2002-10-08 2011-04-12 Netlogic Microsystems, Inc. Advanced processor with mechanism for fast packet queuing operations
US7346757B2 (en) 2002-10-08 2008-03-18 Rmi Corporation Advanced processor translation lookaside buffer management in a multithreaded system
US7627721B2 (en) 2002-10-08 2009-12-01 Rmi Corporation Advanced processor with cache coherency
US7961723B2 (en) * 2002-10-08 2011-06-14 Netlogic Microsystems, Inc. Advanced processor with mechanism for enforcing ordering between information sent on two independent networks
US8015567B2 (en) 2002-10-08 2011-09-06 Netlogic Microsystems, Inc. Advanced processor with mechanism for packet distribution at high line rate
US7509378B2 (en) * 2003-03-11 2009-03-24 Bea Systems, Inc. System and method for message ordering in a message oriented network
CA2463228C (en) 2003-04-04 2012-06-26 Evertz Microsystems Ltd. Apparatus, systems and methods for packet based transmission of multiple data signals
US7379460B2 (en) * 2003-06-06 2008-05-27 Intel Corporation Packet processing system
US20050047439A1 (en) * 2003-08-26 2005-03-03 Madajczak Tomasz Bogdan System to process packets according to an assigned sequence number
US7672302B2 (en) * 2003-11-21 2010-03-02 Samsung Electronics Co., Ltd. Router using switching-before-routing packet processing and method of operation
US7185309B1 (en) 2004-01-30 2007-02-27 Xilinx, Inc. Method and apparatus for application-specific programmable memory architecture and interconnection network on a chip
US7552042B1 (en) 2004-01-30 2009-06-23 Xilinx, Inc. Method for message processing on a programmable logic device
US7823162B1 (en) 2004-01-30 2010-10-26 Xilinx, Inc. Thread circuits and a broadcast channel in programmable logic
US7770179B1 (en) 2004-01-30 2010-08-03 Xilinx, Inc. Method and apparatus for multithreading on a programmable logic device
US7719540B2 (en) * 2004-03-31 2010-05-18 Intel Corporation Render-cache controller for multithreading, multi-core graphics processor
US20060041705A1 (en) * 2004-08-20 2006-02-23 International Business Machines Corporation System and method for arbitration between shared peripheral core devices in system on chip architectures
US7913206B1 (en) * 2004-09-16 2011-03-22 Cadence Design Systems, Inc. Method and mechanism for performing partitioning of DRC operations
US8250131B1 (en) * 2004-12-08 2012-08-21 Cadence Design Systems, Inc. Method and apparatus for managing a distributed computing environment
US7844973B1 (en) * 2004-12-09 2010-11-30 Oracle America, Inc. Methods and apparatus providing non-blocking access to a resource
US7564847B2 (en) * 2004-12-13 2009-07-21 Intel Corporation Flow assignment
US7577438B2 (en) 2005-04-25 2009-08-18 Interdigital Technology Corporation Method and system for efficient addressing and power savings in wireless systems
US7904852B1 (en) 2005-09-12 2011-03-08 Cadence Design Systems, Inc. Method and system for implementing parallel processing of electronic design automation tools
US10554534B1 (en) * 2005-09-23 2020-02-04 Chicago Mercantile Exchange Inc. Clearing message broker system messaging gateway
US7907614B2 (en) * 2005-11-11 2011-03-15 Broadcom Corporation Fast block acknowledgment generation in a wireless environment
US7809009B2 (en) * 2006-02-21 2010-10-05 Cisco Technology, Inc. Pipelined packet switching and queuing architecture
US7751336B2 (en) * 2006-06-08 2010-07-06 Cisco Technology, Inc. Technique for efficiently avoiding transient routing disturbances in link state routing protocols with link state packet fragmentation
US20070294693A1 (en) * 2006-06-16 2007-12-20 Microsoft Corporation Scheduling thread execution among a plurality of processors based on evaluation of memory access data
US8041929B2 (en) * 2006-06-16 2011-10-18 Cisco Technology, Inc. Techniques for hardware-assisted multi-threaded processing
US8448096B1 (en) 2006-06-30 2013-05-21 Cadence Design Systems, Inc. Method and system for parallel processing of IC design layouts
US8639655B2 (en) * 2006-08-31 2014-01-28 Red Hat, Inc. Dedicating threads to classes of LDAP service
US7734658B2 (en) * 2006-08-31 2010-06-08 Red Hat, Inc. Priority queue to determine order of service for LDAP requests
US8010966B2 (en) * 2006-09-27 2011-08-30 Cisco Technology, Inc. Multi-threaded processing using path locks
WO2008101756A1 (en) * 2007-02-20 2008-08-28 International Business Machines Corporation Method and system for concurrent message processing
US8544014B2 (en) * 2007-07-24 2013-09-24 Microsoft Corporation Scheduling threads in multi-core systems
US8327363B2 (en) * 2007-07-24 2012-12-04 Microsoft Corporation Application compatibility in multi-core systems
US8379647B1 (en) * 2007-10-23 2013-02-19 Juniper Networks, Inc. Sequencing packets from multiple threads
TWI371695B (en) * 2007-12-11 2012-09-01 Inst Information Industry A priority-based data message publish method and system according to a data message chain
US8381226B2 (en) * 2008-02-07 2013-02-19 Nec Laboratories America, Inc. System and method for monotonic partial order reduction
US9596324B2 (en) 2008-02-08 2017-03-14 Broadcom Corporation System and method for parsing and allocating a plurality of packets to processor core threads
JP5081847B2 (en) * 2009-02-20 2012-11-28 株式会社日立製作所 Packet processing apparatus and packet processing method using multiprocessor
FR2942556B1 (en) * 2009-02-24 2011-03-25 Commissariat Energie Atomique ALLOCATION AND CONTROL UNIT
US9461930B2 (en) 2009-04-27 2016-10-04 Intel Corporation Modifying data streams without reordering in a multi-thread, multi-flow network processor
US8505013B2 (en) * 2010-03-12 2013-08-06 Lsi Corporation Reducing data read latency in a network communications processor architecture
US8935483B2 (en) * 2009-04-27 2015-01-13 Lsi Corporation Concurrent, coherent cache access for multiple threads in a multi-core, multi-thread network processor
US8514874B2 (en) * 2010-03-12 2013-08-20 Lsi Corporation Thread synchronization in a multi-thread network communications processor architecture
US8868889B2 (en) 2010-03-12 2014-10-21 Lsi Corporation Instruction breakpoints in a multi-core, multi-thread network communications processor architecture
US9444757B2 (en) 2009-04-27 2016-09-13 Intel Corporation Dynamic configuration of processing modules in a network communications processor architecture
US8910171B2 (en) * 2009-04-27 2014-12-09 Lsi Corporation Thread synchronization in a multi-thread network communications processor architecture
US8537832B2 (en) * 2010-03-12 2013-09-17 Lsi Corporation Exception detection and thread rescheduling in a multi-core, multi-thread network processor
JP5452125B2 (en) * 2009-08-11 2014-03-26 クラリオン株式会社 Data processing apparatus and data processing method
TWI512504B (en) * 2009-11-16 2015-12-11 Inst Information Industry Candidate key retrieving apparatus, candidate key retrieving method and computer program product thereof
US8537831B2 (en) * 2010-02-17 2013-09-17 Alcatel Lucent Method and system for common group action filtering in telecom network environments
US8593960B2 (en) 2010-06-30 2013-11-26 Intel Corporation Providing a bufferless transport method for multi-dimensional mesh topology
GB2483737A (en) * 2010-09-13 2012-03-21 Tata Consultancy Services Ltd Workflow scheduler for server cluster with blocking assignment of order sensitive flows and non blocking assignment of other flows
US8756613B2 (en) 2011-09-23 2014-06-17 International Business Machines Corporation Scalable, parallel processing of messages while enforcing custom sequencing criteria
US8811401B2 (en) * 2012-06-21 2014-08-19 Breakingpoint Systems, Inc. Binding of network flows to process threads
US8929379B2 (en) 2012-06-21 2015-01-06 Breakingpoint Systems, Inc. High-speed CLD-based internal packet routing
US9158595B2 (en) * 2012-10-25 2015-10-13 Nvidia Corporation Hardware scheduling of ordered critical code sections
WO2014070446A2 (en) * 2012-11-02 2014-05-08 Sandia Corporation Method and system for a network mapping service
US9135087B1 (en) * 2012-12-27 2015-09-15 Altera Corporation Workgroup handling in pipelined circuits
US9207978B2 (en) * 2013-10-09 2015-12-08 Wipro Limited Method and system for efficient execution of ordered and unordered tasks in multi-threaded and networked computing
US9437299B2 (en) * 2014-03-31 2016-09-06 Freescale Semiconductor, Inc. Systems and methods for order scope transitions using cam
CN111919202A (en) * 2018-03-31 2020-11-10 美光科技公司 Execution control of a multithreaded self-scheduling reconfigurable computing architecture

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001039430A2 (en) * 1999-11-24 2001-05-31 Leon Garcia Alberto A high-speed, programmable packet scheduler and buffer manager
WO2001048606A2 (en) * 1999-12-28 2001-07-05 Intel Corporation Allocation of data to threads in multi-threaded network processor

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5630128A (en) * 1991-08-09 1997-05-13 International Business Machines Corporation Controlled scheduling of program threads in a multitasking operating system
US5745778A (en) * 1994-01-26 1998-04-28 Data General Corporation Apparatus and method for improved CPU affinity in a multiprocessor system
JP3193240B2 (en) * 1994-09-08 2001-07-30 株式会社東芝 Image processing device
JP3231571B2 (en) * 1994-12-20 2001-11-26 日本電気株式会社 Ordered multi-thread execution method and its execution device
US5870567A (en) * 1996-12-31 1999-02-09 Compaq Computer Corporation Delayed transaction protocol for computer system bus
US5835741A (en) * 1996-12-31 1998-11-10 Compaq Computer Corporation Bus-to-bus bridge in computer system, with fast burst memory range
US6505228B1 (en) * 1998-07-22 2003-01-07 Cisco Technology, Inc. Dynamic determination of execution sequence
US6205465B1 (en) * 1998-07-22 2001-03-20 Cisco Technology, Inc. Component extensible parallel execution of multiple threads assembled from program components specified with partial inter-component sequence information
US6484224B1 (en) * 1999-11-29 2002-11-19 Cisco Technology Inc. Multi-interface symmetric multiprocessor
US6804815B1 (en) 2000-09-18 2004-10-12 Cisco Technology, Inc. Sequence control mechanism for enabling out of order context processing
US6834385B2 (en) * 2001-01-04 2004-12-21 International Business Machines Corporation System and method for utilizing dispatch queues in a multiprocessor data processing system
US6832279B1 (en) 2001-05-17 2004-12-14 Cisco Systems, Inc. Apparatus and technique for maintaining order among requests directed to a same address on an external bus of an intermediate network node
US6757768B1 (en) 2001-05-17 2004-06-29 Cisco Technology, Inc. Apparatus and technique for maintaining order among requests issued over an external bus of an intermediate network node
US6886041B2 (en) * 2001-10-05 2005-04-26 Bea Systems, Inc. System for application server messaging with multiple dispatch pools
US6836808B2 (en) * 2002-02-25 2004-12-28 International Business Machines Corporation Pipelined packet processing
US7379460B2 (en) * 2003-06-06 2008-05-27 Intel Corporation Packet processing system
US20050047439A1 (en) * 2003-08-26 2005-03-03 Madajczak Tomasz Bogdan System to process packets according to an assigned sequence number

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001039430A2 (en) * 1999-11-24 2001-05-31 Leon Garcia Alberto A high-speed, programmable packet scheduler and buffer manager
WO2001048606A2 (en) * 1999-12-28 2001-07-05 Intel Corporation Allocation of data to threads in multi-threaded network processor

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
BUX W ET AL: "TECHNOLOGIES AND BUILDING BLOCKS FOR FAST PACKET FORWARDING", IEEE COMMUNICATIONS MAGAZINE, IEEE SERVICE CENTER. PISCATAWAY, N.J, US, vol. 39, no. 1, 1 January 2001 (2001-01-01), pages 70 - 77, XP001006836, ISSN: 0163-6804 *
HUSTON L: "Selecting an appropriate programming model", COMMSDESIGN, 5 August 2002 (2002-08-05), pages 1 - 3, XP002330882, Retrieved from the Internet <URL:http://www.commsdesign.com/printableArticle/?articleID=16505551> *
MELVIN, S., NEMIROVSKY, M., MUSOLL, E., HUYNH, J., MILITO, R., URDANETA, H., AND SARAF, K.: "A Massively Multithreaded Packet Processor", WORKSHOP ON NETWORK PROCESSORS - NP2 AT 9TH INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE, 8 February 2003 (2003-02-08), pages 1 - 11, XP002330883 *

Also Published As

Publication number Publication date
AU2004220640A1 (en) 2004-09-23
EP1602030B1 (en) 2018-09-12
CN100392602C (en) 2008-06-04
CA2517156C (en) 2011-05-24
WO2004080149A2 (en) 2004-09-23
US20040187112A1 (en) 2004-09-23
CA2517156A1 (en) 2004-09-23
CN1759379A (en) 2006-04-12
US7039914B2 (en) 2006-05-02
US7287255B2 (en) 2007-10-23
AU2004220640B2 (en) 2010-07-08
EP1602030A2 (en) 2005-12-07
US20060200825A1 (en) 2006-09-07

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