WO2004081803A1 - Data processing device and method for transferring data - Google Patents

Data processing device and method for transferring data Download PDF

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Publication number
WO2004081803A1
WO2004081803A1 PCT/IB2004/050197 IB2004050197W WO2004081803A1 WO 2004081803 A1 WO2004081803 A1 WO 2004081803A1 IB 2004050197 W IB2004050197 W IB 2004050197W WO 2004081803 A1 WO2004081803 A1 WO 2004081803A1
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WO
WIPO (PCT)
Prior art keywords
tlie
bus
data
processing device
master
Prior art date
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PCT/IB2004/050197
Other languages
French (fr)
Inventor
Hans-Joachim Gelke
Stefan Marco Koch
Anton Reding
Original Assignee
Koninklijke Philips Electronics N. V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Koninklijke Philips Electronics N. V. filed Critical Koninklijke Philips Electronics N. V.
Priority to US10/548,344 priority Critical patent/US7340553B2/en
Priority to JP2006506673A priority patent/JP4892683B2/en
Priority to EP04716680A priority patent/EP1604288A1/en
Publication of WO2004081803A1 publication Critical patent/WO2004081803A1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
    • G06F13/4059—Coupling between buses using bus bridges where the bridge performs a synchronising function where the synchronisation uses buffers, e.g. for speed matching between buses

Definitions

  • the present invention relates to a data processing device and a method for transferring data fonn a first memory of a first processor system to a second memory of a second processor system.
  • the invention can be used for establisl ing a communication between two or more processors.
  • the invention notably concerns an inter- processor communication between processors that are arranged on the same semiconductor die.
  • the data processing device and the method for transferring data according to the invention generally supports applications using multiple microprocessors, where fast exchange of large blocks of data between the processor cores is necessary.
  • PDAs personal digital assistants
  • networking equipment or general computing equipment where different processor cores share different tasks in a system where data must cross processor boundaries.
  • a typical example is a SmaitCard that has a main processor and a crypto-processor on the same semiconductor die.
  • WAP wireless application protocol
  • SMS short message system
  • integrated circuit cards such as multi-purpose JavaCards, small handheld devices, such as palm top computers or personal digital assistants (PDAs), etc.
  • PDAs personal digital assistants
  • the data processing system comprises a central processing unit, a memory subsystem, a bus for receiving bus transactions for transferring data and a device connected to the bus.
  • This device in turn comprises a bus transaction initiator which generates a bus transaction request, a bus transaction optimizer which generates a plurality of bus transaction requests in response to receiving an original bus transaction request, and wherein these requests comprise a high performance bus transaction request and a low-perfomiance bus transaction request.
  • the device also comprises a bus interface unit, which controls a bus transaction in response to receiving a bus transaction request.
  • a bus interface unit which controls a bus transaction in response to receiving a bus transaction request.
  • USP 6212 590 describes a computer system having an integrated bus bridge design with a delayed transaction arbitration mechanism. This is employed within a laptop computer docked to an expansion base with which a high performance can be obtained.
  • the system comprises a secondary bus bridge device in a portable computer and another secondary bus bridge device in an expansion base to which the portable computer docks.
  • a peripheral in the expansion base may initiate a delayed cycle to read or write data to memory through a primary bus bridge device that also couples to a CPU.
  • Both bus bridge devices include an arbiter for controlling arbitration of a peripheral bus that connects both secondary bridge devices.
  • USP 6 279 087 a system and method for maintaining coherency and improving performance in a bus bridge supporting write posting operations is described.
  • the bridge provides an interface between a microprocessor coupled to a processor bus, a main memory coupled to a memory bus, and a peripheral device coupled to a peripheral bus.
  • the bridge disables posting in certain situations, and flushes posted write transactions before allowing certain read requests to be serviced.
  • a computer system employing optimized delayed transaction arbitration teclmique is described. Disadvantageously, both methods do not allow reading and writing data at the same time.
  • a system for network transmission using a communication coprocessor comprising a microprocessor to implement protocol layer and a microprocessor to manage direct memory access
  • the system for transmitting data between a computer bus and the network includes a general purpose unit connected to the bus and to a network-connected adapter, and further includes a first microprocessor and a unit for transferring frames between the bus and the adapter comprising a dual port memory connected there between.
  • the system further comprises a communication coprocessor connected to the general purpose unit.
  • the communication coprocessor includes a second microprocessor implementing for each comiriunication layer the co ⁇ esponding protocol by providing each frame with control data adapted to the protocol.
  • the second microprocessor is connected to the first microprocessor and the dual port memory.
  • the system includes a third microprocessor providing direct memory access management of data transfer between the second microprocessor and the dual port memory.
  • a disadvantage of this solution is a high latency time for block or single transfers, since the entire data block or word has to be written to the dual port memory first before it can be read out by the opposite processor. During all this time, the processors are occupied with the transfers.
  • Another disadvantage is that firmware is involved in both processor blocks to do the transfers. Transfer functions on both sides must also be coordinated.
  • a further multiprocessor system is described in Hyundai USP 5 916 296.
  • the dual processor automotive control system described therein comprises a host microprocessor with a read only memory (ROM), a random access memory (RAM), a central processing unit (CPU) and a direct memory access (DMA) controller.
  • the system further comprises a knock- control system microprocessor provided with a ROM, RAM, CPU and DMA controller.
  • the host microprocessor and the knock-control system microprocessor are connected by a bi-directional cornmunication line.
  • Hie bi-directional communication line between tl e two DMA controllers does not employ a pipelined buffer.
  • An object of the invention is to provide a data processing device and a method for transferring data form a first processor to a second processor which can exchange data at a time in both directions between both processors.
  • Another object of tlie invention is to transfer data from tl e one processor to the other processor wherein the latency time, this means the time between the intention to send data and the point of time the bus is available for the transfer, is as short as possible.
  • a further object of tlie invention is to optimize the performance of both processor cores. Tlie data transfer from one processor core to tl e other shall not consume processor core performance and thus avoid tlie reduction of the overall performance of a system.
  • Another object of the invention is to avoid a loss of processor and system performance when the processors run at different clock speeds.
  • An object of tlie invention is also to provide a data processing device and a method for transfe ⁇ ing data form a first processor to a second processor which can be used as well as for transferring large blocks of data as also for ttansferring a single word.
  • a further object of the invention is to provide a data processing device and a method for transferring data from a first processor to a second processor wherein the transfer of data to tlie desired location within the subsystem does not influence processor performance.
  • a data processing device with the features according to tlie independent apparatus claim, essentially comprising: a first processing unit linlced to a first bus, a second processing unit linked to a second bus, a first bus master linked to said first bus, a second bus master linlced to said second bus, communication channels linking said first and said second bus masters to each other, and a controller for tlie data transfer between the two bus masters via tlie coinmunication channels.
  • An appropriate method for transferring data form a first processor to a second processor comprises the features lied out in an independent method claim.
  • This method for transferring data from a first memory of a first processor system to a second memory of a second processor system comprises the following steps: the first memory transmits the data via a first bus to a first pipeline controlled by a first bus master with a first clock rate; subsequently, the data are transferred from the first pipeline with the help of a second bus master with a second clock rate via a second bus to tlie second memory.
  • the first and tlie second communication channels in tlie data processing device comprise buffers.
  • tlie data transfer from one processor core to the other processor core is buffered and therefore the performance of tlie quicker processor is not influenced by tlie perfonnance of tlie slower processor. Therefore the data transfer does not reduce tl e overall perfomiance of tlie superior system.
  • each buffer has a first and a second clock input, wherein the first clock input is linlced to tlie first bus master and tlie second clock input is linlced to tlie second bus master.
  • the advantage of this embodiment is, if the processor speeds are significantly different, this is not slowing down tlie faster processor and is not reducing tlie performance of the faster system during tlie data transfer.
  • tlie data can be written into tlie first buffer with tlie clock of tlie first processor and tlie data can be read out from the first buffer with the clock rate of tlie second processor.
  • tlie first bus has a first bus width and tlie second bus has a second bus width and tlie first and H e second communication channels comprise an adapting unit for adapting the bus widths.
  • This has tlie advantage that a data transfer is transparent to tlie software.
  • tlie first bus has one type of byte order and the second bus has the otlier type of byte order.
  • the first and the second communication channels comprise a further adapting unit for adapting tlie byte orders.
  • tlie control unit of the data processing device can comprise an output register for a single data transfer, whose input is connected to tlie first bus.
  • a multiplexer is switched in one of tlie communication channels and connected to tlie slave access output register.
  • Tlie control unit is connected to tlie master for receiving and transmitting control and status signals.
  • tlie control unit of the data processing device comprises an address register generator whose input is connected to the master and whose output is connected to the first bus master, and tlie control unit comprises a further address register generator whose input is connected to the master and whose output is connected to the second bus master.
  • the control unit of tlie data processing device can be equipped so that the addresses are incremented automatically. With that, none of the subsystems are loaded with the generation of addresses. hi a further advantageous embodiment, the control unit of tlie data processing device according to the invention can be equipped so that the addresses are generated in ring buffer mode.
  • control of the data processing device according to tlie invention unit comprises a word counter connected to the first bus.
  • tlie control unit is equipped so that the data transfer can be suspended, if tlie buffer is full. With that a buffer overflow and a from that resulting loss of data can be avoided.
  • tlie control unit is equipped so that the bus access load can be controlled such that the bus access load is kept under a predetermined value.
  • the data processing device can be equipped so that the first processor, which is tlie master, can suspend the data transfer.
  • tlie first bus master is equipped so that it can detect an error regarding address alignment or illegal addresses and forward it to the control unit.
  • the data transfer form the second processor to the first processor comprises tlie following steps: tlie second memory transmits the data via the second bus to a second pipeline with the help of tl e second bus master with the second clock rate. Afterwards tlie data are transferred from tlie second pipeline with tlie help of the first bus master with tlie first clock rate via the first bus to the first memory.
  • the figure shows a block diagram of a data processing device according to the invention.
  • the present invention provides an improvement of data exchange in multiprocessor systems.
  • An embodiment of a two processor system with a local master linlced through pipeliniiig to a remote bus master is shown in tlie figure.
  • the data processing device comprises a first processor A, indicated with tlie reference sign 1, which can be a central processing unit (CPU), and a second processor B, indicated with the reference sign 2, which can be for example a digital signal processor (DSP).
  • the first processor A is linlced via a first bus A, indicated with Uie reference sign 5, to a local bus master 3.
  • the second processor B is linlced via a second bus B, indicated with Hie reference sign 6, to a remote bus master 4.
  • Tlie system also comprises a first memory A linked to the first bus 5 and a second memory B linked to the second bus 6.
  • a first subsystem includes the first processor A, the first bus A, tlie first memory A, and tlie local bus master 3.
  • a second subsystem comprises the second processor B, the second bus B, tlie second memory B and the remote bus master 4.
  • Tlie data transfer is carried out by two communication channels, wherein tlie first communication channel transfers tlie data from the remote bus master 4 to the local bus master 3, and the second communication channel transfers tlie data from the local bus master 3 to tlie remote bus master 4.
  • the first communication channel is also called RX-channel, while the second communication channel is also called TX-channel.
  • the RX-channel comprises a RX pipeline whose input is connected to tlie data output R_data_out of tlie remote bus master 4 and whose data output 7.4 is connected via an adapting unit 20 to the data input L_data_in of tlie local bus master 3.
  • Tlie TX-channel comprises a TX pipeline 8 whose input is connected via a multiplexer 10 and a second adapting unit 21 to the data output L_data_out of the local bus master 3 and whose data output 8.5 is connected to tlie data input R_data_in of the remote bus master 4.
  • the first adapting unit 20 is provided to convert the data delivered from tlie data output R_data_out of tl e remote bus master 4 in a format which is suitable for the local bus master 3. Especially if tlie remote bus master 4 delivers its output data on a data bus with ml lines and the data bus of tlie local bus master has nl lines, the first adapting unit 20 converts the data so that they fit to tlie data bus of tl e local bus master 3.
  • tlie first adapting unit 20 converts the output data R_data_out appropriately. Whether tlie output data R_data_o ⁇ t from tlie remote bus master 4 have to be converted or not is decided by a control unit 9, which is linked to a control input 20.1 of the first adapting unit 20.
  • the second adapting unit 21 is provided to convert the data delivered from tlie data output L_data_out of tlie local bus master 3 in a format which is suitable for tlie remote bus master 4. If tlie local bus master 3 delivers its output data on a data bus with n2 lines whereas tlie data bus of tlie remote bus master has m2 lines tlie second adapting unit 21 converts tlie outgoing data so that they fit to the data bus of the remote bus master 4. If tlie local bus master 3 delivers its output data L_ data_out in a Uttle endian format but the remote bus master 4 needs the data in the big endian format the second adapting unit 21 converts tlie output data L_data_out appropriately.
  • the RX pipeline comprises a first in first out (FIFO) buffer 7 with two clock inputs 7.1 and 7.2.
  • the clock input 7.1 is connected to the remote bus master 4 while the clock input 7.2 is connected to tlie local bus master 3.
  • the buffer 7 is connected via its buffer control input 7.3 to tlie control output of a RX-control unit 11 of tlie control unit 9. hi general, the RX-control unit 11 controls tlie buffer 7.
  • the RX-control unit 11 gets the status of die received data via the buffer 7 over a status line 7.4.
  • the TX pipeline comprises a buffer 8 with two clock inputs 8.1 and 8.2, which is also a first in first out buffer.
  • the first clock input 8.1 of the buffer 8 is connected to the remote bus master 4 while the second clock input 8.2 of tlie buffer 8 is connected to the local bus master 3.
  • the clock of tlie first processor A and the clock of the second processor B are substantially different, this is not slowing down tlie faster processor and is not reducing the perfonnance of the faster subsystem during tlie data transfer, because tlie clock rates of the two processors 1 and 2 are decoupled by tlie buffer 8.
  • the data can be written into the buffer 8 with the clock of the processor A and tlie data can be read out from tlie buffer 8 with the clock of the processor B.
  • the TX-control unit 12 controls the buffer 8.
  • the TX-control unit 11 gets tlie status of the transmitted data via tlie buffer 8 over a status line 8.4.
  • the present invention provides the desired improvement by dedicating the local and the remote bus master 3 and 4 for the two buses 5 and 6 of each processor core 1 and 2. The processor perfonnance is not inhibited since the two bus masters 3 and 4 can do the data transfer during the time tlie processors 1 and 2 do not need tlie buses 5 and 6.
  • Tlie data pipeline 8 transfers the output data L_data_o ⁇ t on the path from tlie local bus master 3 to tlie remote bus master 4 while the data pipeline 7 transfers tlie output data R_data_out on tlie path from tlie remote bus master 4 to tlie local bus master 3. This is particularly beneficial when one of tlie bus masters 3 or 4 is temporarily not available to receive or transmit data to its dedicated bus 5 or 6, due to the bus 5 or 6 being not available or because tlie other bus 5 or 6 is not able to accept data packets in the same rate they are provided due to different subsystem clock speeds. Tlie arcliitecture using the data pipelines 7 and 8 allows that tl e two clock domains run with independent clock speeds.
  • Address registers 13 and 14 which cover the full address range of tlie bus A and the bus B, determine the subsystem address the data is transferred to or from and therefore no further data transfer is necessary. This is because the data can directly be transferred from Uie desired source address location to the desired destination address location.
  • the data processing unit according to the invention is also capable to transfer a single data word at a time, witliout the overhead of prograrnming tl e complete set of registers. This is possible through a slave access data input register 16 and a slave access data output register 17 located on tlie control unit 9 and connected over a control unit bus 19 to tlie bus A.
  • the local bus master 3 serves tlie bus A and is called local bus master because it is connected to tlie same processor A which controls the control unit 9 via a control interface 22.
  • the remote bus master 4 serves the bus B. Both bus masters 3 and 4 can also be named as bus interfaces.
  • the bus A can be a bus with a 16 bit bus width while the bus B can have a 32 bit bus width.
  • Tlie pipelines 7 and 8 serve as buffers if bus A or bus B are not immediately available for receiving or transiirittitig.
  • Writing and reading to and from tlie pipelines 7 and 8 is controlled by the control unit 9. hi parallel to each word transmitted and received over the data pipelines 7 and 8, control and status infoniiation is also transferred to tlie RX-control unit 11 and to the TX- control unit 12, respectively.
  • tlie remote bus master 4 The address for tlie remote bus master 4 is generated by tlie remote bus master 4 itself. Only tlie initial block address, also called start address, is sent from tlie control unit 9 to tlie remote bus master 4. This is to avoid employing a pipeline also for the addresses. Since the addresses are incremental, tlie remote bus master 4 increments the address by itself after each transferred word.
  • the control unit 9 contains registers 13 and 14 for tlie source and destination addresses of tlie data to be transferred to and fro
  • the confrol unit 9 also contains a word counter 15 to determine tlie number of words to be transferred.
  • the control unit 9 further comprises a control and status register 18, which allows the controlling processor A to check the status of the transfers and to enable the data transfers via the control units 11 and 12. Finally the control unit 9 contains a slave access data input register 16 and a slave access data output register 17, which allow the processor A to also do single data transfers witliout using the local bus master 3 on bus A.

Abstract

The data processing device according to the invention comprises a first processing unit (1) linked to a first bus (5), a second processing unit (2) linked to a second bus (6), a first bus master (3) linked to the first bus (5), a second bus master (4) linked to the second bus (6), a first and a second communication channel (7, 20, 8, 21) linking the first and the second bus master (3, 4) with each other, and a control unit (9) controlling the data transfer between the first and the second bus master (3, 4) via the first and the second communication channel (7, 20, 8, 21).

Description

Data processing device and method for transferring data
The present invention relates to a data processing device and a method for transferring data fonn a first memory of a first processor system to a second memory of a second processor system. For example, the invention can be used for establisl ing a communication between two or more processors. The invention notably concerns an inter- processor communication between processors that are arranged on the same semiconductor die.
The data processing device and the method for transferring data according to the invention generally supports applications using multiple microprocessors, where fast exchange of large blocks of data between the processor cores is necessary. This includes mobile phones, networked personal digital assistants (PDAs), networking equipment or general computing equipment where different processor cores share different tasks in a system where data must cross processor boundaries.
As the demand for more powerful computing devices increases, more and more systems are offered that comprise more than just one processor.
There are systems where two or more processors are integrated on the same chip or semiconductor die. A typical example is a SmaitCard that has a main processor and a crypto-processor on the same semiconductor die.
As small handheld devices are becoming more and more popular, the demand for powerful and flexible chips is increasing. A typical example is the cellular phone which in the beginning of its dissemination was just a telephone for voice transmission, i.e. for analog communication. Over the years, additional features have been added and most of today's cellular phones are designed for voice and data services. Additional differentiators are wireless application protocol (WAP) support, paging and short message system (SMS) functionaUty, just to name some of Hie more recent developments. All these features require more powerful processors and quite often even dual-processor or multi-processor chips. h the future, systems handling digital video streams for example will become available. These systems also require powerful and flexible chip sets.
Other examples are integrated circuit cards, such as multi-purpose JavaCards, small handheld devices, such as palm top computers or personal digital assistants (PDAs), etc.
In Ghodrat et al. USP 6266723, a method and a system for optimizing of peripheral component interconnect PCI bus transfers is described., This method and device are particularly provided for optimizing the transfer of data on a bus in a data processing system. For this purpose, the data processing system comprises a central processing unit, a memory subsystem, a bus for receiving bus transactions for transferring data and a device connected to the bus. This device in turn comprises a bus transaction initiator which generates a bus transaction request, a bus transaction optimizer which generates a plurality of bus transaction requests in response to receiving an original bus transaction request, and wherein these requests comprise a high performance bus transaction request and a low-perfomiance bus transaction request. The device also comprises a bus interface unit, which controls a bus transaction in response to receiving a bus transaction request. Melo et al. USP 6212 590 describes a computer system having an integrated bus bridge design with a delayed transaction arbitration mechanism. This is employed within a laptop computer docked to an expansion base with which a high performance can be obtained. The system comprises a secondary bus bridge device in a portable computer and another secondary bus bridge device in an expansion base to which the portable computer docks. A peripheral in the expansion base may initiate a delayed cycle to read or write data to memory through a primary bus bridge device that also couples to a CPU. Both bus bridge devices include an arbiter for controlling arbitration of a peripheral bus that connects both secondary bridge devices. hi Melo et al. USP 6 279 087, a system and method for maintaining coherency and improving performance in a bus bridge supporting write posting operations is described. The bridge provides an interface between a microprocessor coupled to a processor bus, a main memory coupled to a memory bus, and a peripheral device coupled to a peripheral bus. To maintain coherency, the bridge disables posting in certain situations, and flushes posted write transactions before allowing certain read requests to be serviced. At least in Melo et al. USP 6 199 131, a computer system employing optimized delayed transaction arbitration teclmique is described. Disadvantageously, both methods do not allow reading and writing data at the same time. hi Pardillos USP 5 642482, a system for network transmission using a communication coprocessor comprising a microprocessor to implement protocol layer and a microprocessor to manage direct memory access is described. The system for transmitting data between a computer bus and the network includes a general purpose unit connected to the bus and to a network-connected adapter, and further includes a first microprocessor and a unit for transferring frames between the bus and the adapter comprising a dual port memory connected there between. The system further comprises a communication coprocessor connected to the general purpose unit. The communication coprocessor includes a second microprocessor implementing for each comiriunication layer the coιτesponding protocol by providing each frame with control data adapted to the protocol. The second microprocessor is connected to the first microprocessor and the dual port memory. Finally, the system includes a third microprocessor providing direct memory access management of data transfer between the second microprocessor and the dual port memory.
A disadvantage of this solution is a high latency time for block or single transfers, since the entire data block or word has to be written to the dual port memory first before it can be read out by the opposite processor. During all this time, the processors are occupied with the transfers. Another disadvantage is that firmware is involved in both processor blocks to do the transfers. Transfer functions on both sides must also be coordinated.
A further multiprocessor system is described in Honda USP 5 916 296. The dual processor automotive control system described therein comprises a host microprocessor with a read only memory (ROM), a random access memory (RAM), a central processing unit (CPU) and a direct memory access (DMA) controller. The system further comprises a knock- control system microprocessor provided with a ROM, RAM, CPU and DMA controller. The host microprocessor and the knock-control system microprocessor are connected by a bi-directional cornmunication line.
A disadvantage of this solution is that Hie bi-directional communication line between tl e two DMA controllers does not employ a pipelined buffer.
An object of the invention is to provide a data processing device and a method for transferring data form a first processor to a second processor which can exchange data at a time in both directions between both processors.
Another object of tlie invention is to transfer data from tl e one processor to the other processor wherein the latency time, this means the time between the intention to send data and the point of time the bus is available for the transfer, is as short as possible. A further object of tlie invention is to optimize the performance of both processor cores. Tlie data transfer from one processor core to tl e other shall not consume processor core performance and thus avoid tlie reduction of the overall performance of a system.
If the processor clock speeds differ significantly in a system according to the prior art, this will slow down tlie faster processor and reduce the perfonnance of the whole system during tlie data transfer. Thus another object of the invention is to avoid a loss of processor and system performance when the processors run at different clock speeds.
A system for transferring large blocks of data versus a system for transferring only a single word of data requires a different hardware implementation. An object of tlie invention is also to provide a data processing device and a method for transfeιτing data form a first processor to a second processor which can be used as well as for transferring large blocks of data as also for ttansferring a single word.
Once data are transferred from one subsystem with the first processor to tlie other subsystem with tl e second processor, prior art solutions often require an additional process to move the data to tlie desired location within tlie subsystem. Disadvantageously this further reduces processor perfonnance. Therefore, a further object of the invention is to provide a data processing device and a method for transferring data from a first processor to a second processor wherein the transfer of data to tlie desired location within the subsystem does not influence processor performance.
The problem is solved by a data processing device with the features according to tlie independent apparatus claim, essentially comprising: a first processing unit linlced to a first bus, a second processing unit linked to a second bus, a first bus master linked to said first bus, a second bus master linlced to said second bus, communication channels linking said first and said second bus masters to each other, and a controller for tlie data transfer between the two bus masters via tlie coinmunication channels. An appropriate method for transferring data form a first processor to a second processor comprises the features lied out in an independent method claim. This method for transferring data from a first memory of a first processor system to a second memory of a second processor system according to the invention comprises the following steps: the first memory transmits the data via a first bus to a first pipeline controlled by a first bus master with a first clock rate; subsequently, the data are transferred from the first pipeline with the help of a second bus master with a second clock rate via a second bus to tlie second memory.
Advantageous further developments of tlie invention can be seen from tlie features lined out in tlie dependent claims.
The first and tlie second communication channels in tlie data processing device according to an embodiment of the invention comprise buffers. Thus tlie data transfer from one processor core to the other processor core is buffered and therefore the performance of tlie quicker processor is not influenced by tlie perfonnance of tlie slower processor. Therefore the data transfer does not reduce tl e overall perfomiance of tlie superior system.
In another embodiment of tlie data processing device according to tlie invention, each buffer has a first and a second clock input, wherein the first clock input is linlced to tlie first bus master and tlie second clock input is linlced to tlie second bus master. The advantage of this embodiment is, if the processor speeds are significantly different, this is not slowing down tlie faster processor and is not reducing tlie performance of the faster system during tlie data transfer. For example, tlie data can be written into tlie first buffer with tlie clock of tlie first processor and tlie data can be read out from the first buffer with the clock rate of tlie second processor. hi a further embodiment of tlie data processing device according to tlie invention tlie first bus has a first bus width and tlie second bus has a second bus width and tlie first and H e second communication channels comprise an adapting unit for adapting the bus widths. This has tlie advantage that a data transfer is transparent to tlie software. hi a still further embodiment of the data processing device according to the invention tlie first bus has one type of byte order and the second bus has the otlier type of byte order. Furthermore the first and the second communication channels comprise a further adapting unit for adapting tlie byte orders. Thus a data transfer between the processors can be ensured even if both subsystems have different byte orders. For example, if one subsystem works with a little endian configuration and the otlier subsystem with a big endian configuration a communication between both subsystems is still possible.
Furthermore, tlie control unit of the data processing device according to tlie invention can comprise an output register for a single data transfer, whose input is connected to tlie first bus. A multiplexer is switched in one of tlie communication channels and connected to tlie slave access output register. With this, a single data transfer or a block data transfer can be realized.
It is further suggested that in tlie data processing device one of the processing units is a master and the otlier one is a slave. Tlie control unit is connected to tlie master for receiving and transmitting control and status signals.
Advantageously, tlie control unit of the data processing device according to tlie invention comprises an address register generator whose input is connected to the master and whose output is connected to the first bus master, and tlie control unit comprises a further address register generator whose input is connected to the master and whose output is connected to the second bus master.
Furtlienriore, the control unit of tlie data processing device according to the invention can be equipped so that the addresses are incremented automatically. With that, none of the subsystems are loaded with the generation of addresses. hi a further advantageous embodiment, the control unit of tlie data processing device according to the invention can be equipped so that the addresses are generated in ring buffer mode.
Advantageously, the control of the data processing device according to tlie invention unit comprises a word counter connected to the first bus. According to a further embodiment of the invention, tlie control unit is equipped so that the data transfer can be suspended, if tlie buffer is full. With that a buffer overflow and a from that resulting loss of data can be avoided. hi another aspect of the data processing device according to the invention, tlie control unit is equipped so that the bus access load can be controlled such that the bus access load is kept under a predetermined value.
Furthemiore, the data processing device according to the invention can be equipped so that the first processor, which is tlie master, can suspend the data transfer. hi another embodiment of Hie data processing device according to the invention, tlie first bus master is equipped so that it can detect an error regarding address alignment or illegal addresses and forward it to the control unit. hi a further embodiment of the method for transferring data according the invention, the data transfer form the second processor to the first processor comprises tlie following steps: tlie second memory transmits the data via the second bus to a second pipeline with the help of tl e second bus master with the second clock rate. Afterwards tlie data are transferred from tlie second pipeline with tlie help of the first bus master with tlie first clock rate via the first bus to the first memory.
The figure shows a block diagram of a data processing device according to the invention.
The present invention provides an improvement of data exchange in multiprocessor systems. An embodiment of a two processor system with a local master linlced through pipeliniiig to a remote bus master is shown in tlie figure.
The data processing device according to the invention shown in the figure comprises a first processor A, indicated with tlie reference sign 1, which can be a central processing unit (CPU), and a second processor B, indicated with the reference sign 2, which can be for example a digital signal processor (DSP). The first processor A is linlced via a first bus A, indicated with Uie reference sign 5, to a local bus master 3. The second processor B is linlced via a second bus B, indicated with Hie reference sign 6, to a remote bus master 4. Tlie system also comprises a first memory A linked to the first bus 5 and a second memory B linked to the second bus 6. A first subsystem includes the first processor A, the first bus A, tlie first memory A, and tlie local bus master 3. A second subsystem comprises the second processor B, the second bus B, tlie second memory B and the remote bus master 4.
Tlie data transfer is carried out by two communication channels, wherein tlie first communication channel transfers tlie data from the remote bus master 4 to the local bus master 3, and the second communication channel transfers tlie data from the local bus master 3 to tlie remote bus master 4. The first communication channel is also called RX-channel, while the second communication channel is also called TX-channel. The RX-channel comprises a RX pipeline whose input is connected to tlie data output R_data_out of tlie remote bus master 4 and whose data output 7.4 is connected via an adapting unit 20 to the data input L_data_in of tlie local bus master 3. Tlie TX-channel comprises a TX pipeline 8 whose input is connected via a multiplexer 10 and a second adapting unit 21 to the data output L_data_out of the local bus master 3 and whose data output 8.5 is connected to tlie data input R_data_in of the remote bus master 4.
The first adapting unit 20 is provided to convert the data delivered from tlie data output R_data_out of tl e remote bus master 4 in a format which is suitable for the local bus master 3. Especially if tlie remote bus master 4 delivers its output data on a data bus with ml lines and the data bus of tlie local bus master has nl lines, the first adapting unit 20 converts the data so that they fit to tlie data bus of tl e local bus master 3. If the remote bus master 4 delivers its output data R_data_out in a little endian fomiat (a first byte addressing fomiat Icnown in tlie computer industry), but tlie local bus master 3 needs the data in the big endian fomiat (a second byte addressing fomiat Icnown in tlie computer industry), tlie first adapting unit 20 converts the output data R_data_out appropriately. Whether tlie output data R_data_oιιt from tlie remote bus master 4 have to be converted or not is decided by a control unit 9, which is linked to a control input 20.1 of the first adapting unit 20. The second adapting unit 21 is provided to convert the data delivered from tlie data output L_data_out of tlie local bus master 3 in a format which is suitable for tlie remote bus master 4. If tlie local bus master 3 delivers its output data on a data bus with n2 lines whereas tlie data bus of tlie remote bus master has m2 lines tlie second adapting unit 21 converts tlie outgoing data so that they fit to the data bus of the remote bus master 4. If tlie local bus master 3 delivers its output data L_ data_out in a Uttle endian format but the remote bus master 4 needs the data in the big endian format the second adapting unit 21 converts tlie output data L_data_out appropriately. Analogously, this is valid also if die output data L_data_oιιt from tlie local bus master 3 are delivered in tlie big endian format but required from the remote bus master 4 in Hie little endian format. Whether tlie output data L_d ta_out from tlie local bus master 3 have to be converted or not is decided by tlie control unit 9, which is linked to a control input 21.1 of the second adapting unit 21. hi the shown embodiment of the invention, the RX pipeline comprises a first in first out (FIFO) buffer 7 with two clock inputs 7.1 and 7.2. The clock input 7.1 is connected to the remote bus master 4 while the clock input 7.2 is connected to tlie local bus master 3. Ηiereby it is possible to realize an asynclironous data transfer from tlie remote bus master 4 to the local bus master 3. If the clock of the first processor A and tlie clock of tlie second processor B are strongly different, this is not slowing down the faster processor and is not reducing the perfonnance of the faster subsystem during the data transfer, because the clock rates of the processors 1 and 2 are decoupled by the buffer 7. For example, the data can be written into the buffer 7 with the clock of tlie processor B and tlie data can be read out from tlie buffer 7 with tlie clock of tlie processor A.
To avoid a buffer underrun or a buffer overflow the buffer 7 is connected via its buffer control input 7.3 to tlie control output of a RX-control unit 11 of tlie control unit 9. hi general, the RX-control unit 11 controls tlie buffer 7. The RX-control unit 11 gets the status of die received data via the buffer 7 over a status line 7.4.
The TX pipeline comprises a buffer 8 with two clock inputs 8.1 and 8.2, which is also a first in first out buffer. The first clock input 8.1 of the buffer 8 is connected to the remote bus master 4 while the second clock input 8.2 of tlie buffer 8 is connected to the local bus master 3. Thereby it is also possible to realize a asynclironous data transfer from the local bus master 3 to tlie remote bus master 4. If the clock of tlie first processor A and the clock of the second processor B are substantially different, this is not slowing down tlie faster processor and is not reducing the perfonnance of the faster subsystem during tlie data transfer, because tlie clock rates of the two processors 1 and 2 are decoupled by tlie buffer 8. For example, the data can be written into the buffer 8 with the clock of the processor A and tlie data can be read out from tlie buffer 8 with the clock of the processor B.
To avoid a buffer underrun or a buffer overflow of the buffer 8, it is connected over its buffer control input 8.3 with tlie control output of a TX- control unit 12 of tlie control unit 9. In general, the TX-control unit 12 controls the buffer 8. The TX-control unit 11 gets tlie status of the transmitted data via tlie buffer 8 over a status line 8.4. The present invention provides the desired improvement by dedicating the local and the remote bus master 3 and 4 for the two buses 5 and 6 of each processor core 1 and 2. The processor perfonnance is not inhibited since the two bus masters 3 and 4 can do the data transfer during the time tlie processors 1 and 2 do not need tlie buses 5 and 6.
Tlie data pipeline 8 transfers the output data L_data_oιιt on the path from tlie local bus master 3 to tlie remote bus master 4 while the data pipeline 7 transfers tlie output data R_data_out on tlie path from tlie remote bus master 4 to tlie local bus master 3. This is particularly beneficial when one of tlie bus masters 3 or 4 is temporarily not available to receive or transmit data to its dedicated bus 5 or 6, due to the bus 5 or 6 being not available or because tlie other bus 5 or 6 is not able to accept data packets in the same rate they are provided due to different subsystem clock speeds. Tlie arcliitecture using the data pipelines 7 and 8 allows that tl e two clock domains run with independent clock speeds.
Address registers 13 and 14, which cover the full address range of tlie bus A and the bus B, determine the subsystem address the data is transferred to or from and therefore no further data transfer is necessary. This is because the data can directly be transferred from Uie desired source address location to the desired destination address location.
Due to the direct memory access on each processor domain, latency time, when transferring big blocks of data, is reduced to a minimum.
Optionally the data processing unit according to the invention is also capable to transfer a single data word at a time, witliout the overhead of prograrnming tl e complete set of registers. This is possible through a slave access data input register 16 and a slave access data output register 17 located on tlie control unit 9 and connected over a control unit bus 19 to tlie bus A.
The local bus master 3 serves tlie bus A and is called local bus master because it is connected to tlie same processor A which controls the control unit 9 via a control interface 22. The remote bus master 4 serves the bus B. Both bus masters 3 and 4 can also be named as bus interfaces. For example the bus A can be a bus with a 16 bit bus width while the bus B can have a 32 bit bus width.
The data paths of the two busses 5 and 6 are connected via the receive (RX) data pipeline 7 in one direction and the transmit (TX) data pipeline 8 in tlie other direction. Tlie pipelines 7 and 8 serve as buffers if bus A or bus B are not immediately available for receiving or transiirittitig. Writing and reading to and from tlie pipelines 7 and 8 is controlled by the control unit 9. hi parallel to each word transmitted and received over the data pipelines 7 and 8, control and status infoniiation is also transferred to tlie RX-control unit 11 and to the TX- control unit 12, respectively.
The address for tlie remote bus master 4 is generated by tlie remote bus master 4 itself. Only tlie initial block address, also called start address, is sent from tlie control unit 9 to tlie remote bus master 4. This is to avoid employing a pipeline also for the addresses. Since the addresses are incremental, tlie remote bus master 4 increments the address by itself after each transferred word.
The control unit 9 contains registers 13 and 14 for tlie source and destination addresses of tlie data to be transferred to and fro
The confrol unit 9 also contains a word counter 15 to determine tlie number of words to be transferred.
The control unit 9 further comprises a control and status register 18, which allows the controlling processor A to check the status of the transfers and to enable the data transfers via the control units 11 and 12. Finally the control unit 9 contains a slave access data input register 16 and a slave access data output register 17, which allow the processor A to also do single data transfers witliout using the local bus master 3 on bus A.
Having illustrated and described a preferred embodiment for a novel data processing device and a method for data transfer, it is noted that variations and modifications in the device and the method can be made witliout departing from the general concept of the invention or the scope of the appended claims.

Claims

CLAIMS:
1. A data processing device, comprising: a first processing unit (1) linked to a first bus (5), a second processing unit (2) linlced to a second bus (6), a first bus master (3) linked to said first bus (5), a second bus master (4) linlced to said second bus (6), a first and a second coimnunication channel (7, 20, 8, 21) linking said first and said second bus master (3, 4) with each other, and a control unit (9) controlling tlie data fransfer between said first and said second bus master (3, 4) via said first and said second communication channel (7, 20, 8, 21).
2. Data processing device according to claim 1, wherein each of tlie first and the second communication channels (7, 20, 8, 21) includes one or more buffers (7, 8).
3. Data processing device according to claim 2, wherein each buffer (7, 8) has a first and a second clock input (7.1, 7.2, 8.1, 8.2) and wherein said first clock input (7.1, 8.1) is linlced to the first bus master (3) and said second clock input (7.2, 8.2) is linked to tlie second bus master (4).
4. Data processing device according to any preceding claim, wherein tlie first bus (5) has a first bus width (nl, n2) and tlie second bus (6) has a second bus width (ml, m2), and tlie first and tlie second communication channels (7, 20, 8, 21) comprise an adapting unit (20, 21) for adapting tlie bus widths (nl, n2, ml, m2).
5. Data processing device according to any preceding claim, wherein the first bus (5) has a first byte order and the second bus (6) has a second byte order, and tlie first and the second communication channels (7, 20, 8, 21) comprise a further adapting unit (20, 21) for adapting the byte orders.
6. Data processing device according to any preceding claim, wherein tlie control unit (9) comprises an output register (17) for a single data transfer, whose input is connected to tlie first bus (5), and a multiplexer (10) is switched in one of Hie communication channels (8, 21) and connected to Hie output register (17).
7. Data processing device according to any preceding claim, wherein one of the processing units (1, 2) is a master and tlie other one is a slave, and the confrol unit (9) is connected to the master (1) for receiving and transmitting control and status signals.
8. Data processing device according to any preceding claim, wherein tlie control unit (9) comprises an address register generator (13), whose input (13.1) is connected to tlie first processing unit (1) and whose output (13.2) is connected to the second bus master (4), and the control unit (9) comprises a further address register generator (14), whose input (14.1) is connected to tlie first processing unit (1) and whose output (14.2) is connected to tlie first bus master (3).
9. Data processing device according to any preceding claim, wherein tlie control unit (9) is equipped so that the addresses for tlie data which shell be transferred are incremented automatically.
10. Data processing device according to any preceding claim, wherein tlie control unit (9) is equipped so that tlie addresses for the data to be fransferred are generated in ring buffer mode.
11. Data processing device according to any preceding claim, wherein the control unit (9) comprises a word counter (15) connected to the first bus (5).
12. Data processing device according to any of the claims 2 to 11, wherein the control unit (9) is equipped so that tl e data transfer can be suspended if the buffer (7, 8) is full.
13. Data processing device according to any preceding claim, wherein the control unit (9) is equipped so that the bus access load can be controlled such that the bus access load is kept under a predetermined value.
14. Data processing device according to any preceding claim, being equipped so that tlie first processing unit (1), which is tlie master, can suspend the data transfer.
15. Data processing device according to any preceding claim, wherein tlie bus first master (3) is equipped so that it can detect an error regarding address alignment or illegal addresses and forward it to tlie control unit (9).
16. A method for transferring data from a first memory of a first processor system to a second memory of a second processor system, comprising the following steps: said first memory transmits said data via a first bus (5) to a first pipeline (8) with the help of a first bus master (3) with a first clock rate, and said data are fransferred from tlie first pipeline (8) with the help of a second bus master (4) with a second clock rate via a second bus (6) to said second memory.
17. Tlie method according to claim 16, wherein a control unit (9) controls tlie bus access load such that the bus access load is kept under a predetermined value.
8. The method according to claim 16 or 17, the data fransfer fonn tlie second memory to the first memory comprising the following steps: said second memory transiiiits said data via tlie second bus (5) to a second pipeline (7) with tlie help of the second bus master (4) with the second clock rate, and said data are transferred from the second pipeline (7) with the help of tlie first bus master (3) with the first clock rate via the first bus (3) to said first memory.
PCT/IB2004/050197 2003-03-12 2004-03-03 Data processing device and method for transferring data WO2004081803A1 (en)

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