WO2004084225A1 - Method and apparatus for establishing and maintaining desired read latency in high-speed dram - Google Patents
Method and apparatus for establishing and maintaining desired read latency in high-speed dram Download PDFInfo
- Publication number
- WO2004084225A1 WO2004084225A1 PCT/US2004/007980 US2004007980W WO2004084225A1 WO 2004084225 A1 WO2004084225 A1 WO 2004084225A1 US 2004007980 W US2004007980 W US 2004007980W WO 2004084225 A1 WO2004084225 A1 WO 2004084225A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- count value
- read
- clock signal
- counter
- adjusted
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/2254—Calibration
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Databases & Information Systems (AREA)
- Dram (AREA)
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP04757495.9A EP1604370B1 (en) | 2003-03-18 | 2004-03-16 | Method and apparatus for establishing and maintaining desired read latency in high-speed dram |
JP2006501236A JP4444277B2 (en) | 2003-03-18 | 2004-03-16 | Method and apparatus for establishing and maintaining a desired read latency in a high speed DRAM |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/389,807 US6762974B1 (en) | 2003-03-18 | 2003-03-18 | Method and apparatus for establishing and maintaining desired read latency in high-speed DRAM |
US10/389,807 | 2003-03-18 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2004084225A1 true WO2004084225A1 (en) | 2004-09-30 |
Family
ID=32681813
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2004/007980 WO2004084225A1 (en) | 2003-03-18 | 2004-03-16 | Method and apparatus for establishing and maintaining desired read latency in high-speed dram |
Country Status (6)
Country | Link |
---|---|
US (2) | US6762974B1 (en) |
EP (1) | EP1604370B1 (en) |
JP (1) | JP4444277B2 (en) |
KR (1) | KR100701924B1 (en) |
CN (1) | CN1788321A (en) |
WO (1) | WO2004084225A1 (en) |
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US8019919B2 (en) | 2007-09-05 | 2011-09-13 | International Business Machines Corporation | Method for enhancing the memory bandwidth available through a memory module |
US7930469B2 (en) | 2008-01-24 | 2011-04-19 | International Business Machines Corporation | System to provide memory system power reduction without reducing overall memory system performance |
US7925826B2 (en) | 2008-01-24 | 2011-04-12 | International Business Machines Corporation | System to increase the overall bandwidth of a memory channel by allowing the memory channel to operate at a frequency independent from a memory device frequency |
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US7770077B2 (en) | 2008-01-24 | 2010-08-03 | International Business Machines Corporation | Using cache that is embedded in a memory hub to replace failed memory cells in a memory subsystem |
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US8140936B2 (en) | 2008-01-24 | 2012-03-20 | International Business Machines Corporation | System for a combined error correction code and cyclic redundancy check code for a memory channel |
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JP6451505B2 (en) * | 2015-05-28 | 2019-01-16 | 株式会社ソシオネクスト | Reception circuit, reception circuit timing adjustment method, and semiconductor device |
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US6687185B1 (en) * | 2002-08-29 | 2004-02-03 | Micron Technology, Inc. | Method and apparatus for setting and compensating read latency in a high speed DRAM |
-
2003
- 2003-03-18 US US10/389,807 patent/US6762974B1/en not_active Expired - Fee Related
-
2004
- 2004-03-16 EP EP04757495.9A patent/EP1604370B1/en not_active Expired - Lifetime
- 2004-03-16 WO PCT/US2004/007980 patent/WO2004084225A1/en active Application Filing
- 2004-03-16 KR KR1020057017624A patent/KR100701924B1/en not_active IP Right Cessation
- 2004-03-16 JP JP2006501236A patent/JP4444277B2/en not_active Expired - Fee Related
- 2004-03-16 CN CNA2004800130885A patent/CN1788321A/en active Pending
- 2004-05-24 US US10/851,081 patent/US6930955B2/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
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US6337589B1 (en) | 1997-09-11 | 2002-01-08 | Mitsubishi Denki Kabushiki Kaisha | Phase-lock loop with independent phase and frequency adjustments |
US6240042B1 (en) | 1999-09-02 | 2001-05-29 | Micron Technology, Inc. | Output circuit for a double data rate dynamic random access memory, double data rate dynamic random access memory, method of clocking data out from a double data rate dynamic random access memory and method of providing a data strobe signal |
Also Published As
Publication number | Publication date |
---|---|
US20040213074A1 (en) | 2004-10-28 |
CN1788321A (en) | 2006-06-14 |
KR20060002832A (en) | 2006-01-09 |
US6762974B1 (en) | 2004-07-13 |
JP2006520978A (en) | 2006-09-14 |
EP1604370B1 (en) | 2013-11-13 |
KR100701924B1 (en) | 2007-04-02 |
US6930955B2 (en) | 2005-08-16 |
EP1604370A1 (en) | 2005-12-14 |
JP4444277B2 (en) | 2010-03-31 |
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