WO2004086219A3 - Method and apparatus for branch prediction based on branch targets - Google Patents

Method and apparatus for branch prediction based on branch targets Download PDF

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Publication number
WO2004086219A3
WO2004086219A3 PCT/US2004/008438 US2004008438W WO2004086219A3 WO 2004086219 A3 WO2004086219 A3 WO 2004086219A3 US 2004008438 W US2004008438 W US 2004008438W WO 2004086219 A3 WO2004086219 A3 WO 2004086219A3
Authority
WO
WIPO (PCT)
Prior art keywords
branch
entry
instruction
information representative
branch instruction
Prior art date
Application number
PCT/US2004/008438
Other languages
French (fr)
Other versions
WO2004086219A2 (en
WO2004086219A9 (en
Inventor
Thang M Tran
Ravi Pratap Singh
Deepa Duraiswamy
Sriknanth Kannan
Original Assignee
Analog Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Analog Devices Inc filed Critical Analog Devices Inc
Priority to JP2006507365A priority Critical patent/JP2006520964A/en
Priority to EP04757879A priority patent/EP1625493A2/en
Publication of WO2004086219A2 publication Critical patent/WO2004086219A2/en
Publication of WO2004086219A9 publication Critical patent/WO2004086219A9/en
Publication of WO2004086219A3 publication Critical patent/WO2004086219A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61P—SPECIFIC THERAPEUTIC ACTIVITY OF CHEMICAL COMPOUNDS OR MEDICINAL PREPARATIONS
    • A61P31/00—Antiinfectives, i.e. antibiotics, antiseptics, chemotherapeutics
    • A61P31/04—Antibacterial agents
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3844—Speculative instruction execution using dynamic branch prediction, e.g. using branch history tables

Abstract

Methods and apparatus are provided for branch prediction in a digital processor. A method includes providing a branch target buffer having a tag array and a data array, wherein each entry in the tag array provides an index to a corresponding entry in the data array, storing in a selected entry in the tag array information representative of a branch target of a current branch instruction, storing in a corresponding entry in the data array information representative of a branch target of a next branch instruction, and providing the information representative of the branch target of the next branch instruction in response to a match to an entry in the tag array. The information representative of the branch target of the next branch instruction may include a taken branch target address of the next branch instruction and an offset value. The offset value may represent an address of a next sequential instruction following the next branch instruction.
PCT/US2004/008438 2003-03-21 2004-03-19 Method and apparatus for branch prediction based on branch targets WO2004086219A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2006507365A JP2006520964A (en) 2003-03-21 2004-03-19 Method and apparatus for branch prediction based on branch target
EP04757879A EP1625493A2 (en) 2003-03-21 2004-03-19 Method and apparatus for branch prediction based on branch targets

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/394,820 2003-03-21
US10/394,820 US7266676B2 (en) 2003-03-21 2003-03-21 Method and apparatus for branch prediction based on branch targets utilizing tag and data arrays

Publications (3)

Publication Number Publication Date
WO2004086219A2 WO2004086219A2 (en) 2004-10-07
WO2004086219A9 WO2004086219A9 (en) 2004-12-09
WO2004086219A3 true WO2004086219A3 (en) 2006-01-12

Family

ID=32988465

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/008438 WO2004086219A2 (en) 2003-03-21 2004-03-19 Method and apparatus for branch prediction based on branch targets

Country Status (5)

Country Link
US (1) US7266676B2 (en)
EP (1) EP1625493A2 (en)
JP (1) JP2006520964A (en)
TW (1) TWI319533B (en)
WO (1) WO2004086219A2 (en)

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US7386679B2 (en) * 2004-04-15 2008-06-10 International Business Machines Corporation System, method and storage medium for memory management
CN101002169A (en) 2004-05-19 2007-07-18 Arc国际（英国）公司 Microprocessor architecture
US7328332B2 (en) * 2004-08-30 2008-02-05 Texas Instruments Incorporated Branch prediction and other processor improvements using FIFO for bypassing certain processor pipeline stages
US7836288B2 (en) * 2004-09-14 2010-11-16 Arm Limited Branch prediction mechanism including a branch prediction memory and a branch prediction cache
KR20080007430A (en) * 2005-02-11 2008-01-21 샌디스크 아이엘 엘티디 Nand flash memory system architecture
US8971461B2 (en) 2005-06-01 2015-03-03 Qualcomm Incorporated CQI and rank prediction for list sphere decoding and ML MIMO receivers
US7747088B2 (en) 2005-09-28 2010-06-29 Arc International (Uk) Limited System and methods for performing deblocking in microprocessor-based video codec applications
US7827392B2 (en) * 2006-06-05 2010-11-02 Qualcomm Incorporated Sliding-window, block-based branch target address cache
US8935517B2 (en) * 2006-06-29 2015-01-13 Qualcomm Incorporated System and method for selectively managing a branch target address cache of a multiple-stage predictor
US20080097914A1 (en) * 2006-10-24 2008-04-24 Kent Dicks Systems and methods for wireless processing and transmittal of medical data through multiple interfaces
EP2106584A1 (en) * 2006-12-11 2009-10-07 Nxp B.V. Pipelined processor and compiler/scheduler for variable number branch delay slots
US7640400B2 (en) * 2007-04-10 2009-12-29 International Business Machines Corporation Programmable data prefetching
US7913068B2 (en) * 2008-02-21 2011-03-22 International Business Machines Corporation System and method for providing asynchronous dynamic millicode entry prediction
US7941653B2 (en) * 2008-12-04 2011-05-10 Analog Devices, Inc. Jump instruction having a reference to a pointer for accessing a branch address table
US9946545B2 (en) * 2010-11-16 2018-04-17 Arm Limited Buffer store with a main store and and auxiliary store
US8886920B2 (en) * 2011-05-13 2014-11-11 Oracle International Corporation Associating tag to branch instruction to access array storing predicted target addresses for page crossing targets for comparison with resolved address at execution stage
US9250912B2 (en) * 2012-06-12 2016-02-02 International Business Machines Corporation Fast index tree for accelerated branch prediction
US9250909B2 (en) * 2012-06-12 2016-02-02 International Business Machines Corporation Fast index tree for accelerated branch prediction
US20140250289A1 (en) * 2013-03-01 2014-09-04 Mips Technologies, Inc. Branch Target Buffer With Efficient Return Prediction Capability
US9489204B2 (en) * 2013-03-15 2016-11-08 Qualcomm Incorporated Method and apparatus for precalculating a direct branch partial target address during a misprediction correction process
JP6273718B2 (en) * 2013-08-13 2018-02-07 富士通株式会社 Arithmetic processing device and control method of arithmetic processing device
US10831491B2 (en) * 2018-06-29 2020-11-10 Intel Corporation Selective access to partitioned branch transfer buffer (BTB) content
US11762660B2 (en) * 2020-06-23 2023-09-19 Ampere Computing Llc Virtual 3-way decoupled prediction and fetch

Citations (2)

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Publication number Priority date Publication date Assignee Title
US5506976A (en) * 1993-12-24 1996-04-09 Advanced Risc Machines Limited Branch cache
US6185675B1 (en) * 1997-10-24 2001-02-06 Advanced Micro Devices, Inc. Basic block oriented trace cache utilizing a basic block sequence buffer to indicate program order of cached basic blocks

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US5142634A (en) * 1989-02-03 1992-08-25 Digital Equipment Corporation Branch prediction
US5608886A (en) * 1994-08-31 1997-03-04 Exponential Technology, Inc. Block-based branch prediction using a target finder array storing target sub-addresses
US5732253A (en) * 1994-10-18 1998-03-24 Cyrix Corporation Branch processing unit with target cache storing history for predicted taken branches and history cache storing history for predicted not-taken branches
US5864697A (en) * 1996-06-28 1999-01-26 Texas Instruments Incorporated Microprocessor using combined actual and speculative branch history prediction
US6119222A (en) * 1996-12-23 2000-09-12 Texas Instruments Incorporated Combined branch prediction and cache prefetch in a microprocessor
TW357318B (en) * 1997-03-18 1999-05-01 Ind Tech Res Inst Branching forecast and reading device for unspecified command length extra-purity pipeline processor
US5964870A (en) * 1997-09-22 1999-10-12 Intel Corporation Method and apparatus for using function context to improve branch
US6446197B1 (en) * 1999-10-01 2002-09-03 Hitachi, Ltd. Two modes for executing branch instructions of different lengths and use of branch control instruction and register set loaded with target instructions

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5506976A (en) * 1993-12-24 1996-04-09 Advanced Risc Machines Limited Branch cache
US6185675B1 (en) * 1997-10-24 2001-02-06 Advanced Micro Devices, Inc. Basic block oriented trace cache utilizing a basic block sequence buffer to indicate program order of cached basic blocks

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
REINMAN G ET AL: "A SCALABLE FRONT-END ARCHITECTURE FOR FAST INSTRUCTION DELIVERY", PROCEEDINGS OF THE 26TH INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE. ATLANTA, GA, MAY 2 - 4, 1999, INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE. (ISCA), LOS ALAMITOS, CA : IEEE COMP. SOC, US, vol. CONF. 26, 2 May 1999 (1999-05-02), pages 234 - 245, XP000887621, ISBN: 0-7695-0171-0 *

Also Published As

Publication number Publication date
TW200422864A (en) 2004-11-01
EP1625493A2 (en) 2006-02-15
JP2006520964A (en) 2006-09-14
TWI319533B (en) 2010-01-11
WO2004086219A2 (en) 2004-10-07
US20040186985A1 (en) 2004-09-23
WO2004086219A9 (en) 2004-12-09
US7266676B2 (en) 2007-09-04

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